JPS61145905A - Fm demodulation circuit - Google Patents

Fm demodulation circuit

Info

Publication number
JPS61145905A
JPS61145905A JP26816184A JP26816184A JPS61145905A JP S61145905 A JPS61145905 A JP S61145905A JP 26816184 A JP26816184 A JP 26816184A JP 26816184 A JP26816184 A JP 26816184A JP S61145905 A JPS61145905 A JP S61145905A
Authority
JP
Japan
Prior art keywords
signal
circuit
capacitor
alternately
demodulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26816184A
Other languages
Japanese (ja)
Other versions
JPH0216043B2 (en
Inventor
Hiroyuki Hatano
裕之 秦野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP26816184A priority Critical patent/JPS61145905A/en
Publication of JPS61145905A publication Critical patent/JPS61145905A/en
Publication of JPH0216043B2 publication Critical patent/JPH0216043B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Stereo-Broadcasting Methods (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE:To realize stable FM demodulation with less number of components by providing a couple of differential circuits switched alternately with two FM signals opposite to each other and charging/discharging a capacitor in response to said switching. CONSTITUTION:FM signals opposite to each other in phase are fed respectively to input terminal 32, 34, transistor (TR)24, 26 repeat conduction/nonconduction alternately by an FM signal A1 and TRs 28, 30 repeat conduction/nonconduction alternately by an FM signal A2. A charge/discharge current flows to a capacitor 46 and charge/discharge voltages are generated at points B and C respectively. A switching current I flows to a collector of the TRs 26, 28 in response to the charge/discharge stated as above, the current flows to a resistor 56 by the current mirror effect of TRs 48, 50 and a demodulated output Vo is generated at an output terminal 58.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、いわゆるパルスカウント復調方式のFM復
調回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FM demodulation circuit using a so-called pulse count demodulation method.

〔従来の技術〕[Conventional technology]

パルスカウント方式のFM(周波数変調)復調回路は、
第3図に示すように、入力端子2に加えられたFM信号
をトリガ回路4に入力してそのFM信号周期に同期した
トリガパルスに変換し、このトリガパルスで単安定マル
チバイブレーク6をトリガし、出力端子8からFM信号
の復調パルスを取り出すものであや。そして、FM信号
の復調パルスを低域フィルタ10を介して平滑した後、
その出力端子12から低周波信号が得られる。
The pulse count type FM (frequency modulation) demodulation circuit is
As shown in Figure 3, the FM signal applied to the input terminal 2 is input to the trigger circuit 4 and converted into a trigger pulse synchronized with the FM signal cycle, and this trigger pulse triggers the monostable multi-bi break 6. , which extracts the demodulated pulse of the FM signal from the output terminal 8. After smoothing the demodulated pulse of the FM signal through the low-pass filter 10,
A low frequency signal is obtained from its output terminal 12.

すなわち、入力端子2に第4図のAに示すFM信号が加
えられると、トリガ回路4は、その立ち上がりおよび立
ち下がりに同期した第4図のBに示すトリガパルスを発
生し、このトリガパルスによってマルチバイブレーク6
は、第4図のCに示す復調パルスを発生する。このパル
スの高レベルの時間t4は一定となるが、時間TがFM
信号の周波数に応じたものとなるので、このパルス信号
を低域フィルタ10を通過させると、FM信号に応じた
レベルを持つ低周波信号が得られる。
That is, when the FM signal shown in A in FIG. 4 is applied to the input terminal 2, the trigger circuit 4 generates a trigger pulse shown in B in FIG. 4 in synchronization with the rising and falling edges of the FM signal, and this trigger pulse causes multivi break 6
generates a demodulation pulse shown at C in FIG. The high level time t4 of this pulse is constant, but the time T is FM
Since the pulse signal corresponds to the frequency of the signal, when this pulse signal is passed through the low-pass filter 10, a low-frequency signal having a level corresponding to the FM signal is obtained.

(発明が解決しようとする問題点〕 このようなFMlj調回路では、トリガ回路4およびマ
ルチバイブレータ6の構成素子数が多く、回路構成が複
雑であり、半導体集積回路で構成する場合に製造コスト
が高くなるとともに、回路構成が複雑化し、動作が不安
定になるなどの欠点があった。
(Problems to be Solved by the Invention) In such an FMlj type circuit, the trigger circuit 4 and the multivibrator 6 have a large number of components, the circuit configuration is complicated, and the manufacturing cost is high when configured with a semiconductor integrated circuit. As the cost increases, the circuit configuration becomes more complex and operation becomes unstable.

そこで、この発明は、少ない構成素子数で安定したFM
復調を実現するFM復調回路を提供しようとするもので
ある。
Therefore, this invention provides stable FM with a small number of components.
The present invention attempts to provide an FM demodulation circuit that realizes demodulation.

〔問題点を解決するための手段〕[Means for solving problems]

すなわち、この発明は、互いに逆相関係にある2つのF
M信号によって交互にスイッチングする一対の差動回路
を設け、各差動回路の動作電流の流出側間に、各差動回
路のスイッチング動作に応動して充電状態または放電状
態に切り換えられるコンデンサを接続してなるものであ
る。
In other words, this invention provides two F
A pair of differential circuits that alternately switch depending on the M signal is provided, and a capacitor that can be switched to a charging state or a discharging state in response to the switching operation of each differential circuit is connected between the operating current outflow side of each differential circuit. This is what happens.

〔作 用〕[For production]

したがって、この発明は、一対の差動回路をFM信号で
交互にスイッチングさせ、このスイッチングに応動して
コンデンサを充放電させ、その電位変化と、差動回路の
スイッチング電流の合成によってFM信号周波数(周期
)に応じたデユーティを持つパルス出力を得る。
Therefore, the present invention alternately switches a pair of differential circuits using an FM signal, charges and discharges a capacitor in response to this switching, and combines the potential change and the switching current of the differential circuit to generate an FM signal frequency ( Obtains a pulse output with a duty according to the period).

〔実施例〕〔Example〕

以下、この発明の実施例を図面を参照して詳細に説明す
る。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図はこの発明のFM復調回路の実施例を示している
FIG. 1 shows an embodiment of the FM demodulation circuit of the present invention.

第1図において、このFM復調回路には一対の差動回路
20.22が設置され、差動回路20はエミッタを共通
にした一対のトランジスタ24.26、差動回路22は
エミッタを共通にした一対のトランジスタ28.30で
それぞれ構成されている。トランジスタ24.30の各
ベースには、入力端子32.34が形成され、互いに逆
相関係にあるFM信号が加えられ、トランジスタ26.
28のベースには、電圧源36から一定のバイアス電圧
■□が加えられている。
In FIG. 1, a pair of differential circuits 20 and 22 are installed in this FM demodulation circuit, the differential circuit 20 is a pair of transistors 24 and 26 that have a common emitter, and the differential circuit 22 has a pair of transistors that have a common emitter. Each transistor is composed of a pair of transistors 28 and 30. Input terminals 32.34 are formed at the bases of each of the transistors 24.30, and FM signals having mutually opposite phases are applied to the bases of the transistors 26.30.
A constant bias voltage □ is applied to the base of 28 from a voltage source 36.

トランジスタ24.26のエミッタは、動作電流を流す
ためのトランジスタ38:#3よび抵抗40を介して接
地され、同様に、トランジスタ28.30のエミッタも
動作電流を流すためのトランジスタ42および抵抗44
を介して接地され、また、トランジスタ24.26のエ
ミッタとトランジスタ28.30のエミッタとの間には
、コンデンサ46が接続されている。各トランジスタ3
8.42には、共通のバイアス電圧源からバイアス電圧
Vll□が加えられている。
The emitters of the transistors 24, 26 are grounded via a transistor 38: #3 and a resistor 40 for carrying an operating current, and similarly, the emitters of the transistors 28, 30 are grounded via a transistor 42 and a resistor 44 for carrying an operating current.
A capacitor 46 is connected between the emitters of transistors 24.26 and 28.30. Each transistor 3
A bias voltage Vll□ is applied to 8.42 from a common bias voltage source.

そして、トランジスタ24.30のコレクタと、接地点
との間には、電源が接続され、駆動電圧Vccが加えら
れ、かつ、トランジスタ26.28のコレクタ側には、
復調出力を取り出すための出力回路を構成するトランジ
スタ48.5oおよび抵抗52.54からなる電流ミラ
ー回路が設置基れている。すなわち、トランジスタ5o
のコレクタには、接地点との間に負荷抵抗56が接続さ
れているとともに、出力端子58が形成されている。
A power supply is connected between the collector of the transistor 24.30 and the ground point, and a driving voltage Vcc is applied to the collector side of the transistor 26.28.
A current mirror circuit consisting of a transistor 48.5o and a resistor 52.54 constituting an output circuit for taking out a demodulated output is installed. That is, transistor 5o
A load resistor 56 is connected between the collector and a ground point, and an output terminal 58 is formed.

以上の構成に基づき、その動作を第2図を参照して説明
する。
Based on the above configuration, its operation will be explained with reference to FIG.

入力端子32.34には、第2図のAに示す互いに逆相
関係にあるFM信号が加えられ、このFM信号において
、VWIはその中点電圧を示す。
The input terminals 32 and 34 are supplied with FM signals shown in A in FIG. 2 that are in opposite phases to each other, and VWI indicates the midpoint voltage of the FM signals.

トランジスタ24.26はFM信号A1で交互に導通、
非導通を繰り返し、トランジスタ28.30はFM信号
A2で交互に導通、非導通を繰り返す。このスイッチン
グ動作によって、コンデンサ46には充放電電流が流れ
、第1図中のB点には、第2図のBに示す充放電電圧、
その0点には、第2図のCに示す充放電電圧が発生する
。これら充放電電圧波形の振幅は、■で与えられる。
Transistors 24 and 26 are alternately conductive with the FM signal A1,
The transistors 28 and 30 alternately become conductive and non-conductive in response to the FM signal A2. Due to this switching operation, a charging/discharging current flows through the capacitor 46, and at point B in FIG. 1, a charging/discharging voltage shown at B in FIG.
At the zero point, a charging/discharging voltage shown as C in FIG. 2 is generated. The amplitude of these charge/discharge voltage waveforms is given by ■.

このような充放電に応動してトランジスタ26.28の
コレクタには、スイッチング電流■が流れ、この電流は
トランジスタ48.50の電流ミラー効果によって抵抗
56に流れ、出力端子58には第2図のDに示す復調出
力v0が発生する。
In response to such charging and discharging, a switching current ■ flows through the collectors of the transistors 26 and 28, and this current flows through the resistor 56 due to the current mirror effect of the transistors 48 and 50, and the output terminal 58 has the voltage shown in FIG. A demodulated output v0 shown in D is generated.

ここで、第2図のDに示す復調出力■。において、パル
ス幅をTP 、その周期はFM信号周期Tの1/2の関
係にあり、抵抗56の抵抗値をRL、抵抗56に流れる
出力電流を■、FM信号の搬送周波数をrcとすると、
復調出力■。は、vo = I ・RL  ・ (CT
/2−TP )−TP )/ (T/2) =I−RL  ・ (2/T) ・ (T/2−27F) =I−RL ・ (1−−4Tp / T )=I ・
RL  ・ (1−4TP  re  )・ ・ ・(
1) となり、検波効率aVo/afは、 avo/ar=−41・RL −TP ・・・(2)と
なる。したがって、復調出力■。は、■。=−4■・R
L’TP  ・Δf ・・・(3)となる。ただし、Δ
fは周波数偏移である。
Here, the demodulated output ■ shown in D in FIG. In, the pulse width is TP, its period is 1/2 of the FM signal period T, the resistance value of the resistor 56 is RL, the output current flowing through the resistor 56 is , and the carrier frequency of the FM signal is rc.
Demodulation output■. is vo = I・RL・(CT
/2-TP )-TP )/ (T/2) = I-RL ・ (2/T) ・ (T/2-27F) = I-RL ・ (1--4Tp / T ) = I ・
RL・(1-4TPre)・・・・(
1), and the detection efficiency aVo/af is avo/ar=-41·RL -TP (2). Therefore, the demodulated output ■. ■. =-4■・R
L'TP .DELTA.f (3). However, Δ
f is the frequency deviation.

また、コンデンサ46の容量をCとすると、T、−〇−
V/Iであるから(■は第2図のBのピーク値)、復調
出力■。は、 Vo=  4I−RL (C・V/I)  ・Δf= 
4Rt’C・■・Δf  ・・・(4)となる。ただし
、この場合、トランジスタの遅延時間は無視している。
Also, if the capacitance of the capacitor 46 is C, then T, -〇-
Since V/I (■ is the peak value of B in FIG. 2), the demodulated output is ■. is, Vo= 4I-RL (C・V/I) ・Δf=
4Rt'C・■・Δf (4). However, in this case, the delay time of the transistor is ignored.

式(4)から明らかなように、復調出力■。は、搬送周
波数feの周波数偏移Δfに比例したものとなるので、
低域フィルタを通過させることにより、低周波信号を再
生することができる。
As is clear from equation (4), the demodulated output ■. is proportional to the frequency deviation Δf of the carrier frequency fe, so
A low frequency signal can be reproduced by passing it through a low pass filter.

このようなFM復調回路では、少ない素子数でFM復調
が得られるとともに、減電圧特性も良好になる。また、
コンデンサ46は、30pF程度で数MHzのFMui
fiが可能であるため、半導体集積回路上の容量素子で
充当することができ、回路構成の簡略化が実現される。
In such an FM demodulation circuit, FM demodulation can be obtained with a small number of elements, and the voltage reduction characteristics are also improved. Also,
The capacitor 46 is approximately 30 pF and several MHz FMui.
Since fi is possible, a capacitive element on a semiconductor integrated circuit can be used, and the circuit configuration can be simplified.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明によれば、少ない素子数
で安定したパルスカウント方式のFM復調を実現するこ
とができる。
As described above, according to the present invention, stable pulse count type FM demodulation can be realized with a small number of elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明のFM復調回路の実施例を示す回路図
、第2図はその動作波形を示す説明図、第3図は従来の
FM復調回路を示すブロック図、第4図はその動作波形
を示す説明図である。 20.22・・・差動回路、46・・・コンデンサ。 第2図 第3図 第4図
Fig. 1 is a circuit diagram showing an embodiment of the FM demodulation circuit of the present invention, Fig. 2 is an explanatory diagram showing its operating waveforms, Fig. 3 is a block diagram showing a conventional FM demodulation circuit, and Fig. 4 is its operation. It is an explanatory diagram showing a waveform. 20.22...differential circuit, 46...capacitor. Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 互いに逆相関係にある2つのFM信号によって交互にス
イッチングする一対の差動回路を設け、各差動回路の動
作電流の流出側間に、各差動回路のスイッチング動作に
応動して充電状態または放電状態に切り換えられるコン
デンサを接続してなることを特徴とするFM復調回路。
A pair of differential circuits are provided that alternately switch depending on two FM signals having an antiphase relationship with each other, and between the operating current outflow sides of each differential circuit, the charging state or An FM demodulation circuit characterized by connecting a capacitor that can be switched to a discharge state.
JP26816184A 1984-12-19 1984-12-19 Fm demodulation circuit Granted JPS61145905A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26816184A JPS61145905A (en) 1984-12-19 1984-12-19 Fm demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26816184A JPS61145905A (en) 1984-12-19 1984-12-19 Fm demodulation circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP9299891A Division JPH04261203A (en) 1991-03-30 1991-03-30 Fm demodulation circuit

Publications (2)

Publication Number Publication Date
JPS61145905A true JPS61145905A (en) 1986-07-03
JPH0216043B2 JPH0216043B2 (en) 1990-04-16

Family

ID=17454749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26816184A Granted JPS61145905A (en) 1984-12-19 1984-12-19 Fm demodulation circuit

Country Status (1)

Country Link
JP (1) JPS61145905A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6467012A (en) * 1987-09-07 1989-03-13 Toshiba Corp Pulse count system fm demodulation circuit
US5138273A (en) * 1989-10-06 1992-08-11 Kabushiki Kaisha Toshiba FM demodulator

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2809479A1 (en) 2012-03-30 2013-09-30 Certainteed Corporation Roofing composite including dessicant and method of thermal energy management of a roof by reversible sorption and desorption of moisture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54158153A (en) * 1978-06-02 1979-12-13 Nec Corp Fm demodulating circuit
JPS5836525A (en) * 1981-08-27 1983-03-03 株式会社ニコン Corner angle mirror
JPS5928285A (en) * 1982-08-03 1984-02-14 Nec Corp Cache buffer controller

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54158153A (en) * 1978-06-02 1979-12-13 Nec Corp Fm demodulating circuit
JPS5836525A (en) * 1981-08-27 1983-03-03 株式会社ニコン Corner angle mirror
JPS5928285A (en) * 1982-08-03 1984-02-14 Nec Corp Cache buffer controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6467012A (en) * 1987-09-07 1989-03-13 Toshiba Corp Pulse count system fm demodulation circuit
US5138273A (en) * 1989-10-06 1992-08-11 Kabushiki Kaisha Toshiba FM demodulator
WO1993017491A1 (en) * 1989-10-06 1993-09-02 Hiroya Itoh Fm demodulation circuit

Also Published As

Publication number Publication date
JPH0216043B2 (en) 1990-04-16

Similar Documents

Publication Publication Date Title
US4525682A (en) Biased current mirror having minimum switching delay
US3924202A (en) Electronic oscillator
US4714900A (en) Current output circuit having well-balanced output currents of opposite polarities
JPS61145905A (en) Fm demodulation circuit
US4006417A (en) Tachometer
US5262690A (en) Variable delay clock circuit
US6967508B2 (en) Compact frequency doubler/multiplier circuitry
US6483356B2 (en) Sinusoidal signal generating circuit providing small phase difference with respect to reference signal and apparatus for driving oscillating element with circuit
JPH02305103A (en) Fm demodulator
JP3697678B2 (en) V / F conversion circuit
US3076152A (en) Stabilized duty cycle modulated multivibrator
US3566301A (en) Multivibrator with linearly variable voltage controlled duty cycle
JPH04261203A (en) Fm demodulation circuit
JP2838212B2 (en) Sawtooth oscillator stage
US3665216A (en) Pulse width modulation detector
JPS6410134B2 (en)
JPH0342010B2 (en)
JP3288612B2 (en) Semiconductor circuit
JPS61227406A (en) Fm modulation-demodulation circuit
JP2821612B2 (en) Output circuit
JPS61248604A (en) Bias circuit
JPH0821835B2 (en) Voltage controlled oscillator
RU2028724C1 (en) Former of saw-tooth pulses of double frequency
JPH0612868B2 (en) Pulse generator
JPH04301904A (en) Pulse count type fm detection circuit

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term