JPS5924460B2 - Central processing unit restart device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses a watchdog timer (hereinafter referred to as WD) when restarting a central processing unit (hereinafter referred to as CPU).
This invention relates to a restart device that distinguishes between an abnormality signal output from a CPU (abbreviated as T) caused by external noise and an abnormality caused by the CPU itself.

Conventionally, as a method for detecting a CpU abnormality, a method using WDT has been used.

This method will be explained using FIGS. 1 to 3. In FIG. 1, the WD is
WDT2, which outputs a reset signal to T2, has a timer that is always working.This timer is reset each time a reset signal is input, and if the reset signal is not input within time T1 set to WDT2, a CPU error occurs. As a result, an abnormal signal was output to the outside, causing the system to go down.

FIG. 2 shows this timing relationship.

A indicates the timing at which a reset signal is output from the CPUI every WDT2VC time T2, and B indicates the J timer of the WDT2, which sets the time T1. This timer time T
1 is set longer than time T2. W from CPUUI
A reset signal is output to DT2 every time T2, and WDT2
However, if the reset signal is not output for some reason, an abnormality signal is output after a fixed time T1, which is the time when the last reset signal was output. As shown in Figure 3, the CPU outputs data to the VWDT2 by incorporating a program to reset the WDT2 in the middle of the program, and then running this program for a certain period of time T.
This can be done by cyclically starting every 2 seconds. If the CPUI operates normally, this program will also operate normally and output a reset signal to WDT2 at certain fixed time intervals, but if this program does not run for some reason, WDT2 will will output an abnormal signal and the system will go down. The cause of this is the CPU
There are two causes for the CPU malfunction: one is due to its own failure or a failure of the equipment, and the other is external noise such as noise from the primary power line or signal line noise, and these noises cause the CPU to malfunction. Conventionally, any of these causes would result in a system down.V) It was not immediately possible to distinguish between these causes, and a great deal of effort was expended on recovery. In the case of a failure of the CPU itself or equipment, humans must intervene to repair it, but in the case of external noise, the CPU
Since this is not a failure of the U or the device, there is no problem in starting up the system immediately, but it is not desirable for the entire system to stop functioning every time there is external noise. The present invention has been made in view of the above circumstances, and its purpose is to provide a CPU restart device that distinguishes between a CPU abnormality signal output from a WDT that is due to a failure of the CPU main body, and one that is due to external noise. That is what it is.

The present invention will be explained in detail based on FIGS. 4 and 5.

In FIG. 4, the restart circuit 3 enclosed by a dotted line in the configuration shown in FIG. 1 is given a power D, and is configured in a loop together with the CPU1 and the WDT2. In the restart circuit 3, the first timer section 31 sets a time T for making other control devices (not shown) recognize the CpU abnormal signal inputted to the WDT 2.
A is set, and after the second timer section 32 and start output section 33 output a restart signal to the CPU1,
The predicted time TB until the timer operates and the CPU abnormality signal comes again is set. The logical product circuit AND performs a logical product of the output signal of the timer section 31 and the output signal of the timer section 32, and outputs the result to the start output section 33.
The operation of the device constructed as described above will be explained next.

The CPU 1 outputs a set signal to the WDT 2 through the communication line 10 at certain fixed time intervals.

WDT2 receives an input or set signal (V) to reset the timer of WDT2. If the reset signal is not input from the CPU1 within the time T1 set in the timer of the WDT2, the WDT2 outputs a CPU abnormality signal to the timer section 31 through the communication device 11, and also outputs a CPU abnormal signal to the timer section 31 via the communication device 11, and also outputs the CPU abnormal signal to the timer unit 31 via the communication line 11. It outputs to other control devices (not shown) through. When the time TA at which the other control device recognizes the abnormality of the CPU has passed, the timer section 31 connects the communication line 13 to output an ON signal to the AND circuit AND. Since the timer section 32 is not operating, the timer section 32 is connected to 0F through the communication line 17.
The F signal is inverted and output to the AND circuit AND. Since the AND circuit AND circuit receives ON'''' and ``ON'', it outputs an 0N signal to the start output section 33. The output unit 33 outputs a restart signal to the CPU1 through the communication line 15, and
Restart Ul. Further, the restart signal is output to the timer unit 32 through the communication line 16 branched from the communication line 15 to start the timer. If the restarted CPU is normal,
If other control devices recognize that CPU is normal and the system operates normally, but CPUl is abnormal, WDT
2 works, WDT2 outputs a CPU error signal,
As described above, the ON signal is output to the AND circuit AND.
When this 0N signal is input to the AND circuit AND within the time TB set in the timer section 32, the 0N signal is inverted from the timer section 32 and output to the circuit AND. The circuit AND has "ON"" and "OFF" input, and is 0.
The FF signal is output to the start output section 33. Since the output section 33 receives the 0FF signal, it does not output a restart signal. This timing is shown in FIG. Figure 5! /(1) A indicates the abnormal signal of the WDT 2, C indicates the timer time of the timer section 31, C indicates the timer time of the timer section 32, and 2 indicates the output signal of the start output section 33, respectively.

Due to an abnormality in the CPU1, the WDT is disabled at time T, as shown in A.
When an abnormal signal is output from 2, the timer of the timer section 31 starts as shown in the figure, and turns 0N at time T2 when time TA has passed.
The signal is output to the AND circuit AND. At this time, as shown in c, the timer of the timer section 32 is activated at time T2.
Instead, an OFF signal is applied to the circuit AND. circuit AND
When the 0N signal is applied to the start output section 33, the start output section 33 outputs a pulse as shown in Figure 2, and the CPU returns to normal operation at the rising time T2 of the pulse, and starts the timer from the falling time T3. A timer in section 32 is started. Further, after an abnormal signal is output as shown in A at time T4, the timer of the timer section 31 is activated as shown in FIG.
outputs the 0N signal to the logic circuit AND. At this time, as shown in C, since the timer of the timer section 32 is working within the time TB, an 0N signal is output to the circuit AND, and as a result, an 0FF signal is applied to the start output section 33, and the output section 3
Since CPU 3 does not output an output signal, CPU1 is not restarted. As described above, according to the present invention, by providing the restart circuit 3 in a device using a conventional WDT, it is possible to distinguish between failures of the CPU itself and failures caused by external noise, eliminating system downtime caused by external noise. In addition, it has excellent advantages such as eliminating unnecessary effort required to restore the system and stabilizing the system.

[Brief explanation of drawings]

Fig. 1 is a block diagram using a conventional WDT, Figs. 2 and 3 are time charts and flow charts for explaining the WDT, and Fig. 4 is a block diagram showing an embodiment of the present invention. ,
FIG. 5 is a time chart showing the timing of FIG. 4. 1 is a CPU, 2 is a WDT, 3 is a restart processing circuit, 31,
32 is a timer section, and 33 is a restart output section.

Claims (1)

[Claims] 1. In an apparatus for detecting a failure of a central processing unit using a watch dog timer, a first timer unit set to a time TA is provided on the output side of the watch dog timer, and the watch dog and timer An abnormality signal of
Introducing the output signal of the second timer section set to B, outputting this AND condition fulfillment signal to the restart output section, and restarting the central processing unit with the output signal of the restart output section. A restart device for a central processing unit, characterized in that the restart device starts a second timer.