JPS592353A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS592353A JPS592353A JP57111021A JP11102182A JPS592353A JP S592353 A JPS592353 A JP S592353A JP 57111021 A JP57111021 A JP 57111021A JP 11102182 A JP11102182 A JP 11102182A JP S592353 A JPS592353 A JP S592353A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- tape
- adhesives
- protective film
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置の製造方法、詳しくはセラミックパ
ッケージに内蔵される半導体集積回路の保護膜を形成す
る方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a protective film for a semiconductor integrated circuit built into a ceramic package.
（２）技術の背景
セラミックパッケージにおいて、セラミックに含まれる
ウラン、トリウム等の放射性元素からα線が放射され、
このα線がセラミックパッケージの内蔵された半導体チ
ップ（以下チップと略称（１）
する）のメモリまたはビット線を通ると、通った跡に十
と−の電荷が発生し、それによって蓄えられた情報が逆
転するソフトエラーは知られている。(2) Background of the technology In ceramic packages, alpha rays are emitted from radioactive elements such as uranium and thorium contained in the ceramic.
When these alpha rays pass through the memory or bit line of a semiconductor chip (hereinafter referred to as chip (1)) with a built-in ceramic package, charges of + and - are generated in the path they pass through, and the stored information is thereby generated. Soft errors in which the values are reversed are known.
かかるソフトエラーを防止するには、チップ上になんら
かの物を配置し、その物によってα線をブロック（阻止
）するしかない。そのために現在とられている方法を説
明すると、第１図に示される如く、セラミックベース基
体１のキャビティ２内に付着されたチップ３上にポリイ
ミド（以下ＰＩと略記する）溶液を滴下しくドロッピン
グ）、それをチップ全面上に拡げた後硬化させて（キュ
アして）形成した保護膜４によってチップをα線から保
護する。なお同図において５はボンディングワイヤを示
す。The only way to prevent such soft errors is to place something on the chip to block alpha rays. To explain the method currently used for this purpose, as shown in FIG. 1, a polyimide (hereinafter abbreviated as PI) solution is dropped onto a chip 3 attached in a cavity 2 of a ceramic base substrate 1. The chip is protected from alpha rays by a protective film 4 formed by spreading it over the entire surface of the chip and then curing it. In addition, in the figure, 5 indicates a bonding wire.
上記の如くにして形成されたＰＩの保護膜４は、上に凸
に（山なり）に形成され、チップの端の部分（チップの
周縁の近くの部分）で保護膜は薄くなる。その結果、チ
ップの端の部分でメモリ等がα線に対し十分に保護され
ない。The PI protective film 4 formed as described above is formed in an upwardly convex (mountain-like) manner, and the protective film becomes thinner at the end portions of the chip (portions near the periphery of the chip). As a result, memories and the like are not sufficiently protected from alpha rays at the edges of the chip.
かくして、チップの端部分においても十分な（２）
厚さの保護膜を設けるために、ＰＩテープを用いる技術
が開発され、併せてＰＩテープをいかなる接着剤を用い
てチップ上にはり付けるかが研究された。Thus, in order to provide a sufficient (2) thick protective film even at the edges of the chip, a technique using PI tape has been developed, and it is also difficult to determine what kind of adhesive should be used to attach the PI tape onto the chip. researched.
第１図に示すセラミックパッケージを完成するには、４
８０℃程度の温度でガラス封止（ガラス接着剤を用いる
キャップのろう付け）をなす。この４８０℃程度の温度
に耐えうる有機ポリマーはＰＩしかないので、ＰＩテー
プの接着にＰＩ接着剤を用いることがなされる。To complete the ceramic package shown in Figure 1, 4
Glass sealing (brazing of the cap using glass adhesive) is performed at a temperature of about 80°C. Since PI is the only organic polymer that can withstand temperatures of about 480° C., PI adhesives are used to bond PI tapes.
かくして、現在とられている耐α線保護膜の形成方法に
おいては、ＰＩ接着剤を少量チップ上にドロッピングし
、それをチップ上に拡げ、次いでＰＩテープを接着剤の
上におき、加熱してＰＩ接着剤をキュアし、ＰＩテープ
をはり付ける。Thus, in the currently used method of forming an α-ray-resistant protective film, a small amount of PI adhesive is dropped onto the chip, it is spread over the chip, and then PI tape is placed on the adhesive and heated. Cure the PI adhesive and attach the PI tape.
（３）従来技術と問題点
上記の加熱キュアにおいて、ＰＩ接着剤とチップの接着
力が強すぎるため、ＰＩ接着剤の硬化収縮時に接着剤と
チップの接着が不安定になることが製品の最終検査で見
出された例がある。しかし、現在セラミックパッケージ
の製造には４８０℃前後（３）
でのガラス封止は不可欠であるので、ＰＩに代る接着剤
が見出されるまではそれを用いざるをえない状況にある
。(3) Prior art and problems In the heat curing described above, the adhesive force between the PI adhesive and the chip is too strong, so when the PI adhesive hardens and shrinks, the adhesion between the adhesive and the chip becomes unstable. There are examples that have been found through testing. However, since glass sealing at around 480°C (3) is currently indispensable for the production of ceramic packages, we have no choice but to use PI until an adhesive is found to replace it.
（４）発明の目的
本発明は上記従来の問題点に泥メ、ｐｉテープとＰ■接
着剤とを用いチップのための耐α線保護膜を形成する方
法において、チップと接着剤との間に安定した接着力を
発生させうる保護膜の形成方法を提供することを目的と
する。(4) Purpose of the Invention The present invention solves the above-mentioned conventional problems and provides a method for forming an α-ray-resistant protective film for a chip using a PI tape and a P adhesive. An object of the present invention is to provide a method for forming a protective film that can generate stable adhesive force.
（５）発明の構成
そしてこの目的は本発明によれば、ＰＩテープ上にＰＩ
接着剤を塗布した後にチップ上にはり付け、加熱加圧に
よりＰＩテープをチップ上に接着する方法を提供するこ
とによって達成される。また、上記工程において、チッ
プ上に予めなんらかの材料で保護膜を形成しておいても
よい。(5) Structure and object of the invention According to the present invention, a PI tape is recorded on a PI tape.
This is achieved by providing a method for bonding the PI tape onto the chip by applying an adhesive and then applying heat and pressure to the chip. Further, in the above step, a protective film may be formed on the chip in advance using some material.
（６）発明の実施例 以下本発明の実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図に本発明の方法を実ｈ＆する工程におけるセラミ
ックパッケージの要部が断面で示され、（４）
同図および次の第３図において既に図示した部分と同じ
部分は同一符号を付して表示する。FIG. 2 shows a cross section of the main parts of a ceramic package in the process of carrying out the method of the present invention. (4) In this figure and the following FIG. to be displayed.
セラミックベース基体ｌのキャビティ２にはチップ３が
付着され、ホンディングワイヤ５が接着されるまでは、
従来技術における工程と同様である。他方、ＰＩテープ
を用意し、その上に液状のＰＩ接着剤を塗布し、取り扱
い中に接着剤が作業者の指等によってぬぐわれることの
ないよう暫時放置して接着剤に含まれる溶剤を部分的に
発散させる。この状態で、接着剤は若干べたつくが、テ
ープから剥がれることばない。The chip 3 is attached to the cavity 2 of the ceramic base substrate l, and until the bonding wire 5 is bonded,
This is similar to the process in the prior art. On the other hand, prepare a PI tape, apply liquid PI adhesive on it, and leave it for a while to prevent the adhesive from being wiped off by the operator's fingers during handling to partially remove the solvent contained in the adhesive. to emanate from. In this state, the adhesive will be a little sticky, but will not peel off from the tape.
次にＰＩテープをチップにはり付ける。第２図にはチッ
プ３上にはり付けられたテープ７をＰＩ接着剤６ （締
張的に図示される）と共に示す。Next, attach PI tape to the chip. FIG. 2 shows the tape 7 applied onto the chip 3 together with the PI adhesive 6 (illustrated in tension).
次いで、４８０℃程度の温度でキュアし、１００ｇ／ｃ
ｍ２程度の力でＰＩテープ７をチップ３に向けて圧着し
て保護膜を形成する。この圧着によって、チップのデバ
イスを損傷することなく、ＰＩテープはチップ３上に均
一にはり付けられる。かかる保護膜を検査したところ、
チップ３とＰＩテープとの（５）
間に安定した接着力が得られたことが確認された。Next, it is cured at a temperature of about 480℃, and 100g/c
The PI tape 7 is pressed against the chip 3 with a force of about m2 to form a protective film. This crimping allows the PI tape to be applied uniformly onto the chip 3 without damaging the chip's devices. When such a protective film was inspected, it was found that
It was confirmed that stable adhesive force was obtained between the chip 3 and the PI tape (5).
なお上記したＰＩテープ、ＰＩ接着剤は市販の製品を用
いる。Note that commercially available products are used as the above-mentioned PI tape and PI adhesive.
本発明の他の実施例においては、上記したＰＩテープの
はり付けの前に、チップ３上に、ＰＩ、りん・シリケー
トガラス（ＰＳＧ ） 、二酸化シリコン等のウェハコ
ーティング８を通常の技術で形成しておく。かくするこ
とによって、チップ上に既に形成されたＰＳＧ ＭＷ等
が前記したＰＩの硬化収縮から保護されることが確認さ
れた。In another embodiment of the invention, a wafer coating 8 of PI, phosphorous silicate glass (PSG), silicon dioxide, etc. is formed on the chip 3 by conventional techniques before the above-described PI tape is attached. I'll keep it. It was confirmed that by doing so, the PSG MW etc. already formed on the chip were protected from the curing shrinkage of the PI described above.
なお以上説明した実施例において、ＰＩ接着剤の塗布の
ときの膜厚を５〜２０μｍＸＰＩテープの厚さを５０〜
１２５μｍ１ウエハコーテイングの膜厚を５〜１５μｍ
に設定して良好な結果を得た。In the examples described above, the film thickness when applying the PI adhesive was 5 to 20 μm, and the thickness of the XPI tape was 50 to 20 μm.
125 μm 1 wafer coating film thickness 5 to 15 μm
I got good results using the settings.
（７）発明の効果
以上、詳細に説明したように、本発明の方法によるとき
は、チップをα線から守る保護膜が、安定した接着力で
もってチップに形成され、セラミックパッケージの信頼
性向上に効果大である。(7) Effects of the Invention As explained in detail above, when using the method of the present invention, a protective film that protects the chip from alpha rays is formed on the chip with stable adhesive strength, improving the reliability of the ceramic package. It is highly effective.
（６）
第１図は従来技術によりｐｒ接着剤をキュアしたときの
セラミックパッケージの要部の断面図、第２図と第３図
とは本発明の方法を実施する工程におけるセラミックパ
ッケージの要部の断面図である。
１−セラミソクヘース基体、２−キャビティ、３−半導
体チップ、４．６−ＰＩ接着剤、７−ＰＩテープ、８−
ウェハコーティング特 許 出願人 冨士通株式会
社
（７）
第１図
第２図
第３図(6) Figure 1 is a sectional view of the main parts of the ceramic package when the PR adhesive is cured using the conventional technique, and Figures 2 and 3 are the main parts of the ceramic package in the process of implementing the method of the present invention. FIG. 1-Ceramic base, 2-cavity, 3-semiconductor chip, 4.6-PI adhesive, 7-PI tape, 8-
Wafer coating patent Applicant: Fujitsu Co., Ltd. (7) Figure 1 Figure 2 Figure 3
Claims (1)
する方法において、ポリイミド接着剤を塗布したポリイ
ミドテープを前記半導体チップ上に置き、加熱圧着によ
って前記ポリイミドテープを半導体チップにはり付ける
ことを特徴とする半導体装置の製造方法。A method for forming a protective film on a semiconductor chip incorporated in a package, characterized in that a polyimide tape coated with a polyimide adhesive is placed on the semiconductor chip, and the polyimide tape is attached to the semiconductor chip by heat pressure bonding. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57111021A JPS592353A (en) | 1982-06-28 | 1982-06-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57111021A JPS592353A (en) | 1982-06-28 | 1982-06-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS592353A true JPS592353A (en) | 1984-01-07 |
| JPH0340949B2 JPH0340949B2 (en) | 1991-06-20 |
Family
ID=14550376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57111021A Granted JPS592353A (en) | 1982-06-28 | 1982-06-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS592353A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59121956A (en) * | 1982-12-28 | 1984-07-14 | Tomoegawa Paper Co Ltd | Heat-resisting adhesive sheet |
-
1982
- 1982-06-28 JP JP57111021A patent/JPS592353A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59121956A (en) * | 1982-12-28 | 1984-07-14 | Tomoegawa Paper Co Ltd | Heat-resisting adhesive sheet |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0340949B2 (en) | 1991-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104064483B (en) | Semiconductor device and its manufacture method | |
| JPS5987840A (en) | Semiconductor device | |
| JPS6122865B2 (en) | ||
| JPS592353A (en) | Manufacture of semiconductor device | |
| JP3531580B2 (en) | Bonding method | |
| JPS5828860A (en) | Semiconductor device and manufacture thereof | |
| JPH09246325A (en) | Semiconductor element mounting structure and manufacture thereof | |
| JPH0475355A (en) | Joining method of semiconductor element to lead frame | |
| JPS59204259A (en) | Method for sealing semiconductor device | |
| JPH02209739A (en) | Manufacture of semiconductor device | |
| CN207977306U (en) | Semiconductor packages | |
| JPS5848950A (en) | Semiconductor device and its manufacture | |
| JPH1050775A (en) | Double coated adhesive insulating tape for semiconductor device and lead frame employing it | |
| JPS6214100B2 (en) | ||
| JPS61111569A (en) | Resin-sealed semiconductor device | |
| JPH05315397A (en) | Sealing method and sealing structure of semiconductor device | |
| JPS593779A (en) | Packaging method of magnetic bubble chip | |
| JPH04219955A (en) | Taping and packaging method of electronic chip component | |
| JP2529459B2 (en) | Semiconductor device and bonding method therefor | |
| JPH0366152A (en) | Semiconductor integrated circuit module | |
| JPS60245260A (en) | Semiconductor element | |
| JPH02210843A (en) | Resin-sealed semiconductor device | |
| JPH01206651A (en) | Semiconductor device | |
| JPS58132955A (en) | Semiconductor device and manufacture thereof | |
| JPS6177347A (en) | Manufacture of semiconductor device |