JPS59204259A - Method for sealing semiconductor device - Google Patents

Method for sealing semiconductor device

Info

Publication number
JPS59204259A
JPS59204259A JP58078185A JP7818583A JPS59204259A JP S59204259 A JPS59204259 A JP S59204259A JP 58078185 A JP58078185 A JP 58078185A JP 7818583 A JP7818583 A JP 7818583A JP S59204259 A JPS59204259 A JP S59204259A
Authority
JP
Japan
Prior art keywords
composition
semiconductor element
semiconductor device
memory
silicone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58078185A
Other languages
Japanese (ja)
Inventor
Takashi Yokoyama
隆 横山
Akio Nishikawa
西川 昭夫
Tokuyuki Kaneshiro
徳幸 金城
Kunihiro Tsubosaki
邦宏 坪崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58078185A priority Critical patent/JPS59204259A/en
Publication of JPS59204259A publication Critical patent/JPS59204259A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/296Organo-silicon compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

PURPOSE:To eliminate the cause for the generation of disconnection by a method wherein a protection coat using a gelled thixotropic Si composition is provided only at the memory part except for the parts of the electrode and connection of the surface of a semiconductor element. CONSTITUTION:Said Si composition is used as a coating material 1, Which is applied only to the memory part 2, except for the electrode 3 and the connection 4. In this case, said Si composition means a composition generating an elastic gel by polymerization. Thereby, the generation of disconnection is eliminated.

Description

【発明の詳細な説明】 本発明は半導体装置の封止方法に係り、とくに半導体素
子を自然界からのα線から遮蔽する被覆の通用形式に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for encapsulating a semiconductor device, and more particularly to a common type of coating that shields a semiconductor element from alpha rays from nature.

自然界で生じたα機が半導体素子のメモリ一部に入射す
ることによって、素子が誤動作を起すことはよく知られ
ている。それゆえ、このα線の影響から半導体素子を保
穫するために、シリコーンやポリイミドなどの樹脂材料
からなる被覆が半導体素子に施され、そのうえで、該半
導体素子は硬化性樹脂組成物によって封止されていた。
It is well known that when α planes generated in nature enter a part of the memory of a semiconductor device, the device malfunctions. Therefore, in order to protect the semiconductor element from the influence of this alpha ray, a coating made of a resin material such as silicone or polyimide is applied to the semiconductor element, and then the semiconductor element is sealed with a curable resin composition. was.

そして第1図(断面)に示されるように、被覆1が、半
導体素子5のメモリ一部2ばかりでなく、酸極部3、該
電極とリードフレーム6との間の結線4の上にまで施さ
れることは、作業上の都合もあって、常態と首ってよか
った。
As shown in FIG. 1 (cross section), the coating 1 covers not only the memory part 2 of the semiconductor element 5 but also the acid electrode part 3 and the connection 4 between the electrode and the lead frame 6. It was a good thing that it was done normally due to work reasons.

そのような保1.φ被覆の適用に当って、核種材料の中
でも特に低い弾性率を有するシリコーン弾性ゲルが、被
覆されている部分に強い応力を及はしたり、湿気に触れ
ても電極の腐食や電流リークを生じることが少ないこと
から有利と考えられ、かなりの頻度で用いられている。
Such protection 1. When applying φ coating, silicone elastic gel, which has a particularly low elastic modulus among nuclide materials, exerts strong stress on the covered part, and even if it comes into contact with moisture, it may cause corrosion of the electrode or current leak. It is considered to be advantageous because it rarely occurs, and is used quite often.

しかし、該シリコーンゲル被覆素子も、外囲温度の急変
に遭@した場合等に、結線の欠陥部で断線するし0が時
として観察された。
However, even when the silicone gel-coated element experiences a sudden change in ambient temperature, wire breakage occurs at a defective part of the wire connection.

本発明の目的は、このような断勝の発生IJIL因を絶
つことである。断線は、結線利とシリコーンゲル両者の
熱膨張係数が異なるために、第1図において結線の点線
で囲まれた部分aに作用する応力によってひき起される
と推薦される。そこで、不発明は被覆の適用域を限定し
、かつ、それを可能にする作業性を付与された被覆用材
料を用いること、tた、その方法を適用された半導体素
子を包含する。すなわち、その特徴は、半導体素子の表
面に保りら被4υを形成したのち樹脂組成物を用いて封
止する半導体装置の封止方法において、被〜材としてゲ
ル化性シクソトロピー性シリコーン組成・物を用い、か
つ、該保祷被援を半導体素子の表面の電極および結線部
分ケ除きメモリ一部分のみに形J戎することでめる。
The purpose of the present invention is to eliminate the cause of such IJIL failure. It is recommended that the wire breakage is caused by stress acting on the portion a of the wire connection surrounded by the dotted line in FIG. 1 because the wire connection strength and the coefficient of thermal expansion of the silicone gel are different. Therefore, the invention includes the use of a coating material that limits the application area of the coating and is provided with workability that makes this possible, as well as semiconductor devices to which this method is applied. That is, the feature is that in a semiconductor device encapsulation method in which a 4υ is formed on the surface of a semiconductor element and then sealed using a resin composition, a gelatinable thixotropic silicone composition is used as the material to be encapsulated. This can be achieved by applying the protection to only a portion of the memory, excluding the electrodes and connection portions on the surface of the semiconductor element.

本発明においては、第2図に示きれるように、破株1は
メモリ一部分2のみに施され、′電極3や結線4は除外
される。従って、断線の原因となる第1図のaのような
部分はできない。被樫の厚さとしては少なくとも杓40
〜50μmは望ましい。
In the present invention, as shown in FIG. 2, the stub 1 is applied only to a portion 2 of the memory, and the electrodes 3 and connections 4 are excluded. Therefore, a portion such as a in FIG. 1, which may cause wire breakage, cannot be formed. The thickness of the oak is at least 40 mm.
~50 μm is desirable.

通常入手し得るゲル化性シリコーン組成物では、メモリ
一部のみにこの厚さに塗布すると、素子表面にそって流
延して1極や結線部に付着することは赴けがたいが、シ
クントロピーを有する組成物音用いることによって、そ
れらへの付着を回避しメモリ一部分のみに限局された被
覆ができる。
With commonly available gelatinous silicone compositions, if applied to only a portion of the memory to this thickness, it is difficult to cast along the element surface and adhere to one pole or connection part. By using a composition having a silica bond, it is possible to avoid adhesion to them and to cover only a portion of the memory.

ここにいうゲル化性シリコーン組成物とは、重合するこ
とによって弾性ゲルを生じる組成物を意味し、通常重合
開始剤または触媒の作用によって、シリコーンプレポリ
マー分子の末媒および側鎖の官能基と架橋剤(多官能性
モノマー)との付加反応によシゲル化する型が多い。前
述のように該ボ且成物はシクソトロピー性を有すること
を要し、該性質は、粒径1μIn以下、特に数十μIn
の7リカ微粉末などを0.001〜1重量%配合するな
ど公知の方法によって付与される。
The term "gelling silicone composition" as used herein means a composition that produces an elastic gel by polymerization, and is usually formed by the action of a polymerization initiator or catalyst to form a terminal solvent and side chain functional groups of a silicone prepolymer molecule. There are many types that form a sigelloid through an addition reaction with a crosslinking agent (polyfunctional monomer). As mentioned above, the composite is required to have thixotropic properties, and this property requires a particle size of 1 μIn or less, especially several tens of μIn.
It is applied by a known method such as blending 0.001 to 1% by weight of 7 Lika fine powder.

次に、本発明の実施例を述べる。Next, examples of the present invention will be described.

市販のゲル化性2液型シリコーンの南側成分(25Cで
の粘度50〜70ポイズ)にシクントロピー性付与剤の
シリカ微粉末(平均粒径約5011 nl )を、樹脂
成分重量に対し0.IM電%混和した。この混和物に、
架橋剤・触媒成分(25Cでの粘度20〜25ボイズ)
を混合したのち、64xbitメモリー素子のメモリ一
部分の氷面に滴下して、厚さ約50μmの丘状に塗布し
た。その後、100tJC1時18J1次いT150C
1時間処理することによって、該塗膜全ゲル化はせた。
Fine silica powder (average particle size: about 5011 nl), which is a sicuntropic agent, is added to the south component of a commercially available gelling two-component silicone (viscosity at 25C of 50 to 70 poise) in an amount of 0.000 m2 based on the weight of the resin component. IM electrolyte was mixed. In this mixture,
Crosslinking agent/catalyst component (viscosity 20-25 voids at 25C)
After mixing, the mixture was dropped onto the ice surface of a portion of the memory of a 64xbit memory device, and applied in the form of a hill with a thickness of about 50 μm. After that, 100tJC1:18J1 then T150C
The coating was completely gelled by treatment for 1 hour.

電極や結線の部分には、該ゲルの付着は認めらrtなが
った。次に、この被覆された素子を、トランスファ成形
法によりエポキシ樹脂組成物を用いて封止した。封止素
子100個に、−1961r 〜+150C温度サイク
ルを2000回課したが、断線を生じなかった。一方、
ノリカ微粉末を加えないシリコーン組成物を用いて、M
1図のような状態で約5 Q 71 III厚さに被覆
し前記と同様に樹脂封止した素子は、同試験において1
00個中8o個の断線を生じた。
No adhesion of the gel was observed on the electrodes or wire connections. Next, this coated element was sealed using an epoxy resin composition by a transfer molding method. Although 100 sealing elements were subjected to temperature cycles of -1961r to +150C 2000 times, no wire breakage occurred. on the other hand,
Using a silicone composition without adding Norica fine powder, M
In the same test, the element coated to a thickness of approximately 5 Q 71 III and sealed with resin in the same manner as above in the state shown in Figure 1 was 1
8 out of 00 wire breaks occurred.

【図面の簡単な説明】[Brief explanation of drawings]

;A1図、第2図は半導体素子の保鐵被チ部分を示す断
面図である。 l・・・被覆ゲル、2・・・メモリー、3・・・′44
M、4・・・結線、5・・・半導体素子、6・・・リー
ドフレーム、7・・・基板。 代理人 弁理士 高橋明夫を 第1図 惰2図 口
Figure A1 and Figure 2 are cross-sectional views showing the portion of the semiconductor element covered by the safety iron. l...Coating gel, 2...Memory, 3...'44
M, 4... Wire connection, 5... Semiconductor element, 6... Lead frame, 7... Substrate. Agent: Patent Attorney Akio Takahashi (Figure 1, Figure 2)

Claims (1)

【特許請求の範囲】[Claims] 1、半導体素子の表面に保護核種を形成したのち樹脂組
成物を用いて封止する半導体装置の封止方法において、
被僅材としてゲル化性シクロトロピー性シリコーン組成
物を用い、がっ、該保瞳被覆を半導体素子の表面の電極
および結線部分を除きメモリ一部分に形成したことを特
徴とする半導体装置の封止方法。
1. In a semiconductor device sealing method in which a protective nuclide is formed on the surface of a semiconductor element and then sealed using a resin composition,
Sealing of a semiconductor device, characterized in that a gelatinable cyclotropic silicone composition is used as a material to be coated, and the eye-keeping coating is formed on a part of the memory except for the electrodes and connection parts on the surface of the semiconductor element. Method.
JP58078185A 1983-05-06 1983-05-06 Method for sealing semiconductor device Pending JPS59204259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58078185A JPS59204259A (en) 1983-05-06 1983-05-06 Method for sealing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58078185A JPS59204259A (en) 1983-05-06 1983-05-06 Method for sealing semiconductor device

Publications (1)

Publication Number Publication Date
JPS59204259A true JPS59204259A (en) 1984-11-19

Family

ID=13654910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58078185A Pending JPS59204259A (en) 1983-05-06 1983-05-06 Method for sealing semiconductor device

Country Status (1)

Country Link
JP (1) JPS59204259A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001918A (en) * 1997-07-10 1999-12-14 Dow Corning Toray Silicone Co., Ltd. Silicone gel composition for use as a sealant and a filler for electrical and electronic components and a gel prepared from this composition
WO2015111409A1 (en) 2014-01-27 2015-07-30 Dow Corning Toray Co., Ltd. Silicone gel composition
WO2018056298A1 (en) 2016-09-26 2018-03-29 東レ・ダウコーニング株式会社 Laminate, manufacturing method thereof, and manufacturing method of electronic component
WO2018056297A1 (en) 2016-09-26 2018-03-29 東レ・ダウコーニング株式会社 Curing reactive silicone gel and use thereof
WO2018079678A1 (en) 2016-10-31 2018-05-03 東レ・ダウコーニング株式会社 Layered body and method for manufacturing electronic component
WO2019049950A1 (en) 2017-09-11 2019-03-14 東レ・ダウコーニング株式会社 Cured silicone elastomer having radical reactivity and use of same
US11396616B2 (en) 2017-04-06 2022-07-26 Dow Toray Co., Ltd. Liquid curable silicone adhesive composition, cured product thereof, and use thereof

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001918A (en) * 1997-07-10 1999-12-14 Dow Corning Toray Silicone Co., Ltd. Silicone gel composition for use as a sealant and a filler for electrical and electronic components and a gel prepared from this composition
WO2015111409A1 (en) 2014-01-27 2015-07-30 Dow Corning Toray Co., Ltd. Silicone gel composition
US10155852B2 (en) 2014-01-27 2018-12-18 Dow Corning Toray Co., Ltd. Silicone gel composition
KR20190051022A (en) 2016-09-26 2019-05-14 다우 코닝 도레이 캄파니 리미티드 Curing reactive silicone gel and uses thereof
WO2018056298A1 (en) 2016-09-26 2018-03-29 東レ・ダウコーニング株式会社 Laminate, manufacturing method thereof, and manufacturing method of electronic component
WO2018056297A1 (en) 2016-09-26 2018-03-29 東レ・ダウコーニング株式会社 Curing reactive silicone gel and use thereof
US11279827B2 (en) 2016-09-26 2022-03-22 Dow Toray Co., Ltd. Curing reactive silicone gel and use thereof
KR20190046997A (en) 2016-09-26 2019-05-07 다우 코닝 도레이 캄파니 리미티드 LAMINATE, METHOD OF MANUFACTURING THE SAME,
KR20190080912A (en) 2016-10-31 2019-07-08 다우 도레이 캄파니 리미티드 Laminate and electronic component manufacturing method
US10961419B2 (en) 2016-10-31 2021-03-30 Dow Toray Co., Ltd. Layered body and method for manufacturing electronic component
WO2018079678A1 (en) 2016-10-31 2018-05-03 東レ・ダウコーニング株式会社 Layered body and method for manufacturing electronic component
US11396616B2 (en) 2017-04-06 2022-07-26 Dow Toray Co., Ltd. Liquid curable silicone adhesive composition, cured product thereof, and use thereof
WO2019049950A1 (en) 2017-09-11 2019-03-14 東レ・ダウコーニング株式会社 Cured silicone elastomer having radical reactivity and use of same
KR20200051665A (en) 2017-09-11 2020-05-13 다우 도레이 캄파니 리미티드 Cured silicone elastomer having radical reactivity and uses thereof

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