JPS593779A - Packaging method of magnetic bubble chip - Google Patents
Packaging method of magnetic bubble chipInfo
- Publication number
- JPS593779A JPS593779A JP57112386A JP11238682A JPS593779A JP S593779 A JPS593779 A JP S593779A JP 57112386 A JP57112386 A JP 57112386A JP 11238682 A JP11238682 A JP 11238682A JP S593779 A JPS593779 A JP S593779A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- magnetic bubble
- magnetic
- bubble chip
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は磁気バブルチップ実装方法の改良に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to improvements in magnetic bubble chip mounting methods.
従来技術の問題点
従来の磁気バブルチップの実装要領を第１図に示す。図
中、１は磁気バブルチップ搭載用の１Ｊｉ２を有する基
板、３は約１０１０Ｘ１０程度のサイズの磁気ハブルチ
ソプである。磁気バブルチップの実装に際しては、あら
かじめ基板１の溝２の底面に熱硬化性接着剤４を塗布し
ておいて溝２内に磁気バブルチップ３を搭載して接着剤
４により基板１に固定し接着剤４を熱硬化させた後、該
磁気バブルチップ３と基板１の基板端子５とをワイヤボ
ンディングにより接続して実装を行なっている。Problems with the Prior Art FIG. 1 shows a mounting procedure for a conventional magnetic bubble chip. In the figure, 1 is a substrate having 1Ji2 for mounting a magnetic bubble chip, and 3 is a magnetic bubble chip having a size of about 1010×10. When mounting the magnetic bubble chip, a thermosetting adhesive 4 is applied to the bottom of the groove 2 of the substrate 1 in advance, and the magnetic bubble chip 3 is mounted in the groove 2 and fixed to the substrate 1 with the adhesive 4. After the adhesive 4 is thermally cured, the magnetic bubble chip 3 and the board terminals 5 of the board 1 are connected by wire bonding to perform mounting.
この場合、チップ固定時にチップ傾きを一定にしないと
ホールド磁界が不安定になる。第２図はこのことを説明
するもので、第２図（ａｌは磁気バブルチップ３が傾い
て固定された状態を示し、第２図（ｂｌは磁気バブルチ
ップ３が正しく固定された状態（チソフＤのみを示す）
を示している。バイアス磁界Ａに対する実際のバイアス
磁界は、第２図（ｂｌの場合がＢであるのに対し第２図
ｆａｌの場合はＢ′になる。ｃ、ｃ’はホールド磁界で
ある。この両者のチップ特性を第２図（Ｃ１に示す。実
線の曲線は第２図ｆｂｌの場合の特性を示し、点線の曲
線は第２図（ａｌの場合を示している。In this case, the holding magnetic field will become unstable unless the chip inclination is kept constant when the chip is fixed. Figure 2 explains this. Figure 2 (al shows the state in which the magnetic bubble chip 3 is tilted and fixed, and Figure 2 (bl shows the state in which the magnetic bubble chip 3 is fixed correctly (Tisof). (only D is shown)
It shows. The actual bias magnetic field for the bias magnetic field A is shown in Fig. 2 (B in the case of bl and B' in the case of fal in Fig. 2. c and c' are the hold magnetic fields. The characteristics are shown in FIG. 2 (C1). The solid line curve shows the characteristics in the case of FIG. 2 fbl, and the dotted line curve shows the characteristics in the case of FIG. 2 (al).
この問題を解決するためには、第３図に示すように、磁
気バブルチップ３を基板ｌの溝２内に接着剤４を介し搭
載した後、磁気ハブルチソプ３を操作する真空ビンセッ
ト６に矢印方向に押圧力を与えて該磁気バブルチップ３
を十分圧着し傾きなく仮固定する必要がある。In order to solve this problem, as shown in FIG. Applying a pressing force in the direction of the magnetic bubble chip 3
It is necessary to crimp it sufficiently and temporarily fix it without tilting it.
ところが、このようにすると、接着剤４が第４図に示す
ように磁気パブルチンプ３と溝２の側壁との間の間隙７
からはみ出して磁気バブルチップ３のボンディング用端
子８に付着するため、接着剤熱硬化後のワイヤボンディ
ングが困難になる。However, in this case, the adhesive 4 fills the gap 7 between the magnetic bubble chimp 3 and the side wall of the groove 2, as shown in FIG.
Since the adhesive sticks out from the adhesive and adheres to the bonding terminal 8 of the magnetic bubble chip 3, wire bonding after the adhesive is thermally cured becomes difficult.
また、このように接着剤４がはみ出す問題をなくすため
に、第５図に示すように搭載する磁気バブルチップ３の
裏面の一部に対応する部分に接着剤４を少な目に塗布す
ると、接着剤硬化時に接着剤周辺部付近に圧縮歪あるい
は引張歪が生じ、磁気バブルチップ３の磁気特性が第６
図に示すように容易に劣化する。第６図に実線で示す曲
線は接着剤硬化前の特性を示し、第６図に点線で示す曲
線は接着剤硬化ｆ＆（１２０°ｃ、３０分）の磁気特性
を示している。In addition, in order to eliminate the problem of the adhesive 4 spilling out, as shown in FIG. Compressive strain or tensile strain occurs near the periphery of the adhesive during curing, and the magnetic properties of the magnetic bubble chip 3 change to
As shown in the figure, it deteriorates easily. The solid line curve in FIG. 6 shows the characteristics before the adhesive is cured, and the dotted line curve in FIG. 6 shows the magnetic characteristics after the adhesive is cured f& (120° C., 30 minutes).
発明の目的
本発明は上述の各種の問題を解決するためのもので、基
板に対する磁気ハブルチソプの実装をその特性を劣化さ
せずに容易に実装することのできる磁気バブルチップの
実装方法を提供することを目的としている。OBJECTS OF THE INVENTION The present invention is intended to solve the various problems mentioned above, and provides a method for mounting a magnetic bubble chip that can easily mount a magnetic bubble chip onto a substrate without deteriorating its characteristics. It is an object.
発明の実施例
以下、第７図乃至第９図に関連して本発明の詳細な説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to FIGS. 7 to 9.
本発明は、磁気ハブルチ・７プを軽く固定しておくだけ
でワイヤボンディングが可能なことを利用して実装を行
なうようにしたもので、その詳細は次の通りである。The present invention utilizes the fact that wire bonding is possible by simply fixing the magnetic hub chip 7 lightly, and the details thereof are as follows.
まず、第７図ｆａｌに示すように、真空ビンセット６に
保持される磁気バブルチップ３を基板１の溝２にじかに
搭載し、ワイヤボンディングに影響を与えない側（ワイ
ヤボンディングを行なわない側）の間隙７に第７図ｆｂ
）に示すように少量の速乾性の接着剤１１を塗布して磁
気バブルチップ３を仮固定する。この接着剤１１として
は、例えば写真用セメダインを用いることができるが、
チップのバブル素子を腐蝕させるＣＩ！等の元素子が含
まれないの
Ｃ宅あればその他のものを用いても良い。この場合、接
着剤１１は速乾性であるため、短時間で仮固定を行なう
ことができ、かつこの際に得られる接着力は、ワイヤボ
ンディングに支障のない程度でありしかもチップに圧縮
または引っ張りの歪を与えない程度である。従って、接
着剤１１が多少チップ表面にかぶってもチップの磁気特
性が変化することはない。この作業完了時における平面
図を第８図に示す。図示のように、接着剤１１は間隙７
の一部に付着させる程度で充分である。First, as shown in FIG. 7fal, the magnetic bubble chip 3 held in the vacuum bottle set 6 is directly mounted on the groove 2 of the substrate 1 on the side that does not affect wire bonding (the side on which wire bonding is not performed). Figure 7fb in gap 7
), the magnetic bubble chip 3 is temporarily fixed by applying a small amount of quick-drying adhesive 11. As this adhesive 11, for example, Cemedine for photography can be used.
CI corrodes the bubble element of the chip! If it does not contain elements such as C, other elements may be used. In this case, since the adhesive 11 dries quickly, temporary fixing can be carried out in a short time, and the adhesive force obtained at this time is of a level that does not interfere with wire bonding, and does not cause compression or tension on the chip. This is to the extent that it does not cause distortion. Therefore, even if some adhesive 11 covers the surface of the chip, the magnetic properties of the chip will not change. FIG. 8 shows a plan view when this work is completed. As shown, the adhesive 11 is in the gap 7
It is sufficient to attach it to a part of the body.
次に第７図（Ｃ１に示すようにワイヤ１２により端子間
のボンディング接続を行なう。なお第７図ｆｃ）は端子
側の断面図である。Next, as shown in FIG. 7 (C1), a bonding connection between the terminals is made using the wire 12. FIG. 7 fc is a sectional view of the terminal side.
最後に第７図（ｄ）に示すように、端子接続および磁気
バブルチップ３を覆って高純度のシリコーン樹脂１３を
塗布し熱硬化させて実装が完了する。第９図は実装完了
状態における端子のない側の断面図を示している。熱硬
化の温度２時間は、１５０’Ｃ。Finally, as shown in FIG. 7(d), high-purity silicone resin 13 is applied to cover the terminal connections and magnetic bubble chip 3 and is thermally cured to complete the mounting. FIG. 9 shows a cross-sectional view of the side without terminals in a state where the mounting is completed. The heat curing temperature for 2 hours was 150'C.
２〜３時間である。このシリコーン樹脂硬化完了時点で
は、磁気バブルチップ３は接着剤１１の他にシリコーン
樹脂により確実に固定される。It takes 2 to 3 hours. At the time when the silicone resin is completely cured, the magnetic bubble chip 3 is securely fixed by the silicone resin in addition to the adhesive 11.
発明の効果
以上述べたように、本発明によれば、′次のような各種
の優れた効果を奏することが可能である。Effects of the Invention As described above, according to the present invention, it is possible to achieve various excellent effects as described below.
（１）チップを基板に正しい姿勢で（傾斜がない）搭載
して仮固定することができ、しかも仮固定する接着剤硬
化時にチップに歪を生じないため、チップの磁気特性低
化を防止することができる。(1) The chip can be mounted and temporarily fixed on the board in the correct orientation (no inclination), and the chip does not become distorted when the temporary fixing adhesive hardens, thus preventing deterioration of the magnetic properties of the chip. be able to.
（２）仮固定用接着剤をチップのボンディングを行なわ
ない側に塗布することにより、端子間のボンディング接
続を支障なく行なうことができる。(2) By applying a temporary fixing adhesive to the side of the chip where bonding is not performed, bonding connections between terminals can be made without any problem.
（３）仮固定用接着剤として速乾性のものを使用するた
め、仮固定を短時間で行なうことが可能である。(3) Since a quick-drying adhesive is used as the temporary fixing adhesive, temporary fixing can be done in a short time.
（４）シリコーン樹脂を用いて表面保護およびチップ固
定を同時に行なうことができるため、パンケージング工
程の簡略化およびパンケージレベルでの歩留り向上が期
待できる。(4) Since surface protection and chip fixation can be performed simultaneously using silicone resin, it is expected that the pancaging process will be simplified and the yield at the pancage level will be improved.
第１図は従来の磁気バブルチップ実装要領を示す斜視図
、第２図ｔａＬ ｆｂ）、 ｆｃ）は従来の実装方法に
よるチップの磁気特性低下発生説明図、第３図は従来の
方法による実装時のチップ加圧要領図、第４図は従来の
方法による実装時の接着剤はみ出し発生説明図、第５図
は従来の方法による実装時の接着剤の他の塗布要領図、
第６図は第５図の場合に起るチップの磁気特性低下を示
すグラフ、第７図乃至第９図は本発明に係る磁気ハブル
チソプ実装方法の実施例を示すもので、第７図（ａｌ〜
（ｄｌは実装工程図、第８図は第７図（ｂ）の工程完了
状態を示す平面図、第９図は第７図（ｄｌの工程完了状
態における端子のない側の断面図である。
図中、１は基板、２は磁気バブルチップ搭載用間隙、１
１は速乾性接着剤、１２はワイヤ、１３はシリコーン樹
脂である。
特許出願人 冨士通株式会社
代理人弁理士 玉蟲久五部
（外３名）
第２図
第３図
第５図 第６図
第７図
第８図
３
第９図Figure 1 is a perspective view showing the conventional method for mounting a magnetic bubble chip, Figure 2 (taL fb), fc) is an illustration of the occurrence of deterioration in the magnetic properties of the chip due to the conventional mounting method, and Figure 3 is a diagram showing how the chip is mounted using the conventional method. FIG. 4 is an explanatory diagram of the occurrence of adhesive extrusion during mounting using the conventional method. FIG. 5 is a diagram showing another method of applying adhesive during mounting using the conventional method.
FIG. 6 is a graph showing the deterioration of the magnetic properties of the chip that occurs in the case of FIG. ~
(dl is a mounting process diagram, FIG. 8 is a plan view showing the process completion state of FIG. 7(b), and FIG. 9 is a sectional view of the side without terminals in the process completion state of FIG. 7(dl). In the figure, 1 is a substrate, 2 is a gap for mounting a magnetic bubble chip, 1
1 is a quick-drying adhesive, 12 is a wire, and 13 is a silicone resin. Patent Applicant Fujitsu Co., Ltd. Representative Patent Attorney Gobe Tamamushi (3 others) Figure 2 Figure 3 Figure 5 Figure 6 Figure 7 Figure 8 Figure 3 Figure 9
Claims (1)
ルチップを搭載し、該磁気ハブルチソプのワイヤボンデ
ィングを行なわない側と前記溝側壁との間隙の一部に速
乾性の接着剤を塗布して該磁気バブルチップを仮固定し
た後、該磁気バブルチップの端子と前記基板の端子とを
ワイヤによりボンディング接続し、最後に前記磁気バブ
ルチップおよび前記端子の接続部を覆いシリコーン樹脂
を塗布し熱硬化させることを特徴とする磁気ハブルチソ
プの実装方法。A magnetic bubble chip is mounted in a magnetic bubble chip mounting groove provided on a substrate, and a quick-drying adhesive is applied to a part of the gap between the side of the magnetic bubble chip where wire bonding is not performed and the side wall of the groove. After temporarily fixing the magnetic bubble chip, the terminals of the magnetic bubble chip and the terminals of the substrate are connected by bonding with wires, and finally, the connecting portions of the magnetic bubble chip and the terminals are covered with silicone resin and cured by heat. A method for implementing a magnetic hub chip characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57112386A JPS593779A (en) | 1982-06-29 | 1982-06-29 | Packaging method of magnetic bubble chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57112386A JPS593779A (en) | 1982-06-29 | 1982-06-29 | Packaging method of magnetic bubble chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS593779A true JPS593779A (en) | 1984-01-10 |
Family
ID=14585375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57112386A Pending JPS593779A (en) | 1982-06-29 | 1982-06-29 | Packaging method of magnetic bubble chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS593779A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7232709B2 (en) | 2003-12-19 | 2007-06-19 | Nitto Denko Corporation | Process for producing a semiconductor device |
| KR100730259B1 (en) * | 1992-03-27 | 2007-06-20 | 가부시끼가이샤 히다치 세이사꾸쇼 | Semiconductor integrated circuit device |
| JP2008205195A (en) * | 2007-02-20 | 2008-09-04 | Nitto Denko Corp | Method for manufacturing semiconductor device |
| US9153556B2 (en) | 2006-09-08 | 2015-10-06 | Nitto Denko Corporation | Adhesive sheet for manufacturing semiconductor device, manufacturing method of semiconductor device using the sheet, and semiconductor device obtained by the method |
-
1982
- 1982-06-29 JP JP57112386A patent/JPS593779A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100730259B1 (en) * | 1992-03-27 | 2007-06-20 | 가부시끼가이샤 히다치 세이사꾸쇼 | Semiconductor integrated circuit device |
| KR100753750B1 (en) * | 1992-03-27 | 2007-08-31 | 가부시끼가이샤 히다치 세이사꾸쇼 | Method of fabricating semiconductor integrated circuit device |
| USRE43443E1 (en) | 1992-03-27 | 2012-06-05 | Renesas Electronics Corporation | Leadframe semiconductor integrated circuit device using the same, and method of and process for fabricating the two |
| US7232709B2 (en) | 2003-12-19 | 2007-06-19 | Nitto Denko Corporation | Process for producing a semiconductor device |
| US9153556B2 (en) | 2006-09-08 | 2015-10-06 | Nitto Denko Corporation | Adhesive sheet for manufacturing semiconductor device, manufacturing method of semiconductor device using the sheet, and semiconductor device obtained by the method |
| JP2008205195A (en) * | 2007-02-20 | 2008-09-04 | Nitto Denko Corp | Method for manufacturing semiconductor device |
| JP4523611B2 (en) * | 2007-02-20 | 2010-08-11 | 日東電工株式会社 | Manufacturing method of semiconductor device |
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