JPS59231905A - Power amplifier - Google Patents

Abstract

PURPOSE:To attain stable operation at the stationary state by providing a means short-circuiting a resistor for driving transistor (TR) comprising push-pull connection of output TRs via said resistor at their saturation in a negative feedback power amplifier so as to reduce power consumption. CONSTITUTION:The amplifier consists of the TRs Q3, Q4 in push-pull connection to a voltage amplifier section 1 via the resistor R and TRs Q1, Q2 in Darlington connection to the TRs Q3, Q4, is provided with a power amplifier section 2 taking a connection midpoint of resistors (r), (r) as an output and an output of the amplifier section 2 is fed back negatively to an input side of the amplifier section 1. Switch means 5, 6 connected in parallel with the R are provided and they are controlled by a control means 7 so that the means 5 is conducted during the charge storage period at the saturation of the TRQ1 and the means 6 is conducted during the charge storage period at the saturation of the TRQ2. The power amplifier with less power consumption and without deteriorated stability at the stationary state is attained in this way.

Description

[Detailed description of the invention] The present invention relates to improvements in power amplifiers.

In general, a negative feedback power amplifier is, as shown in Figure 1,
The voltage amplification section (1) and the first. Second drive transistor Q3. Q4 and this first. Second drive transistor Q3. The first . It is equipped with a power amplification section (2) consisting of second output transistors Q1 and Q2 and whose output is the midpoint of the connection between the resistors r and r, and the output of this power amplification section (2) is sent to a feedback circuit (3). ) to the input side of the voltage amplifying section (1). In the figure, VBI and VB2 are positive and negative bias circuits.

Now, considering the case where the amplitude of the input signal becomes large and the first or second output transistor Ql or Q2 harmonizes, this first or second output transistor Q1
Or, during the accumulation time when the voltage value is accumulated due to the saturation of Q2 and returns from the saturated region to the active region, even if the amplitude of the input signal becomes small, the collector of the first or second output transistor Q1 or Q2 The current and emitter current cannot immediately follow the input signal, and during that time the transistor cannot perform its original operation. Such a first or second output transistor Q
1 or Q2 can be equivalently considered a small resistance during the accumulation time. For this reason, the output voltage and the input voltage are not similar, and in a negative feedback type power amplifier, a negative feedback action is performed to correct such dissimilarity, so that the first or second output transistor Q1 or Q2 It operates by applying a reverse bias between the base and emitter of the device to quickly draw out the accumulated charge.

Hereinafter, for the sake of simplicity, a case where the first output transistor Q1 is saturated will be described with reference to FIG.

With respect to the input voltage (Fig. 2(a)), the output voltage vO remains in a state at its falling edge for an accumulation time t as shown in Fig. 2(b), and the input voltage VIN do not follow. This output voltage vO is negatively fed back to the input side, and the negative feedback works to lower the output voltage VO, making the second output transistor Q2 conductive, and its collector current 1c2 (Fig. 2(d)) Since it flows through the output transistor Ql, the collector current 'I of the first output transistor Q1
C1 becomes as shown in the same figure (C). Further, due to the above negative feedback effect, the base and emitter of the first output transistor Q1 are reverse biased, and the base current IB
is as shown in Fig. 1(e), and as shown by the dotted line in Fig.
The current flows through the drive transistor Q4. At this time, the base-emitter portion of the first drive transistor Q3 is reverse biased for a short time. FIG. 2(f) shows the emitter voltage (voltage at point ■) of the first drive transistor Q3, and its falling part increases slightly due to the current It flowing through the resistor R. g) is the base voltage (0 point voltage) of the first drive transistor Q3.

In this way, the current (6) operates to draw out the accumulated charge quickly, so the smaller the resistance R is, the more the current 1/
becomes larger, and the accumulation time t also becomes shorter.

Further, when the first output transistor Ql is in a saturated state, the voltage between the emitter and collector of the second output transistor Q2 is approximately twice the power supply voltage Vcc, and during the accumulation time t. Since the collector current IC2 as shown in FIG. 2(d) flows, the second output transistor Q2
The loss is large and often leads to secondary damage.

As mentioned above, general power amplifiers have the following characteristics: Second drive transistor Q3. Since the smaller the resistance R between Q4, the shorter the storage time, various circuits have been devised.

Hereinafter, explanation will be given in order with reference to the figures.

In FIG. 3, the resistor R in FIG. 1 is replaced by a resistor 1. A series circuit (4) of second diodes Di, D2 and a resistor R' is connected, and in this configuration, the first and second drive transistors Q3. In order to make the bias current of Q4 the same as that of FIG. 1, the resistor R' may have a smaller value than the resistor R of FIG. The impedance to the current N that draws out the accumulated charge in this series circuit is the first. Second diode 6D1
The series impedance of the differential resistance of .degree.D2 and the resistor R' is smaller than the resistor R, and the accumulation time t is shorter than that of FIG. However, since the first and second diodes DI and L12 have temperature characteristics, there is a drawback that bias stability deteriorates.

FIG. 4 corresponds to the 1st section of FIGS. 1 and 3. Second drive transistor Q3. 3rd in Q4. Fourth drive transistor Q
5. Connect Q6 with push-pull respectively, and connect the first. Second
output transistor Ql.

The accumulated charge of Q2 is the third. Fourth drive transistor Q,5
．． It was designed to be extracted through Q6. However, the first. Since the driving parts of the second output transistors Ql and Q2 have a complementary push-pull configuration,
As the configuration of the bias circuit becomes complicated, the third. Fourth
The drive transistor Q5. 1st as Q6. Second drive transistor Q3. It requires a high-voltage, high-output transistor like Q4, and has the disadvantage of being extremely expensive.

The present invention improves on these conventional drawbacks, and will be explained below with reference to the drawings. In the drawings, parts equivalent to those of the conventional example shown in FIGS. 1, 3, and 4 are designated by the same reference numerals, and their explanations will be omitted.

The present invention provides a voltage amplification section (1) and a first. Second drive transistor Q3.
Q4 and this first. Second drive transistor Q3. Q4
Darlington-connected, respectively, and series-connected resistors r
, r connected via push-pull. A power amplifying section (2) consisting of second output transistors Ql and Q2, whose output is the midpoint of the connection between the resistors r and r, and the output of the power amplifying section (2) is transmitted to the voltage amplifying section. In a configuration in which negative feedback is returned to the input side of (1), 1
, a first . A second switch means and the first switch means are made conductive during a charge accumulation period when the first output transistor Q1 is saturated, and the second switch means is connected to the charge accumulation period when the second output transistor Q2 is saturated. The device is characterized in that it includes a control means for keeping conduction during the period.

Examples will be described below.

In FIG. 5, the emitter of the first driving transistor Q3 is connected to the emitter of the first switching transistor Q7, the collector of the first switching transistor Q7 is connected to the emitter of the second driving transistor Q4, and the first switch is connected. This constitutes means (5). Similarly, the second
The emitter of the driving transistor Q4 is connected to the emitter of the second switching transistor Q8, and the collector of the second switching transistor Q8 is connected to the emitter of the first driving transistor Q3, thereby forming the second switching means (6). do. Third. Fourth diode D3. D
4 are connected in series in the same direction via the first resistor R1, and the anode of the third diode D3 is connected to the base of the first drive transistor Q3, and the cathode is connected to the base of the first switching transistor Q7. , the cathode of the fourth diode D4 is connected to the base of the second driving transistor Q4, and the anode is connected to the second switching transistor Q.
8 to form a control means (7).

Hereinafter, for the sake of simplicity, a case in which the first output transistor Q1 is saturated will be described with reference to FIG. 6.

In FIG. 6, the voltage or current waveforms of each part from FIG. 6(a) to FIG. 6(g) correspond to FIG. 2(a) to FIG. 2(g), respectively.

(11 Base voltage of the first switching transistor Q7 during steady operation (0
point) and emitter voltage (0 point) are almost the same voltage, and the first
The switching transistor Q7 is in a cut-off state.

(2) At saturation Similar to the conventional example shown in FIG. 1, the base voltage (0 point) and emitter voltage (0 point) of the first drive transistor Q3 are as shown in FIG. 6 (g) and Cf>, respectively. Therefore, the base-emitter voltage (■-■) of the first drive transistor Q3 is biased during the accumulation time t as shown in FIG. The current 1c3 becomes as shown in FIG. 6(i).

Further, the base voltage (0 point) of the first switching transistor Q7 is lower than the 0 point by the forward voltage of the third diode D3. (Figure 6(j)).

Therefore, the base-emitter voltage (■-■) of the first switching transistor Q7 is forward biased and becomes conductive during the accumulation time t, as shown in FIG. 6(h), and the collector current ICA is As shown in FIG. 6 (2), the accumulated charge of the first output transistor Ql quickly flows to the second drive transistor Q4 through the first switching transistor Q7, and the accumulation time t is shortened.

Figure 7 shows the 1. Second drive transistor Q3, Q4
between the bases of the second. Third. Fourth resistor R2, R3, R4
Connect the series circuit of 1. Second. The connection point of the third resistors R2 and R3, the third. Connect the connection point of the fourth resistors R3 and R4 to the first.
Second switching transistor Q7. Another embodiment is shown in which the control means (7) is configured by connecting to the base of the first. Second drive transistor Q
3°The voltage between the base of Q4 is set to 2nd. Third. Fourth resistance R
2, R3, and R4, and the first. Second switching transistor Q7. It gives a bias to Q8.

FIG. 8 shows the structure shown in FIG. 3 using the impedance between the base and emitter of the transistor. Fourth diode D3. D4, or the second and fourth resistors R2 and R in FIG.
4 as the first. Second transistor Q9. This is another embodiment in which each is replaced with QIO.

As is clear from the above embodiments, the first. The first and second switch transistors Q7. constitute the second switch means (5) and (6). Q8 short-circuits the resistor R and connects the first.
Since it has the function of drawing out the accumulated charge of the second output transistors Q1 and Q2, the withstand voltage is only about 2V at most, and
Since the conduction time is short, the power consumption is low and it can be realized with a small signal transistor, which is cheaper than the conventional example shown in FIG. 4 and has a simpler structure. Also, in steady state,
1st. Since the second switch transistors Q7 and Q8 are in the cutoff state, the bias stability does not deteriorate as in the conventional example shown in FIG. 3. As described above, the present invention
The voltage amplification section (1) is connected to the first and second drive transistors Q3 through a resistor R in a push-pull manner. Q4, and the first and second drive transistors Q3. The first . A power amplifying section (2) consisting of second output transistors Ql and Q2, whose output is the midpoint of the connection between the resistors r and r, and the output of the power amplifying section (2) is transmitted to the voltage amplifying section. In the configuration in which negative feedback is provided to the input side of (1), the first . A second switch means is provided, and a negative feedback effect causes the first or second output transistor Q1 or Q2 to switch to the first drive transistor Q3, the first output transistor Q1 or the second drive transistor during the charge accumulation period.

4. Utilizing that the second output transistor Q2 is reverse biased, the first or second output transistor Q2 is reverse biased during the charge accumulation period.
The switch means of the first or second output transistor Ql or Q2 can be drawn out immediately by making the switch means of the first or second output transistor conductive. The second switch means has a simple configuration and low power consumption, so it can be realized at low cost, and there is no drawback such as poor bias stability during steady operation, and it is possible to provide a power amplifier with a practical IIIi value. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional power amplifier, FIG. 2 is an explanatory diagram of the same, FIGS. 3 and 4 are diagrams showing the configuration of another power amplifier, and FIG. A diagram showing the configuration of the power amplifier, FIG. 6 is the same, an explanatory diagram, FIGS. 7 and 8 are the same,
FIG. 7 is a diagram showing the configuration of another embodiment. (1,) is a voltage amplification section, (2) is a power amplification section, (5L(
6) is the first. The second switch means (7) is a control means. Patent applicant Onkyo Co., Ltd. Agent Patent attorney Sato Yatabe 1021 Bu 20 3rd UIJ

Claims (1)

[Claims] The voltage amplification section (1) and the first. The second drive transistors Q3, Q4 and the first . Second drive transistor Q3. The first . A power amplifying section (2) consisting of second output transistors Ql and Q2, whose output is the midpoint of the connection between the resistors r and r, and the output of the power amplifying section (2) is transmitted to the voltage amplifying section. In the configuration in which negative feedback is provided to the input side of (1), first and second switch means (5), (6) connected in parallel to the resistor R and short-circuiting the resistor R; The first switch means (5) is made conductive during the charge accumulation period when the first output transistor Ql is saturated, and the second switch means (6) is made conductive during the charge accumulation period when the first output transistor Ql is saturated.
A power amplifier comprising control means (7) for making the output transistor RO 2 conductive during a charge accumulation period when it is saturated.