JPS59231628A - Interruption control system of channel - Google Patents

Abstract

PURPOSE:To eliminate the delay of the processing of each frame when frame intervals are uneven, and reduce the overhead of a host CPU when frames arrive continuously by providing a channel with a timer. CONSTITUTION:The channel 2 is provided with the timer 26 in a communication system wherein the host CPU1 commands the channel 2 to execute a channel program with a read channel command word CCW when data is fetched from a terminal. Namely, the circuit 26 is actuated every time one read CCW is executed, and a program control interruption is sent out of an interruption generation part 25 to the CPU1 for the first time when the circuit 26 enters in a time-out state. Further, when a next read CCW is executed before the circuit 2 enters in the time-out state, timer cancellation is performed. Thus, the circuit 26 is provided to reduce the overhead of the CPU1, speeding up data processing.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] In the present invention, when importing data from a terminal, a host computer prepares a channel program consisting of read-channel command words and executes the program on the channel. In a data communication system where the channel executes the channel program and stores the data sent from the terminal in the buffer area, the program control interrupt of the read channel command word is delayed for a certain period of time by a timer and then sent to the host computer. This invention relates to a channel interrupt control method that is controlled as described above.

[Conventional technology and problems]

Figure 1 is a diagram explaining the outline of the machine system.
FIG. 2 is a diagram illustrating the execution of chained CCW. In FIG. 1, 1 is a host) CPU (central processing unit), 2 is a channel, 3-1 to 3-3 are terminals,
2] is the CaW fetch section, 22 is the ccwWI analysis section, 23
24 shows a CCW execution section, 24 a post-processing section, and 25 an interrupt generation section.

In FIG. 1, when importing data from terminals 3-1 to 3-3 to the host CPUUI via channel 2,
In channel 2, the CCW fetch 921 is
Read CCW (READ
Channel Command Word; read channel command word] and send it to the CC
The W analysis section 22 analyzes the read data, and the CCW execution section 23 executes it and stores the read data in the buffer area.

Generally, one buffer pointed to by the read CCW holds at most one frame (unit of data coming from the line).
It only loads. That is, as shown in FIG. 2, when the final data of the frame is read, the next read CCW is fetched. In this way, the read CCWs are chained in order to improve processing efficiency when a plurality of consecutive frames arrive. Then, when the read CCWs are chained, there is only one read CCW in the channel? It reads the data from terminal 3-1 or 3-3 continuously without sending an interrupt to the host CPU every 5% rows, stores it in the buffer, and then interrupts the host CPU at the last read CCW when the chain is broken. i channel own end (CE)
or device end (DB), etc. The post-processing unit 24 checks whether or not the CCW is chained, and if it is, transfers control to the CCWC Fetch 1, and if it is the last read COW, issues an end interrupt from the interrupt generation unit 25. host) CPU
Give it to I. The CPU (host) processes data at every opportunity. However, if there is a long time between frames and frames, it will take a considerable amount of time to finish executing the last read CCW.
interruption e, program control interrupt]
The flag may be turned on. When the PCI flag is on, channel 2 raises a host CPUIKPCI interrupt every time one CCWt is executed. This PCI interrupt allows the host CPUI to process one frame of data each time it is stored in the buffer area, thereby eliminating processing delays between frames.

In this way, when executing chained read CCWs, either a termination interrupt is raised to the host CPU at the last read CCW, or a PCI interrupt is raised for each read CCW one by one. There is. The former method of turning off the PCI flag reduces the load on the host CPU1 side, while the latter method of turning on the PCI flag reduces the load on the host CPU1 side.
Each has the advantage of being able to process data quickly.

However, in reality, the data to be read is input arbitrarily by an operator at a terminal, so the intervals between frames are usually not constant. Therefore, even if the data is sparsely read, if the delay between each frame is to be eliminated and the data is to be processed quickly, the PCI flags of all read CCWs are turned on.

As a result, the frequency of interruptions to the host) CPUI increases, and the load on the host) CPUI increases. In particular, since data that comes successively is processed one by one using PCI interrupts, processing efficiency also deteriorates.

[Purpose of the invention]

The present invention is based on the above considerations, and the present invention changes the frequency of interrupts to the host CPU depending on the frequency of frame arrival, and when the frame intervals are sparse, eliminates the delay in processing each frame. The purpose of this invention is to provide a channel interrupt control method that reduces host CPU overhead when frames arrive successively.

[Structure of the invention]

To this end, in the channel interrupt control method of the present invention, when data is imported from a terminal, the host computer prepares a channel program consisting of read operation channel command words, and executes the channel program for the channel. In a data communication system, the channel executes a channel music program and stores data sent from a terminal in a buffer area.
Equipped with a timer, every time one read channel command word is executed, all the timers are canceled if there is a timer that is activated by the execution of the read channel command word before the read channel command word. At the same time, check whether the program control interrupt flag is on or not, and start the timer on the condition that it is on.
This system is characterized in that it is configured to issue a program control interrupt to the host computer on the condition that the timer times up.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing the configuration of one embodiment of the present invention, FIG. 4 is a diagram illustrating a data processing unit, and FIG. 5 is a diagram illustrating an example of the flow of processing in a channel. In Figure 3,
1, 2. 3-1 to 3-3 and 21 to 25 correspond to those shown in FIG.
Keep the flag on and one lead ccw
Each time yc is executed, it is sent to the CPU (host) with a delay of 20
1 interrupt meeting and the next board CC during the delay period.
When executing Wt-, the 201 interrupt is controlled not to be sent to the host CPU.

In FIG. 3, timer 26 provides a delay time for the 201 interrupt in channel 2 (host).
The CCWC Fetch 1 fetches the read CCWt' from the CPU main memory (not shown), the ccwWf analysis unit 22 analyzes it, the CCW execution unit 23 executes it, and the post-processing unit 24 checks whether the read CCW is chained. If it is chained, control is returned to CCWC Fetch 1, the next load CCWt is fetched, and the same processing is performed, but if it is the last load CCW, an interrupt is sent. From the generator 25, the channel end (CE
), the end interrupt by the device end LDE) is raised to the host) CPUI. In such a processing process, conventionally, every time one read CCW was executed, a 201 interrupt was immediately issued from the interrupt generation unit 25 to the host CPUI, but in the present invention, one read CCWt
- The timer 26't'' is started every time it is executed, and when the timer 26 times out, the 201 interrupt is triggered @11
The error is sent from the error generating unit 25 to the host CPUI. Before timer 26 times out, the next read c
When executing cwv, cancel the timer.

Therefore, as shown in the fourth review, when data is received intermittently, a 201 interrupt is generated each time the timer 26 times out, and data processing is performed by the host ePU 1. As shown in [
For incoming data.

The timer is canceled without timing out in the middle, and it times out when the data is interrupted, and then a 201 interrupt is raised for the first time, and data processing is performed by the host) CPtJl. In the example shown in Figure 4, etc., one
The three pieces of data are processed together by the 01 interrupt, which reduces the number of interrupts and reduces the burden on the host C)) U1. Timer 26 is read C
Since the CW PCI flag is activated on the condition that it is on, either the CCW analysis unit 2019 CW execution unit 23 or the post-processing unit 24 examines the PCI flag and controls its activation. However, the control pipe post-processing section 2
FIG. 5 shows an example of the case where this is done in step 4.

In the fifth C, the CCW execution unit executes the read CCW, checks whether or not the read CCW requires timer setting, and if it requires timer setting, sets the timer value. . The post-processing section first performs timer cancellation processing if it has been activated by the previous CCW and has not timed out yet. Then PCI beep)? fJbe,
If it is on, after starting the timer, read CC
Check whether W is chained. If it is chained, control is returned to the CCW fetch unit. However, if it is not chained, the timer value 70 is cleared and an end interrupt (CE%DE) k is sent to the host CPU. Furthermore, when the timer times out, a 201 interrupt is issued to the host CPU. Note that the timer value to be set can be set arbitrarily, and if the timer setting is not required, the timer value should be set to 0. When executing the first read ccwt-, the timer value should be given from the host CPU. Good too.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, since the number of 201 interrupts to the host CPU is reduced, the number of running steps of the host CPU is reduced, and the interruption data that requires 201 interrupt processing is reduced. On the other hand, 1) CI interrupt processing can be performed, and data processing can be speeded up.

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the outline of the computer system, Figure 2 is a diagram explaining the execution of chained Ccw, and Figure 3 is a diagram explaining the execution of chained Ccw.
FIG. 4 is a diagram illustrating the configuration of an embodiment of the present invention, FIG. 4 is a diagram illustrating salary for data processing, and FIG. 5 is a diagram illustrating an example of the flow of branding in a channel. 1... host) CPU, 2... channel, 3-1 to 3-3... terminal, 21... ccw fetch unit, 2
2... CCW analysis section, 23... ccw execution section, 24
...Post-processing section, 25... Interrupt generation section, 26...
timer. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Kyotani Shibeda 1 Figure 5 Wz Kuken 3 Figure) X 4 Figure

Claims (1)

[Claims] When importing data from a terminal, the host computer prepares a channel program consisting of read channel command words, instructs the channel to execute the above channel program, and the channel executes the channel program to read the data from the terminal. In a data communication system in which data sent from a read channel command word is stored in a buffer area, the channel is equipped with a timer, and each time one read channel command word is executed, the data sent from the read channel command word is stored in a buffer area. If there is a timer that has been started by executing a channel command word, cancel that timer, check whether the program control interrupt flag is on, and start the timer on the condition that it is on.
A channel interrupt control method characterized in that the channel interrupt control method is configured to issue a program control interrupt to a host computer on the condition that a timer times up.