JPS59230325A - Generator of gate on/off control pulse - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution and to prevent the generation of malfunction by quantizing a gate control signal with a clock pulse having the time width larger than the discharge time of a snubber circuit. CONSTITUTION:A gate control signal is supplied to a terminal GO, and a clock pulse CLK having the time width larger than the discharge time of a snubber circuit is supplied from an oscillator 250. A gate ON/OFF control pulse generator 300 consisting of a flip-flop 301, an AND circuit 302 and a flip-flop 303 delivers a signal quantized by the pulse CLK so as not to output such a signal having small width like a noise. Thus a self-arc extinguishing element is chopped to prevent a malfunction due to noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for driving the gate or pace of an element having a self-blocking ability such as a GTO thyristor or transistor, and particularly to a drive control pulse generator for the element.

[Background of the invention]

Conventionally, self-extinguishing switching elements such as transistors are chopped to control the average voltage applied to a load such as a motor or a resistor, thereby controlling the current flowing to the load. This means that if the load is a motor,
It controls the speed of the motor, and if it is a resistor, it controls the heat generation. In this chopping control, a snubber circuit is generally installed in parallel with a self-extinguishing switching element such as a transistor, as shown in Figure 1, in order to prevent the element from being damaged by the voltage applied to the element when it is turned off. It is being That is, the load 100 is connected to the power supply 102. A wiring inductance 101 is isometrically connected to this load 100. The collector of the transistor 2 and the snubber capacitor 3 are connected to the load 100. This snubber capacitor 3
The snubber resistor 4 and the anode of the snubber diode 5 are connected to the snubber resistor 4 and the anode of the snubber diode 5. Further, the other end of the snubber resistor 4 and the cathode of the snubber diode 5 are connected to a power source 102. Still, the emitter of the transistor 2 is connected to the power supply 102 and the base is connected to the gate driver 10. In the figure, IL is the load current, Is is the snubber discharge current, and V c z (t) is the voltage applied between the collector and emitter of the transistor 2.

Now, the switching operation of transistor 2 in this circuit will be explained.

First, as shown in FIG. 2 (3), when the output from the gate driver 10 is LOW, the transistor 2 is off, and the voltage (Vent) of this transistor 2 is the voltage of the power supply 102 as shown in FIG. The voltage E is shown. When the output from the gate driver 10 becomes HIGH (ON), the transistor 2 turns on, and Vex(t) of this transistor 2
As shown in FIG. 2(b), the voltage decreases during the time Tw that the transistor 2 is on according to the discharge time constant determined by the snubber capacitor 3 and the resistor 4 of the snubber circuit.

This time Tw is the output on-pulse width of the gate driver 10.

At this time, the voltage VCI between the collector and emitter of transistor 2 (is 1 Vcz(t)=E ・t ”” −(
1). Here, t is the on-pulse time T of the transistor 20 (a), the value of the snubber capacitor 3 is Cs, and the value of the snubber resistor 4 is B, then V in Figure 2
The value of c tro is as shown in equation (1).

Next, when the output pulse of the gate driver 10 changes to LOW, that is, when the transistor 2 turns off, the voltage E of the power supply 102 also jumps due to the action of the wiring inductance 101, as shown in FIG. Now, if this maximum value is Vex (wAx), then Vc+c (MAX) is ~. Here, IL is the load current as shown in FIG. This bounce is temporary and will eventually occur.
The voltage converges to the voltage E of the power supply 102 as shown in FIG. 2 α■.

Now, according to equation 1 (3), the jump amount Δ of Vcz (MAX) is
Vc ΔVcw = Vc MAX E
”・When calculated as (4), Δvc is as follows. Substituting equation (2) into equation (5), ΔV
c v becomes. From this equation (6), the gate pulse on time Tw output from gate driver 0 is C+
If it is not a large value with respect to +Rs, the jump amount Δ
If V c z is a large value, it will exceed the allowable maximum collector-emitter voltage Vczwhx (allowable) of transistor 2 and destroy transistor 2. Therefore, Vczwhx (tolerance)>E+ΔVc+c
``17).

Now, the on time Tw and CI of transistor 2! 'fLs
If the relationship is Tw=CsRs, then the jump stain pressure ΔV c v is, and if the relationship between the on-time TV of transistor 2 and CgR,11 is Tw=30sRg, then the jump voltage ΔV c z is, Assuming that the relationship between the on-time Tw of the transistor 2 and CgRs is Tw=5CgRa, the upward stain pressure ΔVc is as follows. Here, 0°368E is the snubber capacitor 3
0.050E means that approximately 63'16 of the voltage charged in
07E is said to have been discharged for about 99.3 hours.

Therefore, the on time Tw of transistor 2 is CllR
Theoretically, the above equation (7) can be satisfied if the value is equal to or higher than 11. Therefore, it is necessary to give the on-pulse width of the transistor 2 a pulse width Tw that is equal to or larger than the snubber discharge time constant CsR5.

In order to obtain such a pulse width Tw larger than the left snubber discharge time constant CsR5, a gate pulse generator as shown in FIG. 3 has been devised.

In the figure, a gate control signal is input from a terminal Go to an AND circuit 201, an AND circuit 202, and a reset terminal of a counter 205. A clock pulse is input to this AND circuit 201 from the oscillator 150. The output of this AND circuit 201 is input to a count input terminal of a counter 205. This counter 205 is
It is a binary counter, and the output signal is input to the comparator 206 as a binary number. Further, the output of the AND circuit 202 is configured to be input to one input terminal of the OR circuit 203. The other input terminal of this OR circuit 203 is connected to the output terminal of a one-shot multi-by-break 204.

The one-shot multivibrator 2040 is configured to receive an output signal from the comparator 206 at its input terminal. Also, the output of this comparator 206 is AND
The signal is configured to be input to another input terminal of the circuit 202 and a hold terminal of the counter 205, respectively. Further, the comparator 206 is configured to receive a comparison reference value output from the comparison reference data setting device 207. The AND circuits 201 and 202, the OR circuit 203, the one-shot multivibrator 204, and the counter 205
, comparator 206, and comparison reference data setter 207 constitute a gate on/off control pulse generator 20.0.

Next, the operation of the circuit shown in FIG. 3 will be explained.

First, a gate control signal as shown in FIG. 4 (G) is inputted from the terminal Go. On the other hand, a clock signal output from oscillator 150 is input to AND circuit 201 . This AND circuit 201 performs the theoretical product of the clock signal output from the oscillator 150 and the gate control signal as shown in FIG. 205 counts. Therefore, in this counter 205, the fourth
The HIGH time width in Figure (4) is counted. This counter 205 outputs a count value QCN as shown in a in FIG. 4(6), and the count value QCN as shown in a in FIG.
It is compared with the comparison reference value QCR shown in b. This comparator 206 operates only when the output from the counter 205 is larger than the output value from the comparison reference data setter 207, as shown in FIG. 4 (0).

Outputs a HIGH signal. The count value of the counter 205 is held by the output from the comparator 206. This counter 205 is connected to terminal G.

Reset at the falling edge of the gate control signal input from (9) be tested.

Furthermore, in response to the rise of the signal output from the comparator 206 as shown in FIG. 4 (Q), the one-shot multivibrator 204 outputs a signal with a constant pulse width as shown in FIG. A signal as shown in FIG. 4 0 outputted from the shot multivibrator 204 and A
A logical sum is taken with the output signal from the ND circuit 202, and O
The R circuit 203 outputs a driver input signal as shown in FIG. 4 (G).

By the way, if the period of the clock CLK output from the oscillator 150 is Tel, and the HIGH time width of the gate control signal D1 input to the terminal Go is Tnl, then the condition TDI > TCLICX Q CR-(11) is satisfied. Since a>b holds only when TDI is narrow, there is no output from comparator 206 and no signal is output from one-shot multivibrator 204. Furthermore, when TDI becomes wider, the OR circuit 203 outputs a driver input signal (10). Note that even if the pulse width of the signal output from the comparator 206 becomes narrow, the width of the driver input signal does not become narrow. This is due to the action of the one-shot multivibrator 204.

In this way, in the conventional circuit shown in FIG. 3, the one-shot multivibrator 204 is not directly connected to the gate control signal, so there is no chance of accidentally outputting an on-pulse in response to the gate control signal that comes in as noise. .

However, it has the disadvantage that the circuit is complicated and the number of nodes is large, making it expensive.

In addition, since a one-shot multivibrator is used, it is possible to deal with noise that enters the gate on/off control pulse generator, but noise that enters the one-shot multivibrator itself can cause malfunction. It has the disadvantage that it occurs.

Furthermore, the one-shot multivibrator requires components such as a capacitor and a resistor (11) to determine its operating time, so it has the disadvantage that it is difficult to make it into a highly integrated IC.

[Purpose of the invention]

An object of the present invention is to turn on/off equipment such as motors with a simple circuit.
It is an object of the present invention to provide a gate on/off control pulse generator that does not cause a self-extinguishing switching element that performs off control to malfunction due to noise.

[Summary of the invention]

The present invention quantizes the gate control signal using a clock pulse having a time width equal to or longer than the discharge time of the snubber circuit, converts the gate control signal into a pulse signal that is an integral multiple of the clock pulse, and then converts the gate control signal into a pulse signal that is an integral multiple of the clock pulse. The idea is to simplify the circuit and prevent malfunctions by using the gate signal as the gate signal.

[Embodiments of the invention]

Examples of the present invention will be described below.

FIG. 5 shows an embodiment of the invention.

In the figure, the terminal (12) Go to which the gate control signal is input is connected to the D input terminal of the flip-flop 301 and the A
One input terminal of the ND circuit 302 is connected. The oscillator 25 is connected to the T input terminal of this flip-flop 301.
A clock signal CLK output from 0 is input. Further, the output Q terminal of this flip-flop 301 is connected to the other input terminal of an AND circuit 302.

The output terminal of this AND circuit 302 is connected to the D input terminal of a flip-flop 303. A clock signal CLK output from the oscillator 250 is input to the T input terminal of the flip-flop 303. Further, a terminal S is connected to the output terminal Q of this flip-flop 303. This terminal S is the same as the terminal S shown in FIG. Therefore, this terminal S has a gate driver 10
The following circuits are connected. The flip-flops 301 and 303 are both edge trigger Da flip-flops, and the state of the D input is latched by the rising edge of the clock T terminal.

These flip-flops 301, 303 and AND(13
) A gate on/off control pulse generator 300 is configured by the circuit 30.

Since it is configured in this way, the terminal Go
When a gate control signal as shown in FIG. 6 is input to the oscillator 250, and a clock signal as shown in FIG.
The gate control signal D1 is triggered and held at the rising edge of the clock signal, and a signal that is reset by the clock signal immediately after the gate control signal becomes LOW is output. That is, the flip-flop 301 outputs a signal as shown in FIG.
The AND value with the gate control signal as shown in FIG.

Therefore, the AND circuit 302 outputs a signal as shown in FIG. Based on this signal, the flip-flop 303 holds the trigger at the rising edge of the clock signal output from the oscillator 250, and is reset by the clock signal immediately after the signal output from the AND circuit 302 (14) becomes LOW. A signal as shown in FIG. 6 [F] is output.

Note that the period of the clock pulse output from this oscillator 250 is the same as the discharging time of the snubber circuit in this embodiment.

Therefore, in response to a gate control signal such as a in FIG. 6, a driver input signal as shown in FIG. 6 [F] is output, but a driver input signal as shown in FIG. The gate control signal shown in (2) whose period is less than one clock of the clock CLK does not operate the flip-flop 301 and the driver input signal is not output. In addition, as shown in C of FIG. 6 (4), the gate control signal is clocked by the clock CLK.
, the flip-flop 3
01 operates as shown in FIG. 6 (Q) and outputs a pulse for one clock cycle, but the flip-flop 303 does not operate and no output is made as shown in FIG. 6 [F].

In this way, unless the gate control signal has a pulse width of one clock or more, the driver input signal (15) will not be output. In this way, malfunctions due to signals such as noise are prevented.

In this way, in this embodiment, the clock period is adjusted to the snubber discharge time constant Tan, and the gate control signal is chopped using this clock signal. It will be a minute. Therefore, the time width of the gate control signal is TC! ?
If L, then TC! TL = n-TCLK
...(12). Therefore, n is a positive integer of 0°1.2.3... proportional to the width of Tcrb. That is, the clock period TcLt is the minimum gate control signal unit.

Therefore, according to this embodiment, by making the minimum unit of the gate control signal equal to or greater than the discharge time constant of the snubber, it is possible to eliminate unlimited narrow gate control signals.

FIG. 7 shows another embodiment of the invention.

In this embodiment, six (n) gate control pulse generators 300 (16) shown in FIG. 5 are arranged in parallel, and can process six (n) gate control signals. This is how it was done. Further, the oscillator 350 is the oscillator 25
The 1/n' frequency dividing circuit 4 outputs a clock signal with a period n' times the clock signal period T (!I, 0).
00 returns to the original Tct, x. This is a modification of the above equation (12).

Therefore, according to this embodiment, the same effects as the embodiment shown in FIG. 5 can be obtained.

Another embodiment of the invention is shown in FIG.

In the figure, the terminal Go has D of the shift register 501.
Input terminal is connected. This shift register 501
A clock signal CLK output from the oscillator 250 is input to the 0T input terminal, and the shift register 50
1 output terminals Q1 to QN are connected to an AND circuit 502 and an N
An AND circuit (17) 503 is connected. The output of this AND circuit 502 is input to the set terminal S of the R8 flip-flop 5040, and the output of the NAND circuit 503 is input to the reset terminal R of the RS flip-flop 504. A terminal S is connected to the output Q terminal of this 7-lip 70 tube 504. This terminal S has a gate driver 1 as shown in FIG.
Circuits after 0 are connected.

This shift register 501, the AND circuit 502, and the N
A gate on/off control pulse generator 500 is configured by an AND circuit 503 and an RS flip-flop 504.

Next, the operation of this embodiment will be explained using a four-stage shift register with reference to FIG.

A signal as shown in FIG. 9 is input from the oscillator 250 to the shift register 501. Now, terminal Go has the 9th
When a gate control signal as shown in FIG.
A HIGH signal as shown in FIG. 9 (18) 0 is output from. This output terminal Q1 outputs the LOW gate control signal to the clock signal CL.
Catch it on K's rise and go down to LOW. The output terminal Q2 of the shift register 501 receives a clock signal based on the output signal of the output terminal Q1, and similarly to the output terminal Ql, a signal as shown in FIG. 9 is output. Similarly, a signal as shown in FIG. 9 is output from the output Q3 terminal, and a signal as shown in FIG. 9 is output from the output Q4 terminal. In this way, the output terminals Ql-Q4 of the shift register 501 have the same width, but are output as signals whose rising edges are shifted by one clock cycle. This output is
An AND circuit 502 performs a logical product and outputs a signal as shown in FIG. 90. In addition, the NAND circuit 503
A signal as shown in FIG. 90 is outputted from the circuit. At the rising edge of the signal as shown in this figure 9,
A signal as shown in FIG. 9(I) which falls at the rising edge of the signal shown in FIG. The output signal from this RS flippuff (19) Rozzo 504 becomes the driver's manual signal. This is a modification of the above equation (12).

This is equivalent to n' times the oscillator frequency (the period is 1/n' times), generates a clock signal, samples the gate control, and counts n' gate control signals. There is. In this embodiment, the number of shift stages of the shift register is set to four, and this number of stages is equal to n' in equation (14) above.
The frequency of the oscillator 250 is selected so that the clock period TCLK is TCI.

Note that in this embodiment, when the gate control signal is HIGH
If the level does not last for four clocks as shown in the ninth drawing, the RS flip-flop 504 will not be set and will be cut.

Therefore, according to this embodiment, it is possible to obtain the same effects as those of the above-mentioned embodiments.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to prevent a self-extinguishing switching element that performs simple (20) times*+ on/off control of equipment such as a motor from malfunctioning due to noise. be able to.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a device to which the present invention is applied, FIG. 2 is a waveform diagram of FIG. 1, FIG. 3 is a circuit diagram of a conventional gate-on-off control pulse generator, and FIG. 3 is a time chart, FIG. 5 is a circuit diagram showing an embodiment of the present invention, FIG. 6 is a time chart of FIG. 5, FIG. 7 is a diagram showing another embodiment of the present invention, and FIG. Figure 9 showing another embodiment of the present invention
The figure is the time chart of FIG. 250.350... Oscillator, 300,500... Gate on/off control pulse generator, 301-303
...7 lip-flop, 302...AND circuit. Agent Patent attorney Tatsuyuki Unuma (21) Grass I, $2 days

Claims (1)

[Claims] 1. In a device in which a snubber circuit consisting of a capacitor, a resistor, and a diode is connected in parallel and a self-extinguishing switching element that chops a load such as a motor is turned on and off via a gate driver based on a gate control signal, A gate on/off control pulse generator characterized in that the gate control signal is quantized by a clock pulse having a cycle equal to or longer than the snubber discharge time constant and outputted to the gate driver as a pulse signal having an integral multiple of the clock pulse.