JP3271545B2 - Malfunction prevention circuit when power supply voltage rises - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a malfunction prevention circuit when a power supply voltage rises, and more particularly to a malfunction prevention circuit when a power supply voltage rises formed on the same semiconductor substrate as another semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, an analog timer circuit (hereinafter, referred to as a timer circuit) which outputs a pulse after a predetermined time has elapsed after a trigger pulse is input has been widely used.

A conventional timer circuit will be described with reference to FIGS. 5, 6, and 7. FIG. 5 is a block diagram of a conventional timer circuit 100 and a peripheral circuit diagram of the timer circuit 100, and FIG. 6 is a timer circuit shown in FIG. 100 is an equivalent circuit diagram, and FIG. 7 is a signal waveform diagram showing the operation of the timer circuit 100.

In FIG. 5, a timer circuit 100 includes comparators 11 and 14, a flip-flop 12, a PNP transistor Q1, an NPN transistor Q2, and an output circuit 1.
3 and resistors R1, R2, R3.

There are eight external terminals in total, and GN
A D terminal 1, a trigger terminal 2 for inputting a trigger pulse,
An output terminal 3 for taking out an output pulse of the timer circuit 100 via the load resistor Rl, a reset terminal 4 for forcibly resetting the timer circuit 100 and setting the output terminal 3 to a low level, and a reference voltage supplied to the comparator 14. , An input terminal 6 of the comparator 14, a discharge terminal 7 connected to the collector of the NPN transistor Q2 for discharging the capacitor Cx constituting a peripheral circuit, and a power supply terminal 8.

The peripheral circuit includes a trigger pulse generator 9 for supplying a trigger pulse to the trigger terminal 2 and a load resistor Rl.
And a resistor Rx and a capacitor Cx which determine the time constant of charging and discharging.
Consists of

Next, the operation of the conventional timer circuit 100 will be described with reference to FIGS.

First, when the power supply voltage Vcc rises from 0V, the power supply voltage Vcc from the power supply terminal 8 via the resistors R1, R2 and R3.
A current flows toward the ND terminal 1 to generate a bias voltage at the base of the NPN transistor Q15. For the timer circuit 100 to operate normally, the bias current of the comparator 14, that is, the current flowing through the resistor R4 is about 40 μA
At least, the base potential VB of the NPN transistor Q15 is required to be equal to the NPN transistor Q1.
4, the forward voltage of the emitter-base of Q15 is 0.6V,
Assuming that the resistance value of the resistor R4 is 10KΩ, VB = 0.6 × 2 + 0.04mA × 10KΩ = 1.6V. Therefore, assuming that the resistance values of the resistors R1, R2, and R3 are all equal, the power supply voltage Vcc at this time is as follows: Vcc = VB ・ /2≒2.4V. That is, the timer circuit 100 supplies the power supply voltage Vcc.
Performs a normal operation at 2.4 V or more.

Next, the operation of timer circuit 100 when power supply voltage Vcc is 2.4 V or more (normally 4.5 V or more) will be described. At time t0 in FIG. 7, since the trigger terminal 2 is at the high level, the PNP transistors Q6 and Q7 are turned off, and the base current is not supplied to the NPN transistor Q9, so that the NPN transistor Q9 is turned off.
Also, since the NPN transistor Q10 turns on, NP
The base of the N transistor Q11 becomes low level,
The PN transistor Q11 turns off. Further, the NPN transistor Q12 turns on, and the NPN transistor Q13
Supply the base current to the NPN transistor Q13
Turns on, and the output terminal 3 goes low. Also, NP
The N-transistor Q2 is also turned on in response to the supply of the base current from the NPN transistor Q12, and both the input terminal 6 and the discharge terminal 7 have the GND potential.

Next, when the trigger terminal 2 goes low at time t1 in FIG. 7, the PNP transistors Q6 and Q7 turn on, and the PNP transistors Q7
9 supplies the base current to the NPN transistor Q
9 turns on. Therefore, the NPN transistor Q10 is turned off and the NPN transistor Q11 is turned on.
The N transistors Q12 and Q13 are both turned off, and the output terminal 3 goes high. Also, the NPN transistor Q2
, The base current is not supplied from the NPN transistor Q12, the NPN transistor Q2 is turned off, and a current flows from the power supply terminal 8 in FIG.
The capacitor Cx starts charging. Further, the voltage of the input terminal 6, that is, the voltage of the capacitor Cx, increases from the time t1 with a time constant determined by the resistor Rx and the capacitor Cx as shown in FIG.

On the other hand, as can be seen from the equivalent circuit diagram of FIG. 6, when the resistances R1, R2, and R3 are all equal, Vr = Vcc.multidot.2 / 3. Therefore, the voltage of the input terminal 6 becomes Vcc at time t2 in FIG.
When に な る, NPN transistors Q3 and Q4 are both turned on, so PNP transistor Q5 is turned on.

Therefore, the NPN transistor Q8 is connected to the PNP
The base current is supplied from the transistor Q5 to turn on, and the NPN transistor Q10 turns on. For this reason, NP
The N transistor Q11 turns off and the NPN transistor Q
Since both Q12 and Q13 are turned on, the output terminal 3 has the GND potential as shown in FIG. 7B. Further, since the NPN transistor Q12 is turned on, the NPN transistor Q2 is also turned on and the capacitor Cx is connected to the NPN transistor Q2.
, And the discharge terminal voltage also becomes the GND potential as shown in FIG.

When the power supply voltage Vcc is lower than 2.4 V, a sufficient emitter-collector voltage cannot be supplied to the NPN transistor and the PNP transistor constituting the timer circuit 100.
00 becomes an unstable state in terms of a circuit, and even if a trigger pulse is not input to the trigger terminal 2, the output voltage becomes high level and a malfunction may occur.

As a method of improving the above-mentioned disadvantages of the conventional timer circuit 100, as shown in FIG.
It has been practiced to connect a zero to a malfunction prevention circuit 200 when the power supply voltage rises, comprising a resistor Rr, a capacitor Cr, a diode Dr, and a Schmitt trigger circuit 15, 16. In the malfunction prevention circuit 200 when the power supply voltage rises, the input voltage of the Schmitt trigger circuit 15 is regarded as low level when the power supply voltage Vcc is low, so that the output voltage of the Schmitt trigger circuit 15 becomes high level. Therefore, the input of the reset terminal 4 becomes low level, and as can be seen from FIG. 5, the output terminal 3 is also forced to low level.

When the power supply voltage Vcc rises, the input voltage of the Schmitt trigger circuit 15 goes high, and the reset terminal 4 goes high, so that the PNP transistor Q1 is turned off. Therefore, the timer circuit 100 operates normally as described above.

[0016]

In the conventional malfunction prevention circuit at the time of the rise of the power supply voltage, the reset time determined by the resistor and the capacitor needs to be longer than the rise of the power supply voltage supplied to the timer circuit. The time design must be redesigned each time a system is designed using a timer circuit.

Further, since it is necessary to individually mount a resistor, a capacitor, a diode, and a Schmitt trigger circuit on a mounting board and to wire these components, there is a problem that the mounting board cannot be reduced in size.

Therefore, an object of the present invention is to provide a circuit such as a timer circuit in which the rising characteristic of the power supply has a significant effect on the circuit characteristics without considering the reset time, and the input of the target circuit when the power supply voltage rises. Prevents the terminal or output terminal from inverting or becoming unstable, and malfunctions when the power supply voltage rises above a predetermined value determined by the threshold voltage generation circuit, at the time of a voltage rise that is electrically disconnected from the target circuit. It is to provide a prevention circuit.

It is a further object of the present invention to provide a malfunction prevention circuit at the time of rising of a power supply voltage which has a reduced mounting board area by being mounted on the same semiconductor substrate as a timer circuit and the like.

[0020]

Therefore, a malfunction preventing circuit according to the present invention at the time of rising of a power supply voltage is provided with a threshold voltage generating circuit connected to a power supply and outputting a threshold voltage, and receiving the threshold voltage. Of the target circuit to be controlled
An input / output terminal control circuit that outputs a control voltage to an input / output terminal; and a malfunction prevention circuit at the time of power supply voltage rise, wherein the power supply voltage is a predetermined value determined with reference to the threshold voltage. If lower than the said control voltage and a low level or high level, if the power supply voltage is higher than the previous Kisho value is characterized in that the high impedance entering-output pin.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of a timer circuit with a malfunction prevention circuit at the time of rising of the power supply voltage according to the present invention, which comprises comparators 11 and 14, a flip-flop 12, an output circuit 13, and the like. A conventional timer circuit 100 and a malfunction prevention circuit 210 at the time of rise of the power supply voltage.

The description of the conventional timer circuit 100 is omitted, and the malfunction preventing circuit 210 at the time of rising of the power supply voltage will be described. The malfunction prevention circuit 210 when the power supply voltage rises includes an input / output terminal control circuit 210
A and a threshold voltage generation circuit 210B.
The input / output terminal control circuit 210A includes NPN transistors Q21 and Q22 and a resistor R21, and the threshold voltage generation circuit 210B includes diodes D21 to D23 and a resistor R22. NPN transistor Q2
1 has an input / output control terminal 210C and an output terminal 3
The collector and the base of the NPN transistor Q22 are connected to the base of the NPN transistor Q21 and the cathode of the diode D23, respectively. Also, diodes D21, D22, D2
Reference numeral 3 denotes a cascade connection, and the anode of the diode D21 is connected to a power supply via a resistor R22.

Next, the operation of the malfunction prevention circuit 210 when the power supply voltage rises according to the present invention will be described.

When the power supply voltage Vcc is low, the NPN transistor Q22 is turned off, and the NPN transistor Q21 is turned on and saturated because the base current is supplied via the resistor R21. Therefore, the output terminal 3 becomes low level regardless of the operation state of the timer circuit 100.

Next, when the power supply voltage Vcc rises until the following equation (1) is satisfied, the NPN transistor Q22 turns on.

Vcc = Vbe (Q22) + 3Vbe + i22 · r22 (1) Here, Vbe (Q22) is an NPN transistor Q22.
Is the forward voltage between the emitter and the base, Vbe is the forward voltage between the anode and the cathode of the diodes D21 to D23, r
22 is a resistance value of the resistor R22, and i22 is a current value flowing through the resistor r22. When the power supply voltage Vcc becomes higher than the value given by the equation (1), the NPN transistor Q22 is turned on, the NPN transistor Q21 is turned off, and the timer circuit 100 is disconnected from the malfunction prevention circuit 210 when the power supply voltage rises. The operation of the circuit 100 alone is started.

That is, when the power supply voltage Vcc is lower than the value of the equation (1), the malfunction prevention circuit 210 at the time of the rise of the power supply voltage operates, and the output terminal 3 is connected to the timer circuit 100.
Becomes low level irrespective of the operation state of. Also, (1)
The power supply voltage Vcc given by the equation is applied to the voltage VB of the control terminal 5.
When equal to 3/2, the power supply voltage supplied to the timer circuit 100 rises to the power supply voltage required for the operation of the timer circuit 100, and at the same time, the malfunction prevention circuit 210 at the time of the power supply voltage rise stops operating, and the timer circuit 100 Start operation.

The malfunction preventing circuit 210 at the time of rising of the power supply voltage according to the present invention is composed of a transistor, a resistor, and a diode.
Are formed in the same process as the circuit element constituting the semiconductor device, so that the manufacturing process is not complicated.

The on-resistance of the NPN transistor Q21 must be sufficiently smaller than the load resistance R1 (about 5 KΩ). However, the current driving capability of the NPN transistor Q21 is sufficiently large, so that the NPN transistor Q21 has a small area. It is possible to design Q21.

Further, when noise is mixed in the power supply, the resistor R22, diodes D21 to D23 and NP
Since the impedance when the GND terminal 1 is viewed through the N-transistor Q22 is sufficiently low, the threshold voltage for turning on the NPN transistor Q22 is not affected by noise.

Next, a second embodiment of the present invention will be described with reference to FIG.

The malfunction prevention circuit 220 when the power supply voltage rises includes an input / output terminal control circuit 210A and a threshold voltage generation circuit 220B. The input / output terminal control circuit 210A is the same as that of the first embodiment. In the threshold voltage generation circuit 220B, an NPN transistor Q23 in which a resistor R23 is connected between an emitter and a base and a resistor R24 is connected between a base and a collector is connected between the base of the NPN transistor Q22 and the resistor R22.

The emitter-collector voltage Vce of the NPN transistor Q23 is given by the following equation (2).

Vce = Vbe (Q23) · (1 + r24 / r23) (2) Here, Vbe (Q23) is an NPN transistor Q23.
, And r23 and r24 are resistance values of the resistors R23 and R24, respectively. By arbitrarily determining the ratio between r24 and r23 in the equation (2), NP
Emitter-collector voltage Vc of N-transistor Q23
e can be set to any value. Therefore, in the first embodiment, it is not necessary to increase the threshold voltage at which the NPN transistor Q22 is turned on by cascading a large number of diodes, and the NPN transistor Q23 and the resistors R23 and R24 turn on the NPN transistor Q22. The feature is that the threshold voltage can be determined.

Next, a third embodiment of the present invention will be described with reference to FIG.

The malfunction preventing circuit 230 when the power supply voltage rises includes an input / output terminal control circuit 210A and a threshold voltage generation circuit 230B. The input / output terminal control circuit 210A is the same as that of the first embodiment. The threshold voltage generation circuit 220B includes resistors R25 and R26.

In the threshold voltage generation circuit 220B,
Base voltage Vb (Q22) of NPN transistor Q22
Is determined by the following equation (3).

Vb (Q22) = Vcc · r25 / (r25 + r26) (3) Here, r25 and r26 are resistance values of the resistors R25 and R26. As can be seen from equation (3), Vb (Q22)
By setting r25 and r26 such that = VB ・ 3/2, when the power supply voltage Vcc becomes higher than the power supply voltage determined by the equation (3), the NPN transistor Q22 is turned on, the NPN transistor Q21 is turned off, and the power supply voltage is turned off. The malfunction prevention circuit 230 at the time of rising is a timer circuit 100
And the original operation of the timer circuit 100 is performed.

In the present embodiment, as can be seen from equation (3), the base voltage Vb (Q2
Since 2) can be determined only by the resistance ratio, the threshold voltage of the malfunction prevention circuit when the power supply voltage rises can be accurately determined.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

The malfunction prevention circuit 240 when the power supply voltage rises includes an input / output terminal control circuit 240A and a threshold voltage generation circuit 240B. The input / output terminal control circuit 240A includes N-channel transistors N1 and N2 and a resistor R29. Is done. The threshold voltage generation circuit 240B includes an N-channel transistor N3 and a resistor R2.
7, R28 and an N-channel transistor N1
Is connected to the input / output control terminal 240C, the gate is connected to the drain of the N-channel transistor N2, and the resistance R
It is pulled up to the power supply via 29. The gate of the N-channel transistor N2 is connected to the resistor R27 and the source of the N-channel transistor N3, and the gate of the N-channel transistor N3 is connected to the source and operates as a diode. The drain of the N-channel transistor N3 is connected to a power supply via a resistor R24.

Next, the operation of the malfunction prevention circuit 240 when the power supply voltage rises will be described.

When the power supply voltage is low, the N-channel transistor N2 is off because the gate of the N-channel transistor N2 is at low level. On the other hand, since the gate of the N-channel transistor N1 is pulled up to the power supply via the resistor R21, the N-channel transistor N1 is turned on and the output terminal 3 is stabilized at a low level. Next, when the power supply voltage Vcc becomes larger than the value determined by the following equation (4), the N-channel transistor N2 turns on.

Vt (N2) = (Vcc−Vt (N3)) · r27 / (r27 + r28) (4) where Vt (N2) and Vt (N3) are thresholds of the N-channel transistors N2 and N3. The value voltages r27 and r28 are the resistance values of the resistors R27 and R28. Vt (N2) = V
If t (N3) = Vt, equation (4) becomes equation (5).

Vcc = (2 + r28 / r27) · Vt (5) When the power supply voltage Vcc becomes larger than the value determined by the equation (5), the N-channel transistor N2 is turned on, and the gate of the N-channel transistor N1 is set to the low level. , The N-channel transistor N1 is turned off, and the malfunction prevention circuit 240 when the power supply voltage rises is
Since it is separated from 0, the timer circuit 100 starts its own operation corresponding to the trigger pulse or the like.

Since the malfunction preventing circuit 240 at the time of the rise of the power supply voltage according to the present embodiment is composed of a MOS transistor and a resistor, a circuit such as the timer circuit 100 which should be prevented from malfunctioning when the power is turned on is a MOS transistor process. When formed, it is advantageous because it does not complicate the process.

In the above description, a timer circuit has been described as an example of a circuit controlled by a malfunction prevention circuit when the power supply voltage rises when the power is turned on. However, the present invention is not limited to the timer circuit. It goes without saying that it can be applied.

The above-described malfunction prevention circuit at the time of rise of the power supply voltage sets the low level when the power supply voltage is lower than a predetermined value determined from the threshold voltage of the malfunction prevention circuit at the time of rise of the power supply voltage. However, the same effect can be obtained.

Further, the input / output control terminal may be connected not only to the output terminal of the target circuit but also to an input terminal or an input / output terminal. In this case, if a signal input to the input terminal has a delay or a noise causes a malfunction of the target circuit, a malfunction prevention circuit at power supply voltage rising according to the present invention is used to connect the input / output control terminal. By connecting to the terminal or the input / output terminal, until the power supply voltage reaches the predetermined value determined from the threshold voltage,
Input terminals or input / output terminals are clamped to high level or low level, and when the power supply voltage exceeds a predetermined value and the target circuit can operate normally, the signal of the original input terminal or input / output terminal is accepted. Can be.

[0051]

As described above, the malfunction preventing circuit according to the present invention when the power supply voltage rises prevents the input terminal or output terminal of the target circuit from inverting or becoming unstable when the power supply voltage rises. Along with
When the power supply voltage becomes higher than a predetermined value determined from the threshold voltage, the power supply voltage is electrically disconnected from the target circuit, so that the target circuit is not affected at all.

Also, instead of adding an external circuit to a circuit that is liable to malfunction at power-on and setting a reset time, parameters of circuit elements formed on the same semiconductor substrate as the circuit that malfunctions are added. Of which
Since the threshold voltage of the malfunction prevention circuit at the time of power supply voltage rise is determined using parameters with small variations, the variation of the threshold voltage is small, and the same semiconductor as the circuit to prevent malfunction at power-on By forming a malfunction prevention circuit at the time of rising of the power supply voltage on the substrate, there is an advantage that the number of external terminals of the package of the semiconductor integrated circuit does not need to be increased. Furthermore, since the rate of increase of the power supply voltage from the GND potential is the same for the circuit that should prevent malfunction and the malfunction prevention circuit when the power supply voltage rises, malfunction can be prevented stably when the power is turned on.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a malfunction prevention circuit when a power supply voltage rises according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the malfunction prevention circuit at the time of rising of the power supply voltage of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the malfunction prevention circuit at the time of rising of the power supply voltage of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of a malfunction prevention circuit at the time of rising of a power supply voltage according to the present invention;

FIG. 5 is a block diagram and a peripheral circuit diagram showing an example of a conventional timer circuit.

FIG. 6 is an equivalent circuit diagram of a conventional timer circuit.

FIG. 7 is a signal waveform diagram for explaining an operation of a conventional timer circuit.

FIG. 8 is a circuit diagram showing a conventional timer circuit and a conventional malfunction prevention circuit when a power supply voltage rises.

[Explanation of symbols]

Reference Signs List 1 GND terminal 2 Trigger input terminal 3 Output terminal 4 Reset terminal 5 Control terminal 6 Input terminal 7 Discharge terminal 8 Power supply terminal 11, 14 Comparator 12 Flip-flop 13 Output circuit 15, 16 Schmitt trigger circuit 100 Timer circuit 110, 120, 130, 140 Timer circuit with malfunction prevention circuit when power supply voltage rises 200, 210220, 230, 240 Malfunction prevention circuit when power supply voltage rises 210A, 240A Input / output terminal control circuit 210B, 220B, 230B, 240B Threshold voltage generation circuit 210C 240C I / O control terminal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (7)

(57) [Claims] 1. A and the threshold voltage generating circuit for outputting a threshold voltage connected to the power supply, control receiving said threshold voltage
In malfunction prevention circuit when the power voltage rising comprising input and output terminals a control circuit for outputting a control voltage to the output terminal of the circuit for performing control, the power supply voltage is determine by referring to the threshold voltage If less than the predetermined value, the control voltage is low or high level, if the power supply voltage is higher than the previous Kisho value, the power supply voltage, characterized in that the high impedance entering-output pin Malfunction prevention circuit at startup. 2. An input / output terminal control circuit comprising: a first transistor having a base pulled up or down and a collector connected to the input / output control terminal; and a collector connected to the base of the first transistor having a collector connected to the base of the first transistor. 2. The malfunction preventing circuit according to claim 1, wherein the circuit comprises a second transistor to which the threshold voltage is applied. 3. The threshold voltage generating circuit includes a diode circuit in which first to Nth (N is an integer) diodes connected in series and a resistor connected in series to the diode circuit. 3. The malfunction preventing circuit according to claim 1, wherein the threshold voltage is set using a voltage generated by flowing a current through the resistor. 4. The threshold voltage generating circuit includes a transistor, a first resistor connected between a base and an emitter of the transistor, and a second resistor connected between a base and a collector of the transistor. 3. The malfunction preventing circuit according to claim 1, wherein the power supply voltage rises. 5. The circuit according to claim 1, wherein the threshold voltage generating circuit divides the power supply voltage by resistance, and outputs the divided voltage to the input / output terminal control circuit.
The malfunction prevention circuit when the power supply voltage rises as described. 6. The input / output terminal control circuit includes: a first MOS transistor having a gate pulled up or down and a drain connected to the input / output control terminal; and a gate having a drain connected to the gate of the first transistor. 2. The malfunction preventing circuit according to claim 1, further comprising a second MOS transistor to which said threshold voltage is applied. 7. A threshold voltage generating circuit comprising: a MOS transistor having a gate and a drain connected, a first resistor connected between a drain of the MOS transistor and a power supply terminal, and a source connected to a source and a ground terminal of the MOS transistor. And a second resistor connected to the second resistor.
Or a malfunction prevention circuit at the time of power supply voltage rise according to 6.