JPS59228172A - Clock signal evaluation apparatus - Google Patents

Abstract

PURPOSE:To enable simple measurement of the duty ratio and the jitter value by comparing a signal to be measured with the output of a PLL circuit to which a signal by dividing a clock signal to be measured is inputted serving as a reference signal. CONSTITUTION:A clock signal to be measured from an input terminal 11 is inputted into a flip flop circuit 13 through a buffer 12 and a signal to be measured divided into two inputted into a phase comparator 14. On the other hand, the output from a voltage controlled crystal oscillator 15 is divided with a divider 16 to give the same frequency as that of the input signal from an input terminal and further, divided into two with a flip flop circuit 17 to be inputted into a phase comparator 14, results of the comparison are fed back to the oscillator 15. Then, inputting signals into phase comparators 14 are applied to XOR gates 18 respectively integrated with an integration circuit 19 and a jitter value indicated on a meter 20. In addition, outputs of the buffer 12 and the divider 16 are integrated with an integration circuit 22 through an XOR gate 21 and a duty ratio is indicated on a meter 23.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock signal evaluation device in a digital control system.

Conventionally, in order to measure the data-1-to-tee ratio, jitter value, etc. of a clock (No. 6), a method has been adopted in which a waveform as shown in FIG. 1 is directly displayed on an oscilloscope and observed.

In this case, in measuring the duty ratio, the ratio of the lengths of T and T'd in waveform 1 must be determined as a percentage.

When measuring the jitter value, process the oscilloscope screen to display a waveform like the one shown in Figure 2, and measure T and Tj.
The ratio of the lengths must be determined as a percentage.

That is, duty ratio - (-r d ÷ - ") x 100 (%
) Jitter value = (Tj ÷T) balun t-1f
However, there were disadvantages such as the presence of i, and the time required for measurement.

The present invention has been made based on the above-mentioned circumstances, and provides a clock signal evaluation device that can directly read the AY ratio and/or the jitter value by inputting the clock signal to be measured. It is something.

For this purpose, the present invention creates a reference signal using a P L-1 circuit, compares this signal with the signal under test, and displays the measured value based on the comparison result. The present invention is characterized in that it is configured to measure the DE/V ratio of the clock signal, m, =, and the jitter value.

Hereinafter, one embodiment of the present invention will be specifically described with reference to the drawings. In the figure, reference numeral 11 is an input terminal for a clock signal to be measured, and an input signal from the input terminal 11 enters a buffer 12, and then is transmitted to a flip-flop circuit 13 and an XOR gate 21. The flip-flop circuit 13 divides the frequency of the clock signal to be measured by two and sends it to the phase comparator 14 as a reference signal τλ.

On the other hand, the signal output from the voltage controlled crystal oscillator M (VCXO) 15 is divided by the frequency divider 16 so that it has the same frequency as the input from the input terminal (i7 and IFiJ), and is further divided by the flip-flop circuit 17. The frequency is divided by 2 and sent to the phase comparator 1.
4 is input. In other words, the phase comparator 14. VC
XO15, jfFIH16, 7 lip 7o 7' circuit 1
7 constitutes a so-called P L 1 circuit. The comparison result is fed back to the VCXO 15 to automatically adjust the oscillation frequency. Further, the input signal to each phase comparator 14 is given to an XOR gate 18,
The signal is integrated by an integrating circuit 19 and sent to a meter 20 to display the jitter value.

In addition, the signal from the barafun 12 and the signal from the frequency divider 16 are integrated by the '2 integration circuit 22 via the XOR gate 21, and sent to the meter 23 (7 = 7 - to display the day ratio). Ru.

Note that in the buffer 12, waveform shaping is performed i:J.

In this way, the signals whose phases have been made equal ( ) by the PLI circuit are compared with the time difference between the targets of each bow using the XOR gate, and the signals are displayed on the meter as an integral value via the integrating circuit (respectively). Unlike direct reading by humans from a scope, there is no variation in the measured values, and the immediate results are given electrically, reducing the measurement time.

Note that in the example described above, a meter of 20.23 was used,
An AD converter may be provided here.

As described in detail above, the present invention uses a signal obtained by frequency-dividing the clock signal under test as a TI-single signal of the P L-circuit, and generates a stable signal with a phase shifted by 1g by the P L-1 circuit. It has the excellent effect of integrating the frequency of the signal under test divided by 2 or/and the time difference between the signals under test, and using this integrated value to easily measure and display jitter values, duty ratios, etc. You can get it.

[Brief explanation of drawings]

FIG. 1 is a graph showing the concept of counting duty ratios on an oscilloscope to explain an embodiment of the present invention, FIG. 2 is a graph showing the concept of counting jitter values, and FIG. 3 is an embodiment of the present invention. This is a 10-step diagram. 11...Input terminal, 12...Buffer, 13...
Flip-flop circuit, 14... Phase comparator, 15.
...VCXo, 1G... Frequency divider, 11... Noritsu flop circuit, 18... XOR gate, 19... Integrating circuit, 20... Meter, 21... XOR gate,
22... Integrating circuit, 23... Meter. Patent applicant: Pioneer Co., Ltd. Agent: Patent attorney: Makoto Kobashi Ukiyo Patent attorney: Susumu Murai

Claims (1)

[Claims] By creating a reference fa@ in a PLI circuit, comparing it with the signal under test, and displaying the measured value based on the comparison result, the duty ratio of a clock signal of a specific frequency or /
A clock signal evaluation device characterized in that it is configured to measure d5 and jitter.