KR940005057Y1 - Master clock circuit - Google Patents

Abstract

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Description

Master clock generation circuit

1 is a block diagram of the present invention.

2 is a detailed circuit diagram of a master clock signal generator in FIG.

3 (a) to 3 (i) is a waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

10: main synchronous signal detection unit 20: frequency division circuit unit

30: phase comparison reference clock signal generation unit 40: phase comparison unit

20A, 30A, 30B: counter FF1-FF3: flip flop

100: system controller 200: master clock signal generator

300: D / A converter 400: V. CIO

ND1-ND17: NANDGATE XNOR: Exclusive Noah Gate

OR1, OR2: Oagate I1-I11: Inverter

B1: buffer

The present invention relates to a circuit for generating a master clock signal. Especially, when data is input from a digital audio device to a digital interface, the phase is compared based on a synchronization signal included in the data. It relates to a master clock generation circuit.

Since 48KHZ, 44.1KHZ, and 32KHZ are used for sampling frequencies used in digital audio equipment, the period of data to be transmitted is changed based on this sampling frequency at the digital interface.

Therefore, a source (oscillator or crystal) is required to generate this sampling frequency when receiving digital data, and the receiving side must select a source suitable for the sampling frequency by determining the period of the reception data.

However, in the conventional digital audio device, there is a defect in that an error of data reception data is frequently generated because the master clock signal corresponding to the sampling frequency cannot be generated correctly.

In order to solve such a conventional defect, the present invention uses a variation of the oscillation frequency according to the voltage applied in a general VIO to continuously check the synchronization signal among the received data, and based on the result It generates a voltage applied to and provides the oscillation frequency of the VIO signal by the applied voltage to the master clock of the receiver to accurately determine the information of the received data, which will be described in detail with reference to the accompanying drawings. .

FIG. 1 is a block diagram showing a part to which the master clock generation circuit of the present invention is applied. As shown therein, the system controller 100 for outputting sampling frequency selection signals FS0 and FS1 and receiving A logic combination of the data RX and the input clock signal CKIN detects a synchronization signal of the received data, and is selected by the sampling frequency selection signals FS0 and FS1 and inputted sampling frequencies (48.1KHZ, 44.1KHZ, 32KHZ) and a system clock signal SYSCK to generate a phase comparison reference clock signal, and then generate a test signal for synchronizing the main synchronization signal with the phase comparison reference clock signal, and generate a test signal and a phase comparison reference clock signal. The D / A converter converts the master clock signal 200 for adjusting the duty ratio of the output signal PD0 and the digital signal PD0 output from the master clock signal generator 200 into an analog signal. 300), and the D / A conversion Was composed of a clock signal (CLOCK OUT), said V O 400 is for outputting in accordance with 300, the frequency control voltage (V _fs) which is output from.

FIG. 2 is a detailed circuit diagram of the master clock signal generator of FIG. 1, as shown in FIG. 1, in which the register 10A, the buffer B1 and the inverter I1, the NAND gates ND1-ND5, and the oragate OR1 and OR2 are shown in FIG. And a main synchronous signal detection unit 10 for logically combining the input clock signal CKIN received from the reception data RX and VSI 400 to detect the main synchronization signal MAINSYNC of the reception data. And an inverter I2 and a counter 20A configured to reset the detected main synchronization signal MAINSYNC by the main synchronization signal MAINSYNC to synchronize the detected main synchronization signal MAINSYNC with a phase comparison reference clock signal PCK. A division circuit unit 200 which counts the input clock signal CKIN returned from the CIO 400 and generates a test signal TEST according thereto, the counters 30A, 30B, flip-flop FF1, (FF2), (FF3), inverters (I3-I9), NAND gates (ND6-ND8), and exclusive Noah gates (XNOR1). A phase comparison reference clock signal generation unit 30 for receiving a sampling frequency selected by the stem controller and generating a phase comparison reference clock signal PCK according to the system clock signal SYSCK, the NAND gates ND9-NB17, Comprising a MOS (PM1), NMOS (NM1), the inverter (I11) and the phase comparison output from the test signal (TEST) detected by the frequency divider circuit 20 and the phase comparison reference clock signal generator 30 Comprising a phase comparison unit 40 for comparing the reference clock signal PCK and adjusting the duty ratio of the output signal PD0 according to the result, see FIG. 3 attached to the operation and effect of the present invention configured as described above. When described in detail as follows.

First, the process of detecting the main synchronization signal MAINSYNC by logically combining the reception data RX and the input clock signal CKIN will be described. The register 10A is an input clock signal fed back from the VSI 400. The received data RX as shown in FIG. 3 (a) is received by CKIN and converted into parallel data, and the converted parallel data is buffered and inverted through the buffer B1 and inverter I1, respectively. Thereafter, the main synchronization signal MAINSYNC as shown in FIG. 3 (d) is detected by being logically combined through the NAND gates ND1-ND5 and the OR gates OR1 and OR2.

On the other hand, the counter 20A resets the main synchronous signal MAINSYNC output from the main synchronous signal detection unit 18 by the reset signal RE _{1 while} being inverted through the inverter I2 and inputted to the clock signal. Count CKIN and output the test signal TEST as shown in FIG. 3 (e) to the output terminal Q5 thereof. The test signal TEST compares the detected main synchronization signal MAINSYNC with a phase comparison reference. It is used to synchronize with the phase comparison reference clock signal PCK output from the clock signal generator 30.

On the other hand, the counter 30A of the phase comparison reference clock signal generation unit 30 supplies the sampling frequency selected by the sampling frequency selection signals FS0 and FS1 of the second bit through the inverters I3 and I4. In response, the system clock signal SYSCK is supplied as the clock signal CK through the inverter I6 and counted to output the signal for each sub-synchronous signal to its output terminal Q5 as shown in FIG. 3 (c).

Here, the sampling frequency of 48KHZ is input to the counter 30A when the sampling frequency selection signals FS0 and FS1 are 0 and 0, and the sampling frequency of 44.1KHZ is input when the sampling frequency selection signals FS0 and FS1 are 1 and 0. When the sampling frequency selection signals FS0 and FS1 are 0 and 1, a sampling frequency of 32 KHZ is input.

The flip-flop FF1 receives the system clock signal SYSCK as a clock signal, receives the input data RX and the input signal RST, and outputs data according to the input data RX. And an Exclusive Noah operation supplied to the Exclusive Noah Gate (XNOR1), and the operation signal is NAND-combined with the input signal RST at the NAND Gate ND6, and the resultant value is the reset signal of the counter 30A. Since a signal other than the main synchronous signal MAINSYNC or the sub synchronous signal is input, the counter 30A continues to be reset and a low potential is output therefrom.

On the other hand, the counter 30B is reset by the output signal of the NAND gate ND _{7 and} receives the output signal of the exclusive NOR gate XNOR1 as the clock signal CK through the inverter I7. A signal as shown in FIG. 3 (b) is output to the output terminal Q3.

The output signal of the exclusive NOR gate XNOR and the inverted input signal RST are NAND-combined at the NAND gate ND6 and supplied to the reset signal RE3 of the flip-flop FF2. The flip-flop FF2 receives the output signal Q5 of the counter 30A as the clock signal CK, and supplies the corresponding output signal to the clock signal CK of the flip-flop FF3.

In addition, the input signal RST is inverted through the inverter I10 and supplied to one input of the NAND gate ND8, and the output signal of the counter 30A is supplied to the NAND gate ND8 through the inverter I8. The NAND-combined signal supplied to the other input of the NAND gate ND8 is supplied to the reset signal RE5 of the flip-flop FF3, and thus the flip-flop FF3 has the same signal as the third (f). The signal is a phase comparison reference clock signal PCK.

The input signal RST supplied through the inverter I10, the phase comparison reference clock signal PCK supplied through the inverter I9, and the test signal TEST are inputted by the phase comparison unit 40. A signal such as a third (g) diagram supplied as a signal and logically combined through the NAND gates ND9 to ND17 and output from the NAND gate ND16 is supplied to the gate of the PMOS PM1, and the inverter I11. Is outputted to the gate to the NMOS NM1, whereby the phase comparator 40 outputs a signal PD0 such as the adjusted third frequency (i). do.

That is, the phase comparison unit 40 compares the test signal TEST detected by the division circuit unit 20 with the phase comparison reference clock signal PCK output from the phase comparison reference clock signal generation unit 30. If the test signal TEST is higher than the phase comparison reference clock signal PCK signal, the duty ratio is decreased to output a frequency PD0 that is lower than the output frequency CLOCK OUT of the VSI 400 and vice versa. If (TEST) is a low potential, the high potential duty ratio is increased to output a frequency higher than the frequency (CLOCK OUT) output from the VCIO 400.

In addition, the frequency control voltage V _fc , from which the signal PD0 output from the phase comparator 40 is converted into an analog signal through the D / A converter 300, is output, and the frequency control voltage V _fc is output. The clock signal (CLOCK OUT) is output from the VCIO 400, which is fed back to the master clock signal generator 200 and the above operation is performed continuously, so that the master clock signal most suitable for the received data is received. Will be created.

As described in detail above, the master clock included in the data using the comparison output is compared with a phase comparison between the signal generated based on the main synchronization signal included in the data using VSEO and the sub-synchronous signal. The ability to generate a signal has the effect of receiving data more accurately.

Claims (1)

A main synchronous signal detection unit 10 for logically combining the input clock signal CKIN received from the reception data RX and VSI 400 to detect the main synchronization signal MAINSYNC of the reception data; In order to synchronize the main synchronization signal MAINSYNC with the phase comparison reference clock signal PCK, the input clock signal CKIN is returned from the VSI 400 while being reset by the main synchronization signal MAINSYNC. Phase comparison circuit 20 that counts and generates a test signal TEST according thereto, and a phase comparison reference clock signal PCK generated according to the system clock signal SYSCK by receiving a sampling frequency selected by the system controller. The reference clock signal generator 30 compares the test signal TEST detected by the frequency divider 20 with the phase comparison reference clock signal PCK output from the phase comparison reference clock signal generator 30. Output according to the result No. master clock generation circuit, characterized in that configured in the phase comparator 40 to adjust the duty ratio of the (PD0).