JPH05119168A - Apparatus for measuring synchronous jitter amount - Google Patents

Abstract

PURPOSE:To highly accurately measure a synchronous jitter amount of a synchronous clock signal generator which generates a clock signal having the same frequency as a reference clock signal synchronizing with a trigger signal. CONSTITUTION:A synchronous jitter measuring apparatus comprises a second clock signal (fo-DELTAf) of frequency close to a first clock signal (fo) and an APC (autophase control) circuit, wherein a synchronization trigger signal 10 having a trigger edge whose phase has shifted slightly with respect to a first clock signal 12 per a first specific clock frequency is generated. Thus a synchronous clock signal 11 is generated from a synchronous clock generator 26, it is input to the APC circuit 18 to generate a phase jump pulse for detecting phase jump of the synchronous clock signal from a phase comparator 7, and this time interval is counted by time required for the fine phase (synchronous trigger signal frequency) to have a synchronous jitter amount measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for measuring the amount of synchronous jitter of a synchronous clock signal generated from a synchronous clock generator which generates a clock signal synchronized with a synchronous trigger signal.

[0002]

2. Description of the Related Art Image memory, laser beam printer (L
The above-mentioned synchronous clock generator is required for BP) and the like. In the case of an image memory, a sampling clock signal synchronized with the horizontal sync signal is required.
This is because in the case of P, image data is printed at an accurate position on the paper surface, and therefore a video clock signal synchronized with a beam detect (BD) signal that defines the horizontal writing timing is required. The amount of jitter with respect to the synchronization trigger signal included in these synchronization clock signals is "pixel shift"
It must be the cause and must be suppressed. Generally, in an image memory and LBP, this jitter amount is 1 pixel (clock cycle).
⅛ or less. This amount of jitter is called the amount of synchronous jitter, and is shown as Tj in FIG. In order to generate a synchronous clock signal which secures a desired amount of synchronous jitter with pure digital technology, a clock signal having a frequency of 8 times or more is required. On the other hand, the image memory and LBP are required to have higher definition, and it is necessary to further increase the frequency of the synchronous clock signal used for them. However, the generation of such a high-frequency clock signal causes many problems in that unnecessary radiation is generated, it is difficult to form an IC, and it is indispensable to use an expensive crystal oscillator.

For this reason, there has been proposed a synchronous clock generator which employs a (half-digital) technique for managing the clock period and requires only a clock signal of a desired frequency. 3 is a block diagram of the synchronous clock generator, and FIG. 4 is a timing chart diagram for explaining its operation.

A triangular wave variable oscillator (VCO) 1, a phase comparator (PD) 2, and a crystal oscillator (XO) 3 constitute a PLL circuit, and an output terminal of the triangular wave variable oscillator (VCO) 1 is shown in FIG. A triangular wave signal having the same precision as that of the crystal oscillator as shown in is output and input to the non-inverting input terminals of the level comparators 4 to 8. The comparison voltages V1 to V5 are input to the inverting input terminals of the comparators 4 to 8, respectively. The outputs D1 to D5 of the level comparators and the rectangular wave output D0 of the triangular wave variable oscillator (VCO) 1 are LOGIC.
It is input to the circuit unit 9. In addition, the synchronization trigger signal 10 is input to the LOGIC circuit unit 9 and the synchronization clock signal 1 is input.
1 is output. One cycle of the triangular wave signal is divided into _ten periods Z _{1 to} Z ₁₀ as shown in FIG. 4C, and each period Z ₁
When latched at the rising edge (or falling edge) of the synchronous trigger signal 10 at ~ Z ₁₀ , the outputs D1 to D5 of each level comparator and the rectangular wave signal D0 have the relationship as shown in the phase data part of FIG. The * mark in FIG. 5 indicates indefinite or neglected. When the input edge phase of the sync trigger signal exists within each period Z _{1 to} Z ₁₀ , the next synchronization is performed by setting and resetting at the data existence timings D0 to D5 shown in the phase data portion and the reset data portion as shown in FIG. The LOGIC circuit section 9 is configured to repeatedly output the synchronous clock signal until the trigger edge. Figure 5 (3)
(13) to (13) show synchronous clock signals when a synchronous trigger edge is present in each period Z _{1 to} Z ₁₀ . The synchronization jitter amount Tj of this synchronization clock generator becomes 1 / 10To (To is a clock cycle) when each part of FIG. 3 is optimized, and a synchronization clock signal that secures a desired synchronization jitter amount with a clock signal of the same frequency as the required clock frequency. 11 can be generated.

Generally, it is essential that the synchronous clock generator is integrated into an IC in order to ensure the characteristics at low cost without adjustment. However, the synchronization jitter amount Tj is caused by variations in the comparison voltages V1 to V5 of the level comparator, variations in symmetry of the triangular wave signal, level, and linearity of slope, variations in the internal delay time of the LOGIC circuit unit 9, and the like.
However, the desired jitter amount (<1 / 8To) cannot be guaranteed in terms of IC design. For this reason, there is a demand for a synchronization jitter amount measuring device that individually measures the synchronization jitter amount Tj and accurately and quickly selects pass / fail.

[0006]

By the way, LBP,
Image memory requires high definition, so 20 MH
More synchronous clock signals need to cross z. For example, now the synchronous clock frequency is 20 MHz (To = 50
ns), it is necessary to set the synchronization jitter amount Tj <less than 6.25 ns. In the synchronous clock generator of FIG. 3, it is necessary to determine that the synchronous jitter amount Tj is 5.0 to 6.25 ns as a non-defective product. There is currently no apparatus for accurately measuring such a minute time, and the only way is to make a visual judgment using an oscilloscope or the like.

However, it is not possible to visually check not only the IC time by spending a great deal of time, but also it is impossible to accurately measure and judge the synchronization jitter amount Tj as shown in FIG.

[0008]

According to the present invention, a synchronous jitter measuring apparatus is provided with a first clock signal (fo).
And a second clock signal (fo-Δ with a frequency close to
f) and APC (autophase contro)
l) A circuit is provided. ◇ This synchronous jitter measuring apparatus creates a synchronous trigger signal having a trigger edge that is phase-shifted by a minute phase Δθ1 with respect to the first clock signal every certain number of first clock cycles. Generates a synchronous clock signal. ◇ By inputting this into the APC circuit in this device, the phase comparator in the APC circuit generates a phase jump pulse for detecting the phase jump of the synchronous clock signal, and this time interval is the time required for the minute phase unit Δθ2 ( The amount of synchronization jitter is measured by counting with a synchronization trigger signal period).

[0009]

1 is a block diagram showing a system for measuring a synchronous jitter amount Tj of a synchronous clock generator using the synchronous jitter amount measuring apparatus of the present invention. FIG. 6 is a main timing chart diagram thereof. The synchronous clock generator 26 has a structure as shown in FIG. 3, but the crystal oscillator 3 is not used as an oscillator because it is a simple inverting AMP as an IC circuit, and the clock signal is input from the synchronous jitter measuring device 25. There is. Crystal oscillator (fo
XO) 13 outputs the first clock signal 12 and inputs it to the synchronous clock generator 26 as a reference clock signal, and the internal triangular wave signal is phase-synchronized with the first clock signal. The crystal oscillator (fo-Δf) XO) 14 outputs a second clock signal having a frequency relationship of 17999/18000 × fo, for example. At this time, the phase of the second clock signal with respect to the first clock signal exists with a minute phase transition (360/18000 °) such as 0 to 360 ° (all phases) with the first clock period number of 18000. This second clock signal is a pulse generator (P.GEN)
15 is input to output the synchronization trigger signal 10 shown in FIG. 6A and is input to the synchronization clock generator 26. The cycle of the synchronization trigger signal 10 is, for example, 12 cycles of the first clock signal. In this case, the trigger edge of the synchronization trigger signal is 0.24 ° with respect to the triangular wave signal in the synchronization clock generator 26, and a slight phase shift Δθ1. At this time, the synchronous clock signal 11 output from the synchronous clock generator 26 is a variable crystal oscillator (foVXO) 1
6, and an APC circuit 1 including a phase comparator (PD) 17
8 is input. The internal circuit configuration of the phase comparator (PD) 17 is shown in FIG.

In FIG. 7, Q1 & Q15, Q2 & Q
5, Q3 & Q6, Q4 & Q7, Q8 & Q12, Q9 & Q
13, Q10 & Q14, Q11 & Q17, Q16 & Q1
The pairing between the eight transistors is good. Input terminal 2
The output of the variable crystal oscillator (foVO) 16 is input to 7'as a differential pair signal. "P" is the positive polarity,
N ″ indicates a negative polarity. The synchronous clock signal 11 is input to the input terminal 11 ′ after being converted into a differential pair signal. The gate signal 19 shown in FIG. This gate signal 19 stops the APC operation during this intermittent period because the synchronous clock signal 11 is an intermittent clock signal as shown in FIG. In the APC circuit 18, the phase error signal 2 is set so that the phase difference between the output signal of the variable crystal oscillator (foVXO) 16 and the synchronous clock signal 11 becomes 90 °.
A variable crystal oscillator (foVXO) 16 is controlled by 8. This is because, at this time, the average values of the collector currents of Q17 and Q18 are balanced, the variation of the average value of the terminal voltage of the capacitor C1 is stopped, and the DC potential of the phase error signal 28 is stabilized. The other end of C1 is connected to a reference potential V1 near a potential Vo (described later) in consideration of the circuit activation time.

FIG. 6D shows an example of the actual waveform of the phase error signal 28. If the trigger edge phase is within the phase period Z _i shown in FIG. 4B until the (N-1) th (N is a certain integer) synchronous trigger signal, the potential of the phase error signal 28 of the APC circuit 18 becomes Vo. Is working like. When the phase period Z _i changes at the Nth trigger edge, the phase of the synchronous clock signal 11 is delayed by the phase period width in which the N−1th trigger edges exist compared to the clock phase at the Nth time (phase Jump occurs). The Nth synchronization trigger signal 10 causes the phase error signal 2 as shown in FIG. 6 (4).
The potential of 8 starts to rise, and in this example, the potential of the phase error signal 28 returns to Vo by the APC operation again at the (N + 2) th trigger edge. N + x-1th synchronization trigger signal 1
0 exists in the same phase period, and thus the potential of the phase error signal 28 remains at Vo. At the (N + x) th synchronization trigger signal, the trigger edge deviates from the (N + x-1) th phase period, and the phase of the synchronization clock signal is delayed by this phase period width (a phase jump occurs again). Phase period width is an integer x
It can be observed by asking for. At this time, similarly to the previous time, the potential of the phase error signal 28 starts to rise and returns to Vo again after several synchronization trigger signal periods. In the case of the synchronous clock generator 26 of FIG. 3 every 1500 pulses (18000/12) of the synchronous trigger signal 10, the phase jump of the synchronous trigger signal 11 occurs ten times, and the potential fluctuation of the phase error signal 28 indicating this is observed. It The potential rise ΔV of the phase error signal 28 at the time of the phase jump per one synchronization clock cycle can be roughly expressed by the following equation.

ΔV = (2 · To · Io · θj / 360 °) / C1 To: Synchronous clock signal period θj: Phase jump amount or phase period width

The potential rise ΔV is easy to discriminate (digitize) the potential fluctuation of the phase error signal 28 within the period of the synchronization trigger signal.
As possible, setting Io and C1 is advantageous for reducing the measurement error of the synchronization jitter amount Tj. The phase error signal 28 is converted into a phase jump pulse by the waveform shaping circuit 20 as shown by (5) in FIG. The rising edge of this phase jump pulse is the threshold level VTH.
To be determined by. Although the falling edge is delayed from the timing determined by the threshold level VTH, an unnecessary phase jump pulse due to a phase jump return due to a clock component remaining in the phase error signal or a jitter component of the triangular wave PLL circuit in the synchronous clock generator 26 is generated. There is no problem in the system even if it is slightly delayed due to a mono-multivibrator for masking (it is necessary that it falls within the synchronization trigger period). Since the synchronization jitter amount Tj is the maximum value of each phase period width, the phase jump pulse interval is measured, and the trigger edge of the synchronization trigger signal is 0 to 36.
0 ° included period (In this example, the synchronization trigger signal is 15
(00 pulses) The determination may be made with respect to the specified value. Therefore, the phase jump pulse is input to the counting circuit 22, where it is counted by the counting pulse 21 representing the minute phase unit Δθ, and the count value indicates the phase period width at that time. Further, the count result is input to the quality determination circuit 23 and compared with the specified value θo of the synchronization jitter amount Tj to determine the quality of the synchronous clock generator 26. Specified value θo is 1 / 8T
is 45 °, and the minute phase unit Δθ2 is 0.
If it is 24 °, it may be set to about 188.

The synchronous jitter amount measuring device described above has the following effects.

The synchronization jitter amount measurement accuracy ΔTj can be roughly expressed by the following equation.

ΔTj = Δθ1 + Δθ2 + θo · (fo · df) / Δf Δθ1: Phase transition value of trigger edge of synchronization trigger signal Δθ2: Minute phase unit for counting synchronization jitter amount Tj θo: Synchronization jitter Specified value of amount Tj fo: Reference clock frequency (synchronous clock frequency) Δf: Frequency difference between first clock signal and second clock signal df: Frequency difference variation between first clock signal and second clock signal , Δθ1 and Δθ2 are 0.24 °, θo is 45 °, f
o is 20 MHz and Δf (fo / 18000) is 1.11
1kHz, df 1ppm from the specifications of the existing crystal oscillator
Then, the synchronization jitter measurement accuracy ΔTj is about 1.29 ° (180 ps on the time axis), and a sufficient value can be secured.

The synchronization jitter amount Tj discrimination time is 180 at the shortest.
00 clock cycle is required, but clock frequency is 20 MH
If z (To = 50ns), the required time is 900μ
The synchronization jitter amount Tj can be measured within a very short time of about s.

Since the synchronization jitter amount Tj is measured by the phase angle, a high frequency circuit is not required and the apparatus can be simply constructed.

Since the synchronization jitter amount Tj is measured by the phases of a plurality of synchronization clock signals, it is possible to obtain stable and stable measurement results against disturbance.

[0020]

As described above, according to the present invention, it is possible to measure the synchronization jitter amount of the synchronous clock signal generator with high accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronous jitter amount measuring device of the present invention.

FIG. 2 is a waveform diagram showing a synchronization jitter amount.

FIG. 3 is a block diagram of a synchronous clock generator.

FIG. 4 is a main timing chart explaining the operation of FIG.

FIG. 5 is a diagram illustrating each phase data for each phase period for explaining the operation of FIG.

FIG. 6 is a main timing chart explaining the operation of FIG.

FIG. 7 is a circuit diagram of a phase comparator for explaining the operation of FIG.

[Explanation of symbols]

 1 triangular wave variable oscillator 2,17 phase comparator 3,13,14 crystal oscillator 4-8 level comparator 9LOGIC circuit section 15 pulse generator 16 variable crystal oscillator 18 APC circuit 20 waveform shaping circuit 22 counting circuit 23 judgment circuit 25 synchronization jitter amount measurement Circuit 26 Synchronous clock generator

Claims (2)

[Claims] 1. A synchronous jitter signal measuring device for measuring the synchronous jitter amount of the synchronous clock signal with respect to a synchronous clock generator for generating a synchronous clock signal synchronized with a trigger edge of the synchronous trigger signal as a reference. a first clock signal generator for outputting a clock signal having a frequency equal to fo, a second clock signal generator for outputting a clock signal having a frequency different from the first clock frequency by Δf, a variable frequency oscillator and a phase A synchronization jitter amount measuring device comprising a comparator, a phase control circuit which operates with the synchronous clock signal, and a synchronization jitter amount which is measured by using a phase error signal of the phase comparator. 2. An apparatus for measuring the amount of synchronous jitter of a synchronous clock signal generator which generates a clock signal having the same frequency as a reference clock signal in synchronization with a trigger signal, wherein a phase difference with respect to the reference clock signal is small in each cycle. A cyclic signal generating means for generating a cyclic signal that shifts by an amount; and a phase detecting means for detecting a phase of the synchronous clock signal generated when the cyclic signal is applied to the synchronous clock generator as a trigger signal. Characteristic synchronous jitter amount measuring device.