JPS59226944A - 浮動小数点デ−タ加減算方式 - Google Patents

浮動小数点デ−タ加減算方式

Info

Publication number
JPS59226944A
JPS59226944A JP58103152A JP10315283A JPS59226944A JP S59226944 A JPS59226944 A JP S59226944A JP 58103152 A JP58103152 A JP 58103152A JP 10315283 A JP10315283 A JP 10315283A JP S59226944 A JPS59226944 A JP S59226944A
Authority
JP
Japan
Prior art keywords
addition
floating point
subtraction
point data
digit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58103152A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0239809B2 (enrdf_load_stackoverflow
Inventor
Koichi Ueda
上田　孝一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58103152A priority Critical patent/JPS59226944A/ja
Publication of JPS59226944A publication Critical patent/JPS59226944A/ja
Publication of JPH0239809B2 publication Critical patent/JPH0239809B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
JP58103152A 1983-06-09 1983-06-09 浮動小数点デ−タ加減算方式 Granted JPS59226944A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58103152A JPS59226944A (ja) 1983-06-09 1983-06-09 浮動小数点デ−タ加減算方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58103152A JPS59226944A (ja) 1983-06-09 1983-06-09 浮動小数点デ−タ加減算方式

Publications (2)

Publication Number Publication Date
JPS59226944A true JPS59226944A (ja) 1984-12-20
JPH0239809B2 JPH0239809B2 (enrdf_load_stackoverflow) 1990-09-07

Family

ID=14346526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58103152A Granted JPS59226944A (ja) 1983-06-09 1983-06-09 浮動小数点デ−タ加減算方式

Country Status (1)

Country Link
JP (1) JPS59226944A (enrdf_load_stackoverflow)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177538A (ja) * 1985-01-29 1986-08-09 エイ・テイ・アンド・ティ・コーポレーション 最上位の数字の位置の検出
JPS63208938A (ja) * 1987-02-26 1988-08-30 Hitachi Ltd フラグ発生回路
JPS63262723A (ja) * 1987-04-20 1988-10-31 Matsushita Electric Ind Co Ltd 演算処理方法
JPS6486237A (en) * 1987-06-19 1989-03-30 Digital Equipment Corp Apparatus and method for accelerating effective subtraction procedure of floating point by estimation of absolute value of difference in threshold of exponential part
JPH0357019A (ja) * 1989-07-26 1991-03-12 Toshiba Corp 浮動小数点データ加減算回路
JPH0362124A (ja) * 1989-07-28 1991-03-18 Nec Ic Microcomput Syst Ltd 加算回路
JPH04278630A (ja) * 1991-03-06 1992-10-05 Koufu Nippon Denki Kk 浮動小数点加減算器
JPH07225671A (ja) * 1993-12-06 1995-08-22 Internatl Business Mach Corp <Ibm> 結果正規化機構と動作の方法
EP0362580B1 (en) * 1988-10-07 1996-04-24 International Business Machines Corporation Leading 0/1 anticipator (LZA)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147932A (en) * 1975-06-02 1976-12-18 Ibm Sum detection logical circuit
JPS5587243A (en) * 1978-12-25 1980-07-01 Fujitsu Ltd Zero detection system of adder output

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147932A (en) * 1975-06-02 1976-12-18 Ibm Sum detection logical circuit
JPS5587243A (en) * 1978-12-25 1980-07-01 Fujitsu Ltd Zero detection system of adder output

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177538A (ja) * 1985-01-29 1986-08-09 エイ・テイ・アンド・ティ・コーポレーション 最上位の数字の位置の検出
JPS63208938A (ja) * 1987-02-26 1988-08-30 Hitachi Ltd フラグ発生回路
JPS63262723A (ja) * 1987-04-20 1988-10-31 Matsushita Electric Ind Co Ltd 演算処理方法
JPS6486237A (en) * 1987-06-19 1989-03-30 Digital Equipment Corp Apparatus and method for accelerating effective subtraction procedure of floating point by estimation of absolute value of difference in threshold of exponential part
EP0362580B1 (en) * 1988-10-07 1996-04-24 International Business Machines Corporation Leading 0/1 anticipator (LZA)
JPH0357019A (ja) * 1989-07-26 1991-03-12 Toshiba Corp 浮動小数点データ加減算回路
JPH0362124A (ja) * 1989-07-28 1991-03-18 Nec Ic Microcomput Syst Ltd 加算回路
JPH04278630A (ja) * 1991-03-06 1992-10-05 Koufu Nippon Denki Kk 浮動小数点加減算器
JPH07225671A (ja) * 1993-12-06 1995-08-22 Internatl Business Mach Corp <Ibm> 結果正規化機構と動作の方法

Also Published As

Publication number Publication date
JPH0239809B2 (enrdf_load_stackoverflow) 1990-09-07

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