JPS59225568A - Manufacture of thin film transistor matrix array - Google Patents
Manufacture of thin film transistor matrix arrayInfo
- Publication number
- JPS59225568A JPS59225568A JP58099437A JP9943783A JPS59225568A JP S59225568 A JPS59225568 A JP S59225568A JP 58099437 A JP58099437 A JP 58099437A JP 9943783 A JP9943783 A JP 9943783A JP S59225568 A JPS59225568 A JP S59225568A
- Authority
- JP
- Japan
- Prior art keywords
- films
- dirt
- thin film
- film transistor
- transistor matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明はマトリックス型液晶表示装置となる各セルの駆
動に用いられる薄膜トランジスタマトリックスアレイの
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of manufacturing a thin film transistor matrix array used for driving each cell of a matrix type liquid crystal display device.
技術の背景
第1図はガラス基板を用い画素スイッチに薄膜トランジ
スタを用いた液晶表示ツクネルを説明するだめの図であ
シ、aは平面図、bは断面図を示す。Background of the Technology FIG. 1 is a diagram for explaining a liquid crystal display tunnel using a glass substrate and a thin film transistor as a pixel switch, in which a shows a plan view and b shows a cross-sectional view.
同図において、1はガラス基板、2はダートパスライン
、lj:)’レインパスライン、4はケ+ F ハス
ラインに接続したダート電極、5はソース電極、6はソ
ース電極に接続した透明導電膜よりなる表示部、7は透
明導電膜よりなる対向電極、8は液晶をそれぞれ示して
いる。In the figure, 1 is a glass substrate, 2 is a dirt pass line, lj:)' rain pass line, 4 is a dirt electrode connected to the K+F lotus line, 5 is a source electrode, and 6 is a transparent conductive film connected to the source electrode. 7 is a counter electrode made of a transparent conductive film, and 8 is a liquid crystal.
第1図において、ダートパスライン2とドレインパスラ
イン3とはマトリックスの縦線、横線を構成しており、
表示部6は大きな面積を持つ矩形でb図に示すように対
向電極7と共に液晶ノ9ネルの1対の電極を樽成し、こ
れらの電極の間に液晶8が封入される。そしてドレイン
及びダート電極を選択して電圧を印加すると、それら選
択ドレイン、ダート電極と共に薄膜トランジスタを構成
するソース電極5に電圧が加わQ表示部6と対向電極7
間の液晶の配列が変り、その部分が透過性になって白く
見える。In FIG. 1, the dirt path line 2 and the drain path line 3 constitute the vertical lines and horizontal lines of the matrix.
The display section 6 is rectangular with a large area, and as shown in Figure b, forms a pair of electrodes of a liquid crystal channel together with a counter electrode 7, and a liquid crystal 8 is sealed between these electrodes. Then, when the drain and dirt electrodes are selected and a voltage is applied, the voltage is applied to the source electrode 5, which together with the selected drain and dirt electrodes constitute a thin film transistor, to the Q display section 6 and the counter electrode 7.
The alignment of the liquid crystal in between changes, and that part becomes transparent and appears white.
従来技術と問題点
このような液晶表示ノやネルに用いられる′1tri膜
トランジスタマトリックスアレイの不良原因として、次
の4つの故障モードがある。Prior Art and Problems There are the following four failure modes as causes of failure in the 1tri film transistor matrix array used in such liquid crystal displays and panels.
その第1はダートパスライン2の断線、第2はドレイン
パスライン3の断線、第3はケ゛−ト電極4とドレイン
パスライン3間のショート、第4はダート電極4とソー
ス電極5間のショートである。The first is a break in the dirt pass line 2, the second is a break in the drain pass line 3, the third is a short between the gate electrode 4 and the drain pass line 3, and the fourth is a short between the dirt electrode 4 and source electrode 5. It is short.
このうち第1、第2の原因はラインでの画素ぬけ、第4
の原因は1画素の表示不良、第3の原因はパネル全体の
不良といつた故障モードとなって現われる。これら第1
、第2の原因はパターニングの際に生ずるものであシ、
技術の修得によって克服できる。Among these, the first and second causes are missing pixels on the line, and the fourth
The cause of this is a display failure of one pixel, and the third cause is a failure mode of the entire panel. These first
, the second cause occurs during patterning,
It can be overcome by acquiring skills.
これに対して第3、第4の原因はピンホールによるショ
ートであり、絶縁膜、半導体膜の形成条件等で少なくす
ることができるが特に第3の場合は、僅か数個所のシ目
−トによpノ9ネル全体が不良となってしまい、このよ
うなアレイの製造歩留り低下の主要原因となっている。On the other hand, the third and fourth causes are short circuits due to pinholes, which can be reduced by changing the formation conditions of the insulating film and semiconductor film, etc., but especially in the third case, short circuits caused by pinholes can occur. This results in the entire pno-nine becoming defective, which is a major cause of reduced manufacturing yields for such arrays.
また現在このような故障の救済方法はない。Furthermore, there is currently no remedy for such failures.
発明の目的
本発明は上記従来の問題点に鑑み、薄膜トランジスタマ
トリックスアレイにおいて、その絶縁膜、半導体膜のピ
ンホールによるショート不良を救済し、製造歩留りを向
上することができる薄膜トランジスタマトリックスアレ
イの製造方法を折供す、ることを目的とするものである
。Purpose of the Invention In view of the above conventional problems, the present invention provides a method for manufacturing a thin film transistor matrix array, which can improve the manufacturing yield by relieving short-circuit defects caused by pinholes in the insulating film and semiconductor film in the thin film transistor matrix array. It is intended to be offered as an offering.
発明の構成
そしてこの目的は本発明によれば、ダート電極、ダート
絶縁膜、半導体膜およびソース、ドレイン電極よりなる
薄膜トランジスタマトリックスアレイにおいて、半導体
膜及びダート絶縁膜に生ずるピンホール直下のダート電
極部を、デートパスラインを陽極とする電解エツチング
により除去することを特徴とする薄膜トランジスタマト
リックスアレイの製造方法を提供することによって達成
される。According to the present invention, in a thin film transistor matrix array consisting of a dirt electrode, a dirt insulating film, a semiconductor film, and source and drain electrodes, the dirt electrode portion directly under the pinhole that occurs in the semiconductor film and the dirt insulating film is removed. This is achieved by providing a method for manufacturing a thin film transistor matrix array, characterized in that the date pass line is removed by electrolytic etching using the date pass line as an anode.
発明の実施例 以下、本発明実施例を図面によって詳述する。Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第2図は本発明による薄膜トランジスタマトリックスア
レイの製造方法を説明するための図である。同図におい
て、10はNiCr膜のダート電極、11はn″’a−
81: H/)lよりなるドレイン電極、12はS i
02又はS i 、N4を用いたダート絶縁膜と半導体
膜のa−8i膜の2層膜、13は12の上のみn+a−
8i : H/ Atのソース電極に接続された透明導
電膜からなる表示部電極、14はダート絶縁膜の5IO
2を用いたダート、ドレイン間の絶縁膜を示す。なおダ
ート電極膜10の上部は基板端部を除いてすべてSiO
2絶縁膜でおおわれている。FIG. 2 is a diagram for explaining a method of manufacturing a thin film transistor matrix array according to the present invention. In the figure, 10 is a dirt electrode of NiCr film, 11 is n''a-
81: Drain electrode consisting of H/)l, 12 is S i
02 or S i , two-layer film of dirt insulating film using N4 and a-8i film of semiconductor film, 13 is n+a- only on top of 12
8i: Display part electrode made of a transparent conductive film connected to the source electrode of H/At, 14 is a 5IO of dart insulating film.
This figure shows an insulating film between the dart and the drain using 2. The upper part of the dirt electrode film 10 is entirely made of SiO except for the edge of the substrate.
2 covered with an insulating film.
本発明方法はこのような薄膜トランジスタマトリックス
アレイの製造工程において、ケ◆−ト電極10と、ダー
ト絶縁膜及び半導体膜の2層膜12を形成した後、ダー
ト電極10を−まとめの陽極とし、H2O、3Qml:
H,PO4(比重1.71)70m/のエツチング液
中に浸績し、陰極にNiを用いて2〜IOVの直流′f
rlo〜60秒印加する。この後純水によシ十分にリン
スを行ないエツチング液を除去し、さらに基板端部で−
まとめにしておいたダート電極10をレジストを用いた
エツチングによって一つづつに分離する。In the manufacturing process of such a thin film transistor matrix array, the method of the present invention involves forming a gate electrode 10 and a two-layer film 12 of a dirt insulating film and a semiconductor film, and then using the dirt electrode 10 as a collective anode and applying H2O. , 3Qml:
H, PO4 (specific gravity 1.71) immersed in 70 m/etching solution, using Ni as the cathode, and applying a direct current of 2 to IOV'f.
Apply rlo~60 seconds. After that, thoroughly rinse with pure water to remove the etching solution, and then remove the etching solution from the edge of the substrate.
The dirt electrodes 10 that have been put together are separated one by one by etching using a resist.
このように処理すると、ダート絶縁膜及び半導体膜にピ
ンホールがある部分のNiCrが除去される。By processing in this manner, NiCr is removed from portions of the dart insulating film and the semiconductor film where there are pinholes.
従ってこの後に形成されるドレイン及びソース電極を設
けても、たとえピンホールがあってもダート電極10は
その部分が無いためショートは無くなる。従って製造歩
留りは大幅に向上する。Therefore, even if the drain and source electrodes formed later are provided, even if there is a pinhole, there will be no short circuit because the dirt electrode 10 does not have that part. Therefore, manufacturing yield is greatly improved.
またこのピンホールの大きさは薄膜トランジスタの大き
さく例えば20μmX200μm)に対して0.5μm
φ程度と十分に小さいので薄膜トランジスタの特性に与
える影響は殆んど無い。Also, the size of this pinhole is 0.5 μm compared to the size of a thin film transistor (for example, 20 μm x 200 μm).
Since it is sufficiently small, about φ, it has almost no effect on the characteristics of the thin film transistor.
発明の効果
以上詳細に説明したように、本発明の薄膜トランジスタ
マトリックスアレイの製造方法は、ダート絶縁膜及び半
導体膜に生ずるピンホール直下のダート電極を陽極電解
エツチングにより除去することにより、ショートの発生
を防止し、製造歩留りを向上せしめ得るといった効果大
なるものである。Effects of the Invention As explained in detail above, the method for manufacturing a thin film transistor matrix array of the present invention prevents the occurrence of short circuits by removing the dirt electrodes directly under the pinholes that occur in the dirt insulating film and semiconductor film by anodic electrolytic etching. This has great effects in that it can prevent this and improve manufacturing yield.
第1図は従来の薄膜トランジスタマトリックスアレイを
用いた液晶表示ツヤネルを説明するための 4S図、
第2図は本発明による薄膜トランジスタマトリックスプ
レイの製造方法を説明するための図である。
図面において、10はゲート電極、11はドレイン電極
、12はケ゛−1・絶縁膜と半導体膜、13は表示部電
極、14はダート、ドレイン間の絶縁膜をそれぞれ示す
。
特許出願人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士 西 舘 和 之
弁理士 内 1)幸 男
弁理士 山 口 昭 之
(C1)
(b)Figure 1 is a 4S diagram for explaining a liquid crystal display panel using a conventional thin film transistor matrix array.
FIG. 2 is a diagram for explaining a method of manufacturing a thin film transistor matrix play according to the present invention. In the drawings, 10 is a gate electrode, 11 is a drain electrode, 12 is a case-1 insulating film and a semiconductor film, 13 is a display electrode, and 14 is an insulating film between the dirt and the drain. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate (1) Yukio Patent attorney Akira Yamaguchi (C1) (b)
Claims (1)
、ドレイン電極よシなる薄膜トランジスタマトリックス
アレイにおいて、半導体膜及びダート絶縁膜に生ずるピ
ンホール直下のダート電極部を、ケ゛−トバスラインを
陽極とする電解エツチングによシ除去することを特徴と
する薄膜トランジスタマトリックスアレイの製造方法。1. In a thin film transistor matrix array consisting of a dirt electrode, a dirt insulating film, a semiconductor film, and source and drain electrodes, electrolytic etching is performed on the dirt electrode part directly under the pinhole that occurs in the semiconductor film and dirt insulating film, using the cathode bus line as an anode. 1. A method for manufacturing a thin film transistor matrix array, the method comprising the step of removing the thin film transistor matrix.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58099437A JPS59225568A (en) | 1983-06-06 | 1983-06-06 | Manufacture of thin film transistor matrix array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58099437A JPS59225568A (en) | 1983-06-06 | 1983-06-06 | Manufacture of thin film transistor matrix array |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59225568A true JPS59225568A (en) | 1984-12-18 |
Family
ID=14247391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58099437A Pending JPS59225568A (en) | 1983-06-06 | 1983-06-06 | Manufacture of thin film transistor matrix array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59225568A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01235385A (en) * | 1988-03-16 | 1989-09-20 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1983
- 1983-06-06 JP JP58099437A patent/JPS59225568A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01235385A (en) * | 1988-03-16 | 1989-09-20 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
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