JP3265702B2 - Thin film transistor panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor panel used for an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor panel (hereinafter referred to as a TFT panel) used for an active matrix liquid crystal display element has the following configuration.

Generally, a liquid crystal display element is manufactured by a method of assembling a plurality of liquid crystal display elements at once.
This method is used to manufacture a liquid crystal display element.
The FT panel is sized to collect panels for a plurality of liquid crystal display elements.

FIG. 4 is a plan view of a conventional TFT panel used when manufacturing a liquid crystal display element by the above-mentioned manufacturing method.
The TFT panel includes a plurality of transparent pixel electrodes 2 arranged vertically and horizontally on a transparent substrate 1 made of glass or the like, a plurality of thin film transistors (TFTs) 3 connected to the respective pixel electrodes 2, And a data line DL for supplying a data signal to the thin film transistor 3.

The substrate 1 has a plurality of liquid crystal display elements having a T
A large-sized substrate large enough to collect an FT panel, and a portion of each liquid crystal display element to be a TFT panel is a region (hereinafter, referred to as an element region) 1A corresponding to the size of the liquid crystal display element.
And a blank portion 1B secured around the element region 1A.
The gate and the data lines GL and DL are formed in the element region 1A.

The margin 1B is formed in the final (TFT
This part is removed after the panel and the counter electrode forming panel are joined and the liquid crystal display element is assembled).
B is divided and removed along two vertical and horizontal dividing lines c along the outline of the element region 1A, which is indicated by a dashed line in the figure.

FIG. 5 is an enlarged plan view of a part of the TFT panel, and FIGS. 6 and 7 are lines VI-VI and VII-VI of FIG.
FIG. 3 is an enlarged sectional view taken along the line I, showing the thin film transistor 3;
Is a gate electrode G formed integrally with a gate line GL wired on the substrate 1 as shown in FIGS.
A gate insulating film 4 made of SiN (silicon nitride) or the like covering the gate electrode G, and an i-type made of a-Si (amorphous silicon) formed on the gate insulating film 4 so as to face the gate electrode G. A semiconductor film 5 and n made of a-Si doped with impurities on the i-type semiconductor film 5;
It is composed of a source electrode S and a drain electrode D formed with the mold semiconductor film 6 interposed therebetween.

The gate insulating film 4 of the thin film transistor 3
As shown in FIG. 4, the pixel electrode 2 and the data line DL are formed on the gate insulating film (transparent film) 4 over substantially the entire surface of the substrate 1 covering the gate line GL. ing. In FIG. 4, GLa is a terminal portion formed at one end of the gate line GL, DLa is a terminal portion formed at one end of the data line DL, and the terminal portion GLa of the gate line GL is a data line DL. Is formed, an opening 4a is formed in the gate insulating film 4 to be exposed.

The pixel electrode 2 has one end connected to the source electrode S of the thin film transistor 3 and the data line DL connected to the drain electrode D of the thin film transistor 3.
Is connected to In this TFT panel, the data line DL is formed integrally with the drain electrode D of the thin film transistor 3. However, the TFT panel has an interlayer insulating film on the gate insulating film 4 which also serves as a protective film of the thin film transistor 3. And a data line DL is formed on the interlayer insulating film.
In the panel, the data line DL is connected to the drain electrode D at a contact hole provided in the interlayer insulating film.

The above-mentioned TFT panel has an alignment film (not shown) made of polyimide or the like formed thereon, rubbed the surface of the alignment film, and then sent to a liquid crystal display element assembling step. In this case, during the rubbing treatment of the alignment film, strong static electricity is generated due to friction between the rubbing cloth and the alignment film, and the gate line GL and the data line DL are generated.
And the thin film transistor 3 may cause dielectric breakdown due to static electricity.

For this reason, in the TFT panel, the gate line GL and the data line DL are short-circuited in the margin 1B to prevent dielectric breakdown due to static electricity.

That is, as shown in FIG.
A short-circuit path 10 for short-circuiting the gate line GL and the data line DL is formed in the margin 1B of the T panel, and both ends of the gate line GL and both ends of the data line DL are respectively led to the margin 1B. It is connected to the short circuit path 10.

The short-circuit path 10 is formed in the element region 1A of the substrate 1.
Are formed in an endless frame shape around the entire circumference of the substrate 1. Both ends of the vertical short-circuit path and the horizontal short-circuit path are respectively extended to the outer peripheral edge of the substrate 1, and are formed along the outer peripheral edge of the substrate (not shown). Connected to ground line. The short-circuit path 10 and the ground line are formed integrally with the gate line GL on the substrate 1, and both ends of the data line DL are provided with contact holes (not shown) provided in the gate insulating film 4 therebelow. Are connected to the short-circuit path 10.

As described above, if the gate line GL and the data line DL are short-circuited in the margin 1B, the potentials of the gate line GL and the data line DL become the same. The intersection with the DL and the insulation breakdown of the thin film transistor 3 can be prevented.

In the above-mentioned TFT panel, an interlayer short circuit between the gate line GL and the data line DL and an interlayer short circuit between the gate electrode G of the thin film transistor 3 and the source and drain electrodes S and D are reliably prevented. ,
The surface of the gate line GL and the gate electrode G is connected to the terminal G
Anodization is performed except for La, and an oxide film a is formed on the surface as shown in FIGS.

In the anodic oxidation of the gate line GL, the substrate 1 on which the gate line GL is formed is immersed in an electrolytic solution so that the gate line GL faces the cathode in the electrolytic solution.
Using the gate line GL as an anode, this gate line GL
And the cathode is applied by applying a voltage.

The anodic oxidation of the gate line GL is performed by covering the terminal portion GLa of the gate line GL with a resist mask (not shown), and supplying an oxidizing voltage to the gate line GL. Is the short-circuit path 10
And a ground line as a power supply path.

As described above, when a voltage is applied between the gate line GL and the cathode in the electrolyte, the gate line GL, which is the anode, undergoes a chemical reaction and is anodically oxidized from its surface (upper surface and both side surfaces). Then, an oxide film a is formed on the surfaces of the gate line GL and the gate electrode G.

FIG. 8 is a plan view of both ends of the gate line GL in the above-mentioned TFT panel, and FIGS.
FIG. 11 is an enlarged cross-sectional view taken along lines IX-IX and XX. When the above-described anodic oxidation is performed, the surfaces of the gate line GL and the gate electrode G are removed except for the terminal portion GLa.
Is anodized as shown in FIG. In this case, the portions of the short-circuit path 10 and the ground line that are immersed in the electrolytic solution are also anodized, and an oxide film a is formed on the surface.

The anodic oxidation of the gate line GL is carried out by controlling the voltage applied between the gate line GL and the cathode. Since the voltage is determined by the voltage, by controlling the applied voltage according to the thickness of the wiring, an oxide film a having a desired thickness can be generated on the surface of the gate line GL.

Next, the manufacture of a liquid crystal display device using the above-mentioned TFT panel will be described.
After an alignment film is formed on each of the element regions 1A of the T panel, the TFT panel and a counter electrode forming panel (not shown) are formed on each of the element regions of the transparent substrate from which a plurality of liquid crystal display elements can be collected. And one having an alignment film formed thereon) are joined to one panel via a frame-shaped sealing material which is printed so as to surround the liquid crystal enclosing region of each element region. It is manufactured by separating a three-dimensional body into individual elements, and then enclosing liquid crystal in each element. Separation of the above assembly into individual elements is performed by scribing along the contour of each element region on the substrate of the TFT panel and the counter electrode forming panel, and cutting both panels at this location. .

In this case, the TFT panel is divided along two vertical and horizontal dividing lines c along the contour of the element region 1A, and when the TFT panel is divided at this point, the TFT panel is divided into the margin 1B of the substrate 1. The formed short-circuit path 10 is removed together with the margin 1B, and each gate line GL and each data line DL short-circuited via this short-circuit path 10 are removed.
Are separated into individual lines. FIG. 11 and FIG. 12 are enlarged cross-sectional views showing a state in which the blank portion 1B along the line IX-IX and line XX of FIG. 8 is divided and removed.

[0023]

However, the liquid crystal display device using the above-mentioned conventional TFT panel has a problem that its life is short.

This is because the gate line GL and the data line DL are electrolytically corroded from the end faces thereof (the end faces after the margin 1B is cut off) during use of the liquid crystal display element. The surface of the gate line GL is anodically oxidized. However, when the margin portion 1B of the TFT panel is divided and removed, the metal portion of the gate line GL (the portion excluding the oxide film a on the surface) becomes a line end surface (divided line). 11 and 12, the metal portion is electrolytically corroded from the exposed end.

In this electrolytic corrosion, the end faces of the gate line GL and the data line DL are exposed to the air, and in this state, the line mutual ends between the ends of the gate lines GL and between the ends of the data lines DL. This is caused by the flow of leakage current due to the potential difference between them.

That is, the active matrix liquid crystal display element is driven by applying a gate signal to each gate line GL sequentially and applying a data signal corresponding to image data to each data line DL. Generates a potential difference corresponding to the voltage of the gate signal, and a potential difference between the data lines corresponding to the voltage of the data signal applied to each line.

Since the ionic impurities adhered during the division of the blank portion 1B and during the subsequent display element manufacturing process and the like remain on the divided end surfaces of the TFT panel, the gate lines and the data lines are separated. When a potential difference occurs, a leakage current flows between the ends of each line using the ionic impurity as a medium, and an electrolytic reaction occurs due to the leakage current and moisture in the air, so that the gate line GL and the data line DL move from the end surface thereof. Electrolytic corrosion.

Further, when the metal corrodes, its volume increases, and when the electrolytic corrosion progresses into the display area of the liquid crystal display element, the gate line GL and the data line DL are expanded due to the corrosion of the metal part. As a result, the gate insulating film 4 and the alignment film (not shown) are lifted up or broken, and the alignment state of the liquid crystal in that region is disturbed, and a stain-like abnormal display is generated in the display area.

The degree of the progress of the electrolytic corrosion depends on the amount of the leakage current and the area of the cross section (gate line GL) orthogonal to the corrosion progress direction (line length direction) of the gate line GL and the data line DL. The cross-sectional area of the metal portion) determines that the smaller the amount of leakage current and the larger the cross-sectional area of the line, the slower the electrolytic corrosion progresses, so that the terminal portions GLa and DLa of the gate line GL and the data line DL are The electrolytic corrosion from the formed end portion is due to the terminal portions GLa and DLa having a large cross-sectional area.
When it reaches, its progress is suppressed.

However, in the conventional TFT panel, since the electrolytic corrosion from the end portions of the gate lines GL and the data lines DL where the terminals are not provided proceeds without being restrained on the way, the electrolytic corrosion from the end portions does not occur. Moves into the display area in a relatively short period of time.

For this reason, in a liquid crystal display element using a conventional TFT panel, an abnormal display such as a stain pattern occurs in a display area before a deterioration in display quality due to natural deterioration of liquid crystal or the like starts to appear. It becomes unusable at that point.

The present invention suppresses the progress of electrolytic corrosion from the end portions of the gate line and the data line which are not provided with the terminals, and reduces the occurrence of spot-like abnormal display in the display area of the liquid crystal display element. It is an object of the present invention to provide a TFT panel that can prevent the liquid crystal display element for a long period of time and greatly improve the life of the liquid crystal display element.

[0033]

According to the present invention, a TFT panel is provided in a device region corresponding to a liquid crystal display device on a transparent substrate.
A plurality of pixel electrodes, a plurality of thin film transistors respectively connected to these pixel electrodes, a gate line for supplying a gate signal to the thin film transistor, and a data line for supplying a data signal to the thin film transistor, At least one of the two ends of the gate line and the data line and the outside of the element region.
A corrosion delay portion for delaying the progress of electrolytic corrosion in the line length direction is formed between the peripheral edge and the peripheral edge . The TFT panel of the present invention, the liquid on the substrate
Pixels formed in the element region corresponding to the crystal display element
And electrodes, respectively connected to the plurality of pixel electrodes
A plurality of thin film transistors;
A gate line for supplying the over preparative signal, the thin film Transitional
A data line for supplying a data signal to the star, and the substrate
It is formed on the outer margin portion from the device region of the upper, the gate
Short-circuit path for short-circuiting the data line and the data line
And the gate line of the element region on the substrate and
Of both end portions of the fine said data lines, at least one of
These are short-circuited between the end and the short-circuit path in the margin.
Allowed, and the width of the gate line and the Detara
Metal part formed to a width larger than the width of the in
It is characterized by that.

[0034]

According to the TFT panel of the present invention, a corrosion delay portion for delaying the progress of electrolytic corrosion in the length direction of the line is formed at least at one of the two ends of the gate line and the data line where there is no terminal. Therefore, the progress of electrolytic corrosion from the end portions of the gate line and the data line where no terminal portion is provided is suppressed in the corrosion delay portion.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a TFT panel,
FIG. 2 is a plan view of both ends of the gate line. In FIGS. 1 and 2, those corresponding to the conventional TFT panels shown in FIGS. 4 to 12 are denoted by the same reference numerals, and redundant description will be omitted.

In the TFT panel of this embodiment, a corrosion delay portion P for delaying the progress of electrolytic corrosion in the line length direction is provided in a portion inside a marginal portion cut off at both ends of the gate line GL and the data line DL. The other structure is the same as that of the conventional TFT panel.

That is, the TFT panel includes a plurality of pixels on a transparent substrate 1 (on an element area 1A corresponding to the size of a liquid crystal display element) having a margin 1B around the periphery which is finally separated and removed. An electrode 2, a plurality of thin film transistors 3 connected to each of the pixel electrodes 2, a gate line GL for supplying a gate signal to the thin film transistor 3, and a data line DL for supplying a data signal to the thin film transistor 3 are formed. A short-circuit path 10 for short-circuiting the gate line GL and the data line DL is formed on the margin 1B of the substrate 1. Both ends of the gate line GL and the data line DL are connected to the margin 1B of the substrate 1. And is connected to the short-circuit path 10.

In this embodiment, the gate line G
L and the data line DL are formed in a shape in which the width of a portion inside the marginal portion cut portion (divided line c) at both ends is locally widened, and the wide portion is a corrosion delay portion P. The width and length of the corrosion delay portion P are substantially equal to the width and length of the terminal portions GLa and DLa of the gate line GL and the data line DL. The surface of the gate line GL except for the terminal portion GLa is anodized including the surface of the corrosion delay portion P.

In this TFT panel, a corrosion delay portion P for delaying the progress of electrolytic corrosion is formed in a portion inside a marginal portion cut off at both ends of the gate line GL and the data line DL. During the use of the device, the corrosion delay section P can prevent the gate line GL and the data line DL from being electrolytically corroded from the end faces thereof (the end faces obtained by dividing and removing the margin 1B).

That is, the degree of the progress of the electrolytic corrosion is as follows:
As described in the section of [Problems to be Solved by the Invention], the amount of leakage current flowing as a medium using ionic impurities attached to the divided end faces of the TFT panel due to the potential difference between the lines, Data line D
L (corresponding to the cross-sectional area of the metal part in the gate line GL),
The smaller the amount of leakage current and the larger the cross-sectional area of the line, the slower the progress of electrolytic corrosion.
Electrolytic corrosion from the end side of L and data line DL
When the corrosion retarding portion P having a large cross-sectional area and having a large width is reached, its progress is suppressed.

Therefore, according to the TFT panel, it takes a long time until the electrolytic corrosion of the gate lines GL and the data lines DL progresses into the display area of the liquid crystal display element. It is possible to prevent a stain pattern abnormal display due to corrosion of the data line DL from occurring for a long period of time, and to greatly improve the life of the liquid crystal display element.

In the above embodiment, the gate line GL
In addition, the corrosion delay portion P of the data line DL is a wide portion whose width is larger than the width of the gate line GL and the data line DL. The corrosion delay portion P is formed by meandering the gate line GL and the data line DL. You may.

FIG. 3 is a plan view of both ends of a gate line according to a second embodiment of the present invention. In this embodiment, the inner side of the marginal portion (divided line c) at both ends of the gate line GL is shown. Is meandering, and the meandering portion is a corrosion delay portion P.

Although not shown, in this embodiment, the data line also has a meandering portion inside the marginal portions at both ends, and the meandering portion is a corrosion delay portion. Further, the meandering line of the corrosion delay part P is a gate line G
It is formed to be slightly wider than the width of L and data line DL.

Also in this embodiment, the gate line GL
In addition, since the electric field corrosion from the end side of the data line DL progresses meandering in the corrosion delay portion P, the electric field corrosion in the line length direction hardly progresses, and therefore, the gate line GL and the data line DL It takes a long time until the electrolytic corrosion of the liquid crystal display element progresses into the display area, and therefore, the gate line GL is provided in the display area.
In addition, it is possible to prevent the abnormal display of a stain pattern due to the corrosion of the data line DL from occurring for a long period of time, and to greatly improve the life of the liquid crystal display element.

In the first and second embodiments,
Corrosion delay portions P are provided at both ends of the gate line GL and the data line DL. Electrolytic corrosion from the ends of the lines GL, DL forming the terminal portions GLa, DLa has a large cross-sectional area. Terminal parts GLa, DL
a, the progress is suppressed at the time of reaching the gate line GL and the terminal portions GLa, D of the gate line GL and the data line DL.
It is not necessary to form the above-mentioned corrosion delay part P on the end part side where La is formed.

[0047]

According to the TFT panel of the present invention, at least one of both ends of the gate line and the data line is provided with a corrosion delay portion P for delaying the progress of electrolytic corrosion in the line length direction. Therefore, the progress of electrolytic corrosion from the ends of the gate lines and data lines is suppressed, and the occurrence of spot-like abnormal display in the display area of the liquid crystal display element is prevented for a long time. The life can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a TFT panel according to a first embodiment of the present invention.

FIG. 2 is a plan view of both ends of a gate line in the TFT panel of FIG.

FIG. 3 is a plan view of both ends of a gate line according to a second embodiment of the present invention.

FIG. 4 is a plan view of a conventional TFT panel.

FIG. 5 is an enlarged plan view of a part of a conventional TFT panel.

FIG. 6 is an enlarged sectional view taken along the line VI-VI of FIG. 5;

FIG. 7 is an enlarged sectional view taken along line VII-VII of FIG. 5;

FIG. 8 is a plan view of both ends of a gate line in a conventional TFT panel.

FIG. 9 is an enlarged sectional view taken along line IX-IX in FIG. 8;

FIG. 10 is an enlarged sectional view taken along line XX of FIG. 8;

FIG. 11 is an enlarged cross-sectional view showing a state where a blank portion along the line IX-IX in FIG. 8 is divided and removed.

FIG. 12 is an enlarged cross-sectional view of a state in which a blank portion along the line XX in FIG. 8 is divided and removed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 1A ... Element area 1B ... Blank part c ... Divided line 2 ... Pixel electrode 3 ... Thin film transistor GL ... Gate line GLa ... Terminal part a ... Oxide film DL ... Data line DLa ... Terminal part P ... Corrosion delay part 10 ... Short circuit Road

Claims (4)

(57) [Claims] 1. A thin film transistor panel using an active matrix liquid crystal display element, wherein a liquid crystal on a transparent substrate is provided.
A plurality of pixel electrodes in an element region corresponding to the crystal display element ,
A plurality of thin film transistors connected to each of the pixel electrodes; a gate line for supplying a gate signal to the thin film transistor; and a data line for supplying a data signal to the thin film transistor, wherein the gate line and the data line are formed. A corrosion delay portion for delaying the progress of electrolytic corrosion in the line length direction is formed between at least one of the two end portions and the outer peripheral edge of the element region. TFT panel. 2. The thin film transistor panel according to claim 1, wherein the corrosion delay portion has a width larger than a width of the gate line and the data line. 3. The thin film transistor panel according to claim 1, wherein the corrosion delay section is formed by meandering a gate line and a data line. (4) Use active matrix liquid crystal display
Thin film transistor panel , Liquid crystal table on board
Pixel electrodes formed in the element region corresponding to the display element
When , A plurality connected to each of the plurality of pixel electrodes
A thin film transistor and a gate to the thin film transistor
A gate line to supply signals , The thin film transistor
A data line for supplying a data signal to the , Formed in a margin outside the element region on the substrate.
Re , Shorting the gate line and the data line
Short circuit , The gate line and the front of the element region on the substrate
Of both ends of the data line , At least one end
And between the short-circuit path in the margin and ,
And the width is the gate line and the data line
Metal part formed to have a width larger than the width of
And a thin film transistor panel.