JPS59222957A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to microscopically form a CMOS and to reduce the generation of latch-up by a method wherein an MOS field-effect transistor of a reverse conductive type to a substrate is provided at a diffusion region, which conducts with the substrate, and an MOS field-effect transistor of the same conductive type as the substrate is provided in an epitaxial layer, and moreover, the buried layer of a reverse conductive type is provided at the lower part of the transistor of the same conductive type. CONSTITUTION:A P type buried layer 3 and P type well layer 5, which is formed from the surface of an epitaxial layer 4, are made to respectively contact to the prescribed parts of the N type epitaxial layer 4, thereby forming a diffusion region, which conducts with a substrate. An N type channel MOS transistor is formed at the surface region of the P type well layer 5. A P channel MOS transistor is formed at the surface region of an epitaxial layer 2 other than the P type well layer 5. Before the P channel MOS transistor is provided, this transistor has been readied to such a structure that an N type buried layer can be provided at any time at the lower part thereof. By complementarily connecting the N channel MOS transistor and the P channel MOS transistor, a CMOS circuit can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a novel semiconductor device that enables miniaturization of CMO8 semiconductor devices, reduction of latch-up, and improved performance of CMOS. .

Conventional configurations and their problems CMOS (complementary MO8) LSIs have the characteristics of extremely low power consumption and large operating margins, and have made remarkable progress by taking advantage of these characteristics. As the range of applications expands, the demand for not only lower power consumption but also higher performance, such as higher speed and higher density, is increasing.

In particular, compared to the n-channel type MO8 circuit, the 0M08 circuit has
M in a relatively high concentration well with a large input capacity.
It was considered that slow operation speed was unavoidable due to the formation of O8 type field effect transistors, but in recent years 0M08
With the rapid expansion of the application range of circuits, there is a growing need for 0M08 circuits to increase speed without sacrificing the low power consumption that is a feature of 0MO3.

Miniaturization of 0MO3 is considered to be the most effective way to increase speed while maintaining the features of 0MO3, but in 0MO8, n-channel MOS transistors and P
Channel-type MO3) transistors coexist on the same substrate, so when attempting to miniaturize 0MO5, in addition to the problems of Mo5t and transistors (short channel effect, decrease in punch-through withstand voltage, high electric field effect), latch-up phenomena etc. Problems arise that make parasitic effects more likely. In other words, in order to miniaturize OMO3, in addition to miniaturizing MOS transistors, it is necessary to miniaturize wells, and in particular to form shallow wells in order to suppress the spread of diffusion in the lateral direction of the well. If the depth is made shallower, the longitudinal risk becomes less strong and the launch amplifier phenomenon becomes more likely to occur.

Therefore, in the conventional miniaturization of 0MO8, in order to prevent latch-up, even if the miniaturization progresses, the depth of the well cannot be reduced, and the depth must remain at about 5 μm. Therefore, CMO, which can miniaturize wells and reduce latch-up, has been developed.
3 semiconductor devices were desired.

OBJECTS OF THE INVENTION An object of the present invention is to provide a novel structure of a semiconductor device that is capable of miniaturizing OMO8 and reducing latch-up.

Structure of the Invention In order to achieve the above object, the present invention provides an epitaxial layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and a part of this epitaxial layer includes a well layer from the surface of the epitaxial layer and a buried layer of the substrate part. A MOS field effect transistor of the opposite conductivity type to the substrate is provided in the diffusion region conductive to the substrate, and a MOS field effect transistor of the same conductivity type as the substrate is provided in the epitaxial layer. Further, a buried layer of a conductivity type opposite to that of the substrate is provided under the MOS field effect transistor of the same conductivity type as the substrate, and the structure of the present invention enables miniaturization of a CMO8 semiconductor device, It is possible to reduce latch-up and realize higher performance of the coos circuit.

Description of examples Hereinafter, specific examples will be described using the drawings.

FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor device that is an embodiment of the present invention. In the figure, a p-type silicon substrate 1
An n-type buried layer 2 and a p-type buried layer 3 are formed thereon, and an n-type epitaxial layer 4 is formed thereon. p
For example, the impurity concentration of the mold silicon substrate 1 is about 101
52□5 is used. The n-type epitaxial layer 4 is
Arsenic was used as an impurity at a concentration of about 1015 cm-5, and the thickness was 3 μm. Further, the impurity concentration of the n-type buried layer 2 was about 1018σ-3, and the impurity concentration of the p-type buried layer was about 1015.

Next, the p-type buried layer 3 and the p-type well layer 5 formed from the surface of the epitaxial layer 4 are brought into contact with a predetermined portion of the n-type epitaxial layer 4, thereby forming a diffusion region conductive to the substrate. The surface concentration of impurities in the p-type well layer 5 is about 2 x 1016 -6, and the diffusion depth is about 165.
It was set as μm. In the heat treatment for forming the p-type well layer 5, the p-type buried layer 3 is diffused upward, so the heat treatment conditions are controlled so that the p-type well layer 6 and the p-type buried layer overlap.

In the surface region of the p-type well layer 6 formed as described above, n
A channel type MO6) transistor is formed. This transistor has a structure in which n-type diffusion layers 6 and 7 are used as a source and a drain, respectively, and a gate electrode 9 is provided on a gate insulating film 8. As the gate insulating film 8, a silicon dioxide film is used, and as the gate electrode 9, a metal electrode made of polysilicon, for example, is used.

Furthermore, a p-channel type MO transistor is formed in the surface region of the epitaxial layer 2 other than the p-type well layer 5. This transistor has a p-type diffusion layer 10.11 as a source and a drain, and a gate electrode 1 on a gate insulating film 12.
It has a structure with 3. A silicon dioxide film is used as the gate insulating film 12, and a metal electrode made of polynolycon, for example, is used as the gate electrode 13. Before providing the switched p-channel MO8) transistor, the structure is such that an n-type buried layer is always provided under the transistor. Furthermore, in the figure, the n-type diffusion layer 14 and the p-diffusion layer 15 are semiconductor diffusion regions provided as guard bands.

Finally, the 0M03 circuit can be realized by complementarily connecting the n-channel MO3) transistor and the p-channel MOS transistor.

In the structure of the CMO3 semiconductor device obtained as described above, the n-type buried layer 3 is buried in advance under the p-type well layer 5, and the p-type well layer 5 is formed by shallow diffusion. This makes it possible to suppress the lateral diffusion of the p-type well layer 5, thereby making it possible to miniaturize the well and increase the degree of integration of p-type CMO3.

FIG. 2 shows an equivalent circuit of the parasitic transistor in FIG. 1. In the same figure, 16 is a parasitic NpN
1-transistor, 17 is the resistance between the base and emitter of the parasitic NPN transistor, 18 is the parasitic PNPI-transistor, and 19 is the resistance between the base and emitter of the parasitic PNP transistor. In the structure of the embodiment of the present invention, an n-type buried layer 2 is provided under the P-channel type MOS transistor;
It has an n-type buried layer 3 under the n-channel MO transistor 8), and the base regions of the parasitic NPNI transistor 16 and the W raw PNP transistor 18 both have a structure with high impurity concentration. Therefore, the hfe of these parasitic transistors is kept low.

In addition, the n-type buried layer 2 and the parasitic PNP transistor 1
8 by lowering the base-emitter resistance 19 (parasitic PNP)
It is difficult to turn on the transistor 18. Similarly, the Kp type buried layer 3 lowers the resistance 17 between the parasitic NpN1 and the base φ emitter of the transistor 16, making it difficult to turn on the parasitic NpN transistor 16.

As described above, in the structure of the semiconductor device of the present invention, the impurity concentration in the base region of the parasitic transistor is increased and the resistance between the base and emitter is reduced, making it difficult for the parasitic transistor to turn on. Latch-up phenomenon is less likely to occur.

Effects of the Invention As described above, according to the structure of the present invention, CiVI
It is possible to miniaturize the OS and reduce latch-up, reducing C1
This greatly contributes to improving the performance of vlIO3.

[Brief explanation of drawings]

FIG. 1 is a structural sectional view of a semiconductor device which is an embodiment of the present invention, and FIG. 2 is a diagram for explaining the present invention in detail. 1...p-type silicon substrate, 2...n-type buried layer, 3...n-type buried layer, 4...n-type epitaxial layer, 5...p-type Well layer, 6,7
...Source, drain, 8...gate insulating film, 9...gate electrode, 10.11...source, drain, 12...gate insulating film, 13...・
・Gate electrode, 14... n-type diffusion layer, 15...
P-type diffusion layer, 16... Parasitic/: J Lima PNF synister, 17... Base-emitter resistance of parasitic NpN transistor, 18... Parasitic PNP transistor, 19... ...Base-emitter resistance of a parasitic PNP transistor. Figure 1 ρ Figure 2 θ

Claims (1)

[Claims] - an epitaxial layer of opposite conductivity type formed on a conductivity type semiconductor substrate; a buried layer of one conductivity type and a buried layer of opposite conductivity type formed at the interface between the epitaxial layer and the substrate; - a well layer reaching a buried layer of conductivity type, an MO3 type field effect transistor of an opposite conductivity type is formed in the well layer, and an MO8 type field effect transistor of one conductivity type is formed in the epitaxial layer on the buried layer of the opposite conductivity type; A semiconductor device that forms a transistor.