JPS6059771A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device of C-MOS transistor structure capable of completely preventing a latchup phenomenon by forming the high density first conductive type first buried layer and the second conductive type second buried layer selectively in the first on second conductive type semiconductor substrate. CONSTITUTION:Since the high density region of an N<+> type buried layer 13 exists in a base region in a vertical parasitic parasitic bipolar transistor Tv, its current amplification factor can be reduced sufficiently from 1. Even is the current amplification factor of lateral transistors Tl1, Tl2 increases as compared with 1 due to the non-formation of channel cut layers 22, 23, equivalent parasitic resistance of P-well region 16 and N type epitaxial layer 15 decreases by approximately several tens to hundreds times due to the presence of the layer 13 and a P<+> type buried layer 14. Thus, even when a surge current is externally inputted, a potential difference generated between the base and the emitter of parasitic lateral transistors Tl1, Tl2 becomes extremely low, thereby effectively preventing the latchup.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a complementary field effect transistor with reduced latch-up.
The present invention relates to a body device iJ% and a manufacturing method thereof.

[Technical background of the invention and its problems]

Complementary field effect transistors, especially MOS 2'+'-
In semiconductor devices, the so-called launch-up phenomenon often becomes a problem. This latch amplifier phenomenon is as follows. That is, ;r "As shown in Figure 1, in the MO3 type semiconductor device, K(
- Using the diffusion layer 4 and the well 3 as emitters and bases, respectively, N-type epitaxial /i'J 2 and N
A parasitic vertical pi moon whose collector is the shaped semiconductor substrate 1? - Parasitic lateral pie J? with ratrannosk Tv, one diffusion layer 4, P-type well, 9, and N-type epitaxial layer 2 as emitter, base, and collector. ~Latransosme Tt1 and well 3, epitaxial layer 2, P
A parasitic lateral bypass with the diffusion layer 5 as the collector, base, and emitter? - latrannosta Tt2 is formed in the device. And the parasitic pi polar trunks on the 1\T channel MO3 side and the parasitic pi on the P channel 840S side, J? - If the product of the current amplification factor with the polar transistor is greater than 1 and a current is input from the outside, the parasitic/polar transistor operates as a zyristor, and the external transistor and the inside of the device A large current flows during this period, and the device is eventually destroyed. This latch-up phenomenon continues until the device is turned off.

In the figure, the insulating film formed on the wafer is omitted and the gate electrode cN+GP is schematically shown.

Conventionally, as a countermeasure against such latch-up phenomenon, for example, N
In some cases, a substrate having a higher concentration than the N-type epitaxial layer 2 is used as the N-type semiconductor substrate 1 . As a result, the current increase rate 11a of the parasitic lateral transistor was reduced, and although some effect was seen, 1 was insufficient to completely prevent latch-up.

In addition to such countermeasures, for example, an N+ layer with a higher concentration than this was provided under the N-type well in which the P-channel MO3) runnostar was formed, but this was also insufficient. (For more information on this, please refer to IBM, Tech,
Dis, Bul Ietin, vol, 1 (5°N
o, 8 January 1974. pp2719-2
720. ) [Objective of the Invention] The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device with an 0MO3) lunge structure that can completely prevent the latch amplifier phenomenon, and to provide an efficient manufacturing method thereof. That is.

[Summary of the Invention] That is, according to the semiconductor device of the present invention, a highly concentrated first
A first buried layer of a conductivity type and a second buried layer of a second conductivity type are provided, and a pitaxial layer of the first conductivity type is formed on the substrate. A well region of a second conductivity type is provided on the second buried layer so as to be electrically coupled to the buried layer, and a well region of a second conductivity type is provided on the epitaxial layer above the first condyle 1. Two diffusion layers of the first conductivity type are formed in the well region as the source and drain of the second conductivity type channel MOS transistor, and the source and drain of the first conductivity type channel MO8) lannostar. Then, a predetermined dirt electrode is formed on the epitaxial layer via a %'5'') insulating film.Furthermore, the first buried electrode is connected to a power source in a direction in which the second diffusion layer is reverse biased. A first current extraction portion of the first conductivity type connected to the buried layer is connected to a power source in a direction in which the first diffusion layer is reverse biased to a second conductivity type channel MO8) transistor region and connected to the second buried layer. It is more effective if the second current extraction portions of the second conductivity type are provided in the first conductivity type channel HoS, ) Lansosk regions, respectively.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

First, as shown in Figure 2+a), for example, the substrate 0 degree 1014
~1015 low 1. For example, as an insulating film for a diffusion mask on a high-quality P-type silicon substrate 1,
2, and an opening is provided at the site under which the P-channel trannosmation is planned to be formed. And, for example, sb (
For example, using antimony) or As (arsenic),
An r-buried layer 13 with a high Ck degree of 10 cm 8a is formed on the substrate 1. this? During the process of forming the buried layer 13, the above opening is covered with a thermal oxide film 12□. Next, the thermal oxide film 1 is located under the area where the N-channel transistor is to be formed.
2 with an opening, for example, by boron ion implantation or a silica glass film containing boron ions (so-called BSG film).
12' is deposited on the substrate 1, and boron is diffused into the substrate 11 to form a P buried layer 14 having an impurity concentration of, for example, about 1017 to 10''m-' and a height of 2 degrees. do.

Next, all of the j1 film formed on the substrate 11 is removed, and as shown in FIG.
A shaped epitaxial layer 15 is deposited. During this epitaxial growth step, impurities in N+ buried layer 13 and P buried layer 14 are mainly diffused upward into N type epitaxial layer 15.

Note that the conditions such as the layer thickness and resistivity of the N-type epitaxial layer 15 described above are merely a guideline, and should be changed as appropriate depending on the conditions of the device to be formed.

Next, specific elements are formed using such a semiconductor wafer. First, as shown in FIG. 2fc), thermally oxidized jlq 122 of about 10 countries, accelerating voltage under the condition of 150 keV, e.g. 1100° ~
A thermal diffusion treatment is performed at approximately 1200°C. This is fi C
A P well region 16 is formed on the P buried layer 14 as an N channel transistor formation region of the IvllO3 transistor, with the P buried layer 14 as the bottom.

Next, the epitaxial layer I′, 21 on the N+ buried layer 13 is
N-type impurity is deeply diffused from a part of the surface of 5 at a height of t1 degree to form an N+ current extraction portion 18 connected to the N+ buried layer 13. Similarly, P type impurity is deeply diffused from a part of the surface of the P well region 16 at a high concentration to form a P+ current extraction portion 19 connected to the P+ buried layer 14.

Next, after removing the thermal oxide film 122, as shown in FIG. 2 (ω), the upper surface of the wafer is formed. The laminated film is formed into a laminated film and turned into a predetermined shape.

Incidentally, if necessary, selective ion implantation (channel cut implantation) for preventing field r inversion is performed as appropriate using N-type impurities on the surface of the N-type evimexial layer 15 and P-type impurities on the surface of the P well region 16. An N-type channel cut layer 22 and a P-type channel cut layer 23 are formed, respectively. Then, selective oxidation is performed at a low temperature of, for example, 900°C to 1000°C, using the non-oxidizing film 2 as a mask, as shown in FIG.
), a field oxide film 24 having a thickness of approximately 0.7 to 10 μm is formed.

Next, the non-oxidizing film 2 and the thermally oxidized film 123 are removed, and thermally oxidized Lb for Case 1 is applied to the exposed silicon surface. Forms 12g. Further, appropriate ion implantation for controlling the transistor value is performed in the region where the run raster is to be formed. Note that the ion implantation for this 1 value control may be of P type or N type, and in some cases both P type and 1/J type ion implantation may be implanted in the same area in the depth direction. Sometimes it is done by

After that, as shown in FIG. 2(f), a layer of polysilicon If doped with 3 degrees of N-type impurity is formed on the top surface.
By patterning the M-deposited r-to-electrode base, the dark I-electrodes 25p and 25H are formed on the dirt thermal oxide film 12g.

Thereafter, the surfaces of the gate electrodes 25P and 25N are thermally oxidized and covered with a thermal oxide film 124. Then this da-) 'I
! N
For example, what is the device area of the shaped epitaxial layer 15? For example, arsenic ion implantation is performed in the P well region 161'I:. Then, the implanted impurity is activated by heat treatment, and the p4 which becomes the source and drain of the P-channel transistor is formed in the N-type epitaxial layer 15.
- In the diffusion layer 26P and the P-well region 16, anti-diffusion layers 26N, which become the source and drain of the N-channel transistor, are formed, respectively.

Next, as shown in Fig. 2 (fg) K, a passivation film 27 is deposited on the entire surface of the wafer, and then a contact hole for taking out the electrode is made. Provided by turning. Finally, a metal film is deposited on the wafer and patterned to form predetermined electrodes 29 and wiring, completing a CMO8 type semiconductor device.

〔Effect of the invention〕

First, by providing the P buried layer 14 on the N-channel MOS transistor side and the buried anti-buried layer 13 on the P-channel MO8 transistor side as described above, the following improvements can be seen. That is, in FIG. 2 Fg+, the P expansion yy I<i 26p on the P channel MOS transistor side, which conventionally had a large effect on the latch-up phenomenon, is used as the emitter, the N type epitaxial layer 15 and the N+ buried layer 13 are used as the pace diffusion region, Vertical parasitic pi-no. with board 1 as collector? - Since there is a high concentration region of the anti-buried layer 13 in the space region of the transistor Tv, the current increases by 1
The wealth factor hFE can be made sufficiently smaller than 1.

Therefore, a lateral parasitic via j? with the P+ diffusion layer 26 p as the emitter, the N type epitaxial layer 15 as the base, and the P well region 16 as the collector. -Is the current amplification factor of the transistor Tt2 higher than the parasitic pi of the 9-decal type? -It becomes higher than the current amplification factor of Latransostor Tv,
This lateral type parasitic transistor TL2 is the dominant cause of the launch-up phenomenon.

However, this P+ diffusion layer 26P has a shallow diffusion depth, and since a high concentration Oty type channel cut layer 22 using, for example, phosphorus is normally present at the base of this lateral transaster Tj2, this parasitic transistor Tt2 The current amplification factor can be easily reduced to 1 or less.

On the other hand, a parasitic lateral transistor Tt1 having the anti-diffusion layer 26N as an emitter, the P-well region 16 as a base, and the N-type epitaxial layer 15 as a collector is formed on the N-channel MO8r running side. The amplification factor is also the same as the above lateral transistor T.
As in the case of t2, it is easy to suppress the value to 1 or less due to the P-type channel cut layer 23 existing in the portion serving as the pace.

Therefore, the condition for the occurrence of the latch-up phenomenon that the product of the current amplification factors of the parasitic bipolar transistor on the N-channel MO8) transistor side and the parasitic bipolar transistor on the P-channel 1.10S transistor side is not satisfied, Latch phenomenon can be prevented.

Also, suppose Channel Kan l-J threat 22, 2,? By not forming a channel cut,
, 23's effectiveness is weak, lateral transnosta "1 +
Even if the current amplification factor of Tt2 becomes larger than 1 and the above-mentioned latch-up generation conditions are met, the low resistance? Due to the presence of the buried Ji 13 and the P+ buried layer 14, P
The equivalent parasitic resistance of the well region 16 and the N-type epitaxial layer 15 is lowered by about one to two orders of magnitude than in the prior art.

As a result, even if a surge current is input from the outside, the parasitic lateral transistor Tt1. The potential difference generated between the base and emitter of Tt2 becomes extremely small, and latch-up can be effectively prevented.

In addition, in the device of FIG. 2(g), in the N-type epitaxial region 15 and the P-well region 16, there are connected to the N+ buried layer 13 and the P+ W layer 4, and to the positive power supply - and the ground power supply, respectively. Was it done? Current area extraction part 18 and P
+A current extraction portion 19 is formed. This results in
For example, the surge current injected into the P well region 16
Not only from the current area extraction portion 19 (, P well region 16
It was formed over a wide area to be the bottom of P+
It is also effectively absorbed from the buried layer 14.

The same thing can be said about the P-channel MO8) Runnostar side, and the equivalent parasitic resistance in the element region can be made extremely small.

Further, according to the manufacturing method shown in the above embodiment, a CMO8 type semiconductor device having an excellent latch-up prevention function as described above can be efficiently manufactured.

In the above embodiment, a P-type semiconductor substrate 1 is used, but for example, an N-type semiconductor substrate is used, and an N-type epitaxial layer is formed on this N-type substrate. Hereinafter, the device may be manufactured in the same manner as in the above embodiment.

Further, the conductivity type of each part may be completely reversed to that of the above embodiment.

As described above, according to the present invention, it is possible to provide a CMO3 type semiconductor device having an excellent latch-up prevention function as described above, and also to provide an efficient manufacturing method thereof.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a cross-sectional structure of a conventional semiconductor device, and FIG. 2 is a diagram showing a cross-sectional structure of a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps. 11... Semiconductor substrate, 13... Horsefly buried layer, 14...
・P+ buried layer, 15... epitaxial layer, 16...
・P well region, 18...N+ current output portion, 19
...P''-current area) output part, 24...field oxide film, 25F, 25N...dirt electrode, 26p...
P4-diffusion layer, 26N...N" Diffusion M, 27...
passivation film.

Claims (5)

[Claims] (1) A semiconductor substrate, a first buried layer with a high concentration of a first conductivity type, and a second buried layer with a high concentration of a second conductivity type, which are formed in different regions on the substrate; The first formed
an epitaxial layer of a conductivity type, a well region of a second conductivity type formed in the epitaxial layer on the second buried layer so as to be in contact with the second buried layer, and an epitaxial layer on the first buried layer. The first of the first isoelectric type at high concentration was formed internally.
a current extraction section, a high concentration, second conductivity type 21st current extraction section formed in the well region, and a pair of first conductivity formed at a predetermined distance in the surface area of the well region. a pair of second diffusion layers of a second conductivity type formed at a predetermined distance from the surface region of the epitaxial layer on the first buried layer; A first dirt electrode is formed between the diffusion layers via a dirt insulating film, and a dirt electrode is formed between the second diffusion layers in the epitaxial region.
1. A semiconductor device comprising a second gate electrode formed via a gate KAf, a second gate electrode 131, (2) The first current extraction portion of the first conductivity type is the first current extraction portion of the first conductivity type.
2. The semiconductor device according to claim 1, further comprising a layer connected to the buried layer. (3) The second current extraction portion of the second conductivity type is
A 1-pin semiconductor device according to claim 1 or 2, characterized in that the semiconductor device is connected to a buried layer. (4) The first current extraction portion of the first conductivity type is connected to the second current extraction portion of the first conductivity type.
The diffusion layer is connected to a power source in a direction in which the diffusion layer is reverse biased, and the second current extraction portions of the second conductivity type are each connected to a power source in a direction in which the first diffusion layer is reverse biased. A semiconductor device according to any one of claims 1 to 3. (5) A first layer with a high Ga content in different regions of the semiconductor substrate.
a step of selectively forming a first buried layer of conductive type and a second buried layer of high concentration second conductive type; forming an epitaxial layer of a first conductivity type on the semiconductor substrate; and forming a second well region of a second conductivity type on the second buried layer with the buried first layer as a bottom. The process and the above 1st! +I↓A step of forming a first current extraction portion of the first conductivity type with a high concentration in the epitaxial layer on the buried layer, and a step of forming a second current of the second conductivity type with a high concentration in the well region on the second buried layer. a step of forming a take-out portion;
A step of forming a dirt electrode at a predetermined location on the upper layer via a gate insulating film, and a step of forming a dirt electrode at a predetermined interval on the epitaxial layer on the first buried layer as a part of the dirt electrode mask. A pair of second conductive/Ff type second diffusion layers spaced apart from each other by a predetermined distance in the well region on the second buried layer.
1. forming a pair of m1 diffusion layers of the first conductivity type; manufacturing method.