JPS59222927A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59222927A JPS59222927A JP9920083A JP9920083A JPS59222927A JP S59222927 A JPS59222927 A JP S59222927A JP 9920083 A JP9920083 A JP 9920083A JP 9920083 A JP9920083 A JP 9920083A JP S59222927 A JPS59222927 A JP S59222927A
- Authority
- JP
- Japan
- Prior art keywords
- zinc
- layer
- oxygen plasma
- thin film
- film layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は、半導体装置の製造法に関し、特に■−Ｖ族化
合物半導体の表面にＺｎが拡散されている場合において
、メタライゼーションの前処理としての前記表面の処理
法に関する。Detailed Description of the Invention (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular, when Zn is diffused on the surface of a -V group compound semiconductor, the surface is treated as a pre-treatment for metallization. Regarding the processing method.
（従来技術とその問題点）
１１１−Ｖ族化合物半導体を用いた発光素子を製造する
場合、Ｐ型半導体層にオーミック電極を形成する必要が
ある。ところでＰ型半導体に良好なオーミック電極を形
成するためには、一般に半導体のキャリヤ濃度を少くと
もｌ Ｘ Ｉ Ｑ ”ｔｒｉ３以上まで高くすることが
望ましいが、そのために、封管法による亜鉛（Ｚｎ）の
拡散法が広く用いられている。(Prior art and its problems) When manufacturing a light emitting device using a 111-V group compound semiconductor, it is necessary to form an ohmic electrode on a P-type semiconductor layer. By the way, in order to form a good ohmic electrode on a P-type semiconductor, it is generally desirable to increase the carrier concentration of the semiconductor to at least 1 The diffusion method is widely used.
このような製造法を用いた半導体装置の代表的な例とし
てガリウムアルミニウム砒素（ＧａＡＩＡｓ）ダブルへ
テロ接合型発光ダイオードが挙げられる。A typical example of a semiconductor device using such a manufacturing method is a gallium aluminum arsenide (GaAIAs) double heterojunction type light emitting diode.
以下発光ダイオードの製造への実施例を用いて本発明の
詳細な説明する。The present invention will be described in detail below using an example for manufacturing a light emitting diode.
第１図は、光通信用高輝度発光ダイオードの断面を示す
概念図である。砒化ガリウム（ＧａＡｓ ）基板１上に
活性層３を含んだ四つのエビクキシャルＷｊ ２ 、３
、４． 、５ が形成されており、ダブルへテロ接
合となるために所定のアルミニウムや不純Ｑｊが添加さ
れている。エビクキシャル層５の」二に電流注入用の窓
孔を有する二酸化シリコン（Ｓ １０２）膜６が形成さ
れており、窓孔部下のエビクキシャル層（ＧａＡＩＡｓ
）に亜鉛（Ｚｎ）が拡散されたＰ−−７を有している。FIG. 1 is a conceptual diagram showing a cross section of a high-brightness light emitting diode for optical communication. Four evixical layers Wj 2 , 3 including an active layer 3 on a gallium arsenide (GaAs) substrate 1
,4. , 5 are formed, and predetermined aluminum and impurity Qj are added to form a double heterojunction. A silicon dioxide (S102) film 6 having a window hole for current injection is formed on the second side of the evidential layer 5, and the evixical layer (GaAIAs) under the window hole is formed.
) has P--7 in which zinc (Zn) is diffused.
亜鉛拡散層上には、前記窓孔を通してオーミックコンタ
クトされた電極金属膜８が形成されており、前記二酸化
シリコン膜６上にも同時に形成されている。基板ｌの反
対の面にも電極金属９が形成されている。そして基板に
は、発光した光を外部へ取り出すための窓あけが行われ
ており、エピタキシャル層２が露出している。An electrode metal film 8 is formed on the zinc diffusion layer and is in ohmic contact through the window hole, and is also formed on the silicon dioxide film 6 at the same time. Electrode metal 9 is also formed on the opposite surface of substrate l. A window is formed in the substrate to take out the emitted light to the outside, and the epitaxial layer 2 is exposed.
このような４１へ造を有する発光ダイオードの製造工程
の中で本発明に関係する部分を示すと次のようになる。The steps related to the present invention in the manufacturing process of a light emitting diode having such a 41-shaped structure are as follows.
Ｓ ＋ ０２膜の開化部を形成した後、亜鉛（Ｚｎ）と
砒素あるいは砒化亜鉛（ＺｎＡｓ２）をサースとして石
英アンプル内に真空封入して６００〜７００°Ｃ程度に
加熱し、封管による拡散を行い、Ｐ″一層７ を形成す
る。しかる後に、オーミックコンタクトのためのメタラ
イゼーション工程を行う。After forming the open part of the S + 02 film, zinc (Zn) and arsenic or zinc arsenide (ZnAs2) are vacuum sealed in a quartz ampoule as saas and heated to about 600 to 700°C to prevent diffusion using a sealed tube. Then, a metallization process for ohmic contact is performed.
しかるに、亜鉛（Ｚｎ）が拡散されたエピタキシャル層
の表面に何の処理もせずにメタライゼーションを行うと
、オーミック電極の接触抵抗が著しく高くなって順方向
電圧の高い素子となり、電極８の密着性が弱いために、
後の組立工程において前記電極がはがれるため歩留りが
著しく低下することが、しばしば生じる。この原因は、
封管拡散中に露出したエピタキシャル層６の表面が拡散
層 −一スにより汚染し、何らかの薄膜層が形成されて
いるためと考えられる。薄膜層の厚さは数１００Ａ′以
下である。この薄膜層は、耐薬品性が高い。However, if metallization is performed on the surface of the epitaxial layer in which zinc (Zn) is diffused without any treatment, the contact resistance of the ohmic electrode becomes extremely high, resulting in a device with a high forward voltage, and the adhesion of the electrode 8 becomes poor. Because it is weak,
It often happens that the electrode peels off during the subsequent assembly process, resulting in a significant reduction in yield. The cause of this is
This is thought to be because the surface of the epitaxial layer 6 exposed during the sealed tube diffusion was contaminated by the diffusion layer and some kind of thin film layer was formed. The thickness of the thin film layer is several hundred A' or less. This thin film layer has high chemical resistance.
このような薄膜層を除去するための方法としては、従来
化学エツチングが行われていた。しかしこの方法には次
のような欠点がある。薄ｊ漢層の組成、厚さは不均一で
あり、ピンホールも多くあるために、薄膜層のエツチン
グが１ｆｆＬむ段階で、結晶（エピタキシャル層）表面
が露出すると、薄膜層ノ方カ耐エツチング性に強いため
に、結晶の方が速くエツチングされてしまい。結晶の表
面に凹凸が生じ拡散層がエツチングされてしまうことに
なる。この凹凸の量は多いときには３〜５μＩｎになる
ことがある。Chemical etching has conventionally been used as a method for removing such thin film layers. However, this method has the following drawbacks. The composition and thickness of the thin layer are non-uniform, and there are many pinholes, so if the crystal (epitaxial layer) surface is exposed at the stage where the thin film layer is etched by 1ffL, the etching resistance of the thin film layer will deteriorate. Crystals are more resistant to corrosion, so they are etched faster. This results in unevenness on the surface of the crystal and etching of the diffusion layer. When the amount of this unevenness is large, it may be 3 to 5 μIn.
（発明の目的）
本発明の目的は、封管法により亜鉛（Ｚ ｎ ） を
拡散するときに化合物半導体の結晶表面に生じる薄膜層
を容易に取除き良好なメクラゼーションを行うことによ
り、信頼度の高い製品を歩留りよく製造する事のできる
新規な製造法を提供することにある。(Objective of the Invention) The object of the present invention is to easily remove the thin film layer that occurs on the crystal surface of a compound semiconductor when diffusing zinc (Zn) using the sealed tube method, thereby improving reliability. The purpose of the present invention is to provide a new manufacturing method that can produce products with high yields.
（発明の内容〕
本発明の内容を実施例について説明する。ただし、本発
明とは直接関係しない工程については省略する。(Contents of the Invention) The contents of the present invention will be explained with reference to Examples.However, steps not directly related to the present invention will be omitted.
第２図は、本発明の半導体表面の処理法を示す概念図で
ある。FIG. 2 is a conceptual diagram showing the semiconductor surface treatment method of the present invention.
亜鉛（Ｚｎ）の拡散を行った後、プラズマエヅチング装
置を用い酸素プラズマ中に約１０分さらす。After zinc (Zn) is diffused, it is exposed to oxygen plasma for about 10 minutes using a plasma etching device.
このとき例えば真空度は５ ｔｏｒｒ で高周波出力
は１００Ｗ である。この後、メタライゼーションを
行う。このような酸素プラズマ処理により薄膜層が除か
れる。酸素プラズマを行った試料では良好なオーミック
コンタクトが得られ、電極のはがれも生じなかった。酸
素プラズマ処理によるため、結晶表面はエツチングされ
ないという利点がある。At this time, for example, the degree of vacuum is 5 torr and the high frequency output is 100W. After this, metallization is performed. Such oxygen plasma treatment removes the thin film layer. Good ohmic contact was obtained with the sample treated with oxygen plasma, and no electrode peeling occurred. Since oxygen plasma treatment is used, there is an advantage that the crystal surface is not etched.
なお本発明では、５ｉｎ２膜の窓孔から拡散を行い、そ
の後酸素プラズマ処理を行ったが、Ｓｉｎ。In the present invention, diffusion was performed through the window hole of the 5in2 film, and then oxygen plasma treatment was performed.
膜のあるなしは、本特許とは無関係である。The presence or absence of a membrane is irrelevant to this patent.
（発明の効果）
本発明によれば、封管法による亜鉛拡散工程中に生成し
た結晶表面の薄膜層を均一に除くことができ、しかも、
結晶表面をエツチングすることはないので、素子の構造
を破壊することはない。(Effects of the Invention) According to the present invention, it is possible to uniformly remove the thin film layer formed on the crystal surface during the zinc diffusion process using the sealed tube method, and further,
Since the crystal surface is not etched, the structure of the device is not destroyed.
本発明により、直列抵抗が低くて信頼度の高し）発光ダ
イオードが実現される。According to the present invention, a light emitting diode (with low series resistance and high reliability) is realized.
本発明は、いわゆる半導体レーザやその他の化合物半導
体素子の製造において同様の効果が得られることは言う
までもない。材料はＧａＡｌＡｓに限ることなく １ｎ
ＧａＡｓＰ、ＩｎＧａＡｓ、ＩｎＰその細化合物半導体
であっても同様の効果が得られることは当然である。It goes without saying that the present invention can provide similar effects in the manufacture of so-called semiconductor lasers and other compound semiconductor devices. The material is not limited to GaAlAs.
It goes without saying that similar effects can be obtained with fine compound semiconductors such as GaAsP, InGaAs, and InP.
第１図は高輝度発光ダイオードの断面構造概念を示す図
、第２図は本発明による製造法を示す図である。
図中１はｎ型ＧａＡｓ基板
２はｎ型Ｇａ、 、ＡｌｘＡｓ エピタキシャル層３
はＰ型Ｇａ、 、ＡｌｙＡｓエピクキシャル層４はＰ
型Ｇａ、□ｘＡ Ｉ ＸＡＳエピクキシャル層５は
Ｐ型Ｇｅｌ、−７ＡｌｚＡｓ エビクキシャル層６は
５１０２膜
７は Ｚｎ拡散層（ｐ ）
８．９は 電極金属膜
１０は 光取出し窓
］１は 薄膜層である。FIG. 1 is a diagram showing a conceptual cross-sectional structure of a high-brightness light emitting diode, and FIG. 2 is a diagram showing a manufacturing method according to the present invention. In the figure, 1 is an n-type GaAs substrate 2 is an n-type Ga, AlxAs epitaxial layer 3
is P-type Ga, , AlyAs epitaxial layer 4 is P-type
The type Ga, □xA I XAS epitaxial layer 5 is
P-type Gel, -7AlzAs evixical layer 6 is
5102 film 7 is a Zn diffusion layer (p) 8.9 is an electrode metal film 10 is a light extraction window] 1 is a thin film layer.
Claims (1)
導体の表面に電極を形成する工程において、先に前記結
晶表面を酸素プラズマにより清浄化することを特徴とす
る半導体装置の製造方法。l) Manufacturing a semiconductor device characterized in that in the step of forming an electrode on the surface of an m-v group compound semiconductor in which zinc is diffused by a sealed tube method, the crystal surface is first cleaned with oxygen plasma. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9920083A JPS59222927A (en) | 1983-06-02 | 1983-06-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9920083A JPS59222927A (en) | 1983-06-02 | 1983-06-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59222927A true JPS59222927A (en) | 1984-12-14 |
Family
ID=14241004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9920083A Pending JPS59222927A (en) | 1983-06-02 | 1983-06-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59222927A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62252134A (en) * | 1986-04-24 | 1987-11-02 | Matsushita Electric Ind Co Ltd | Manufacture of compound semiconductor device |
-
1983
- 1983-06-02 JP JP9920083A patent/JPS59222927A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62252134A (en) * | 1986-04-24 | 1987-11-02 | Matsushita Electric Ind Co Ltd | Manufacture of compound semiconductor device |
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