JPS59216254A - Interruption level control system - Google Patents

Abstract

PURPOSE:To generate an interruption of an interruption level whose priority order is different to a processing device by making a time of a pulse width variable against an input of one line of an external interruption request signal line. CONSTITUTION:When an external interruption request signal 1 is varied to an L level from an H level, one shot multivibrators 5, 6 and 7 are triggered at the same time. In case an interruption is generated in an interruption level one line 2 whose interruption priority order is the highest, a pulse whose pulse width is under 10mus is sent out to the external interruption request signal 1. As a result, an FF 9 is set, and when an interruption mask signal 8 is ''1'', an interruption of an interruption level 1 is generated to a processing device. Also, in case the pulse width of the external interruption request signal 1 is 10mus-100mus, an interruption is generated in an interruption level two line 3. Also, a pulse whose pulse width is 100mum-1ms is sent out to an interruption level three line 4 of the least significant priority order.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to interrupt level control for electronic computers.

[Background of the invention]

Conventionally, when there are a plurality of levels of interrupt input to a processing device from the outside, a plurality of external interrupt request signals are assigned to each interrupter level according to the level of each interrupter. In addition, since the interrupt level for an interrupt from each external device to the processing unit was uniquely determined by that device, the interrupt from each device was However, this means of recognizing the state of the interrupt has the disadvantage that the status etc. must be analyzed after the interrupt occurs.

Furthermore, in order to generate an interrupt by changing the interrupt level, a plurality of external interrupt request lines are required from the external device depending on the interrupt state, resulting in an increase in hardware.

[Purpose of the invention]

An object of the present invention is to provide a control method that allows a single interrupt request line from the outside to set different interrupt levels to a processing device without changing the interrupt input circuit. [Summary of the Invention] The present invention generates an interrupt every time a trigger pulse is generated in an external interrupt input. The interrupt level is assigned in accordance with the pulse width of the pulse output to the line.

[Embodiments of the invention]

An embodiment of the present invention will be described with reference to the drawings.

The figure shows an example of generating an interrupt signal to the processing device in response to external interrupt request signal 1 at one of three levels: interrupt level 1, line 2, interrupt level 2, line 5, and interrupt level 624, line 5. It is.

First, when external interrupt request signal 1 changes from H level to L level, a one-shot signal with a timer value of 10 μs is generated.
A one-shot multivibrator 6 with a timer value of 100 μs and a one-shot multivibrator 7 with a timer value of i ms are each simultaneously triggered. Here, if you want to generate an interrupt on Itl interrupt level 1 line 2, which has the highest interrupt priority, the Noculus width of external interrupt request signal 1 is 10.
When a pulse of less than μs is sent, the interrupt level 1 line 2 free knob flop 9 is set to 1 after 10 μs.
If the interrupt mask signal 8 is V"1", an interrupt of interrupt level 10 is generated to the processing device.

In addition, if the external interrupt request signal has a width of 10 nodes or more than 10 μs but less than 100 μs, the interrupt level 2 line 6
An interrupt occurs. When generating an interrupt at interrupt level 6 line 4, which has the lowest interrupt priority, do so by sending a pulse with a pulse width of 100 μs or more but less than 1 ms, and for inputs with a pulse width of 1 ms or more. There are many circuits that often generate interrupts.

In this way, by varying the time of the pulse width for one line of input of the external interrupt request signal 1, it is possible to generate interrupts of different priority levels to the processing device.

It should be noted that generating interrupt signals with different pulse widths in externally connected devices can be achieved, for example, by providing one-shot, multi-function, and e-break signals with different timer values for each device.

〔Effect of the invention〕

The present invention has the advantage of being able to reduce the number of external interrupt request lines and generate interrupts at a plurality of interrupt levels with one line, and has great industrial value.

[Brief explanation of drawings]

The figure is an interrupt input circuit diagram of an embodiment of the present invention. 1...External interrupt request signal, double interrupt level 1 line, 6300 interrupt level 2 lines, 4...Interrupt level 6 lines, 5...10μsr7 shot multivibrator 6...100μ317 shot multivibrator 7.・・1mSmS pumped multivibrator,
8...Interrupt mask signal, 9...Interrupt misobel 1 flinopfuroz, 10...
Interrupt level 2 flip-flop, 11... Interrupt level 5 flip-flop. Representative Patent Attorney Akio Takahashi

Claims (1)

[Claims] 1. In a circuit that generates an interrupt to the processing device in response to an interrupt request from the externally connected device between a processing device having multiple interrupt levels and an externally connected device, the width of the pulse output to the interrupt request line is Depending on the type, the interrupt level is set as many times as the number of pulse width types.
An interrupt level control method characterized by being able to vary the interrupt level.