JPH0525406B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital logic circuit having means for making a majority decision on n (n is a natural number) bits of a serial pulse train.

〔overview〕

The present invention provides a digital logic circuit having means for making a majority decision on n bits of a serial pulse train, comprising: a delay circuit for receiving a serial pulse train;
A control circuit that compares the output of this delay circuit with a series pulse train and outputs a predetermined control signal, an up-down counter that is controlled by the control signal from this control circuit, and determines the output result of this up-down counter. The circuit is simplified so that even if the number of bits of the serial pulse train for majority decision increases, the increase in circuit scale is small.

[Conventional technology]

Conventionally, this type of digital logic circuit includes a conversion circuit 106 that converts a serial pulse train 1 into a plurality of digital signals 9, and a plurality of digital signals 9 outputted from the conversion circuit 106, as shown in FIG. A majority decision circuit 10 that makes a majority decision based on
It was composed of 2a. Majority decision circuit 102
a is composed of an arithmetic circuit 107 and a determination circuit 105a. In addition, the arithmetic circuit 107 is composed of a full adder and a half adder [a problem to be solved by the invention] In the conventional digital logic circuit described above, the circuit scale becomes extremely large as the number of bits of the serial pulse train increases. The disadvantage is that it gets bigger.

This will be explained below using a specific example shown in FIG.
FIG. 4 is a circuit diagram of a digital logic circuit having a 13-bit majority decision means. In FIG. 4, the conversion circuit 106 is constructed by arranging 13 D-type flip-flops in series. The serial pulse train 1 is input to the conversion circuit 106, and the D-type flip-flop 13 in the conversion circuit 106 when the clock signal 4a is input.
The output signals 9 of 13 are input to the majority decision circuit 102a, and the 13 signals are determined to be logic "1" or logic "0".
A determination result output 6 is outputted from which a majority determination is made. Here, the majority decision circuit 102a:
Judgment circuit 105a, full adder 30, and half adder 40
It is configured by an arithmetic circuit 107 consisting of a combination of. The majority decision circuit 102a makes a majority decision on the number of logic "1" and logic "0" in the 13-bit serial pulse train, and the arithmetic circuit 107 has seven full adders 30 and 14 half adders 40. Consisting of
The circuit scale is increasing. On the other hand, when the serial pulse train for majority decision is 5 bits, the arithmetic circuit includes one full adder 30 and six half adders 40.

An object of the present invention is to provide a digital logic circuit having a majority decision means with a simple circuit configuration, which requires only a small increase in circuit scale even when the number of bits of a series pulse train to be decided by majority increases, by eliminating the above-mentioned drawbacks. It is about providing.

[Means for solving problems]

The present invention provides a digital logic circuit having means for making a majority decision on n (n is a natural number) bits of a serial pulse train, which includes a delay circuit 101 that receives the serial pulse train, and compares the output of this delay circuit with the serial pulse train. A control circuit 103 that outputs a control signal that commands a counting operation in the case of a mismatch.
, an up-down counter 104 that counts up or down according to the logic of the series pulse train based on the control signal, and a majority decision based on the magnitude of the counted value of the up-down counter and a predetermined value that is compared with a predetermined value. It is characterized by including a determination circuit 105 that outputs a result.

[Effect]

In the present invention, a control circuit compares the output of a delay circuit in which a serial pulse train of n bits is delayed by n bits with the input serial pulse train, and operates an up-down counter only when the logics of both do not match. Outputs a control signal. The up-down counter operates according to this control signal. For example, if the serial pulse train is a logic "1" and the output of the delay circuit is a logic "0", the up-down counter will count up. 1", it counts down, and if both logics are the same, it is a no-count, and the respective outputs are output to the determination circuit. The decision circuit obtains a result by performing majority decision on this output.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Delay circuit 101 receives serial pulse train 1 and outputs output signal 2 in response to clock signal 4. The control circuit 103 receives the serial pulse train 1 and the output signal 2 of the delay circuit, and outputs a control signal 3 for operating the up-down counter 104 only when the logics of both signals do not match. Up-down counter 104 is controlled by control signal 3 and counts by clock signal 4. Judgment circuit 10
5 receives the output signal 5 of the up-down counter 104, makes a majority decision, and outputs the decision result 6. In FIG. 1, the control circuit 103, up/down counter 104, and determination circuit 105 constitute a majority circuit 102.

The feature of the present invention is that in FIG.
01, control circuit 103, up/down counter 1
04 and a determination circuit 105 are provided.

FIG. 2 is a circuit diagram showing a specific example of one embodiment of the present invention, and is a circuit having a 13-bit majority decision means. The delay circuit 101 is composed of 14 D-type flip-flops. However, the delay circuit 10
1 and the up-down counter 104 are assumed to have been initialized by the reset signal 7.
A serial pulse train 1 is input to a delay circuit 101, and a D-type flip-flop is shifted by a clock signal 4. At this time, the output signal 2 of the delay circuit 101 when the clock signal 4 is input, and the serial pulse 8
are compared and determined by the control circuit 103, and the output 3 of the control circuit 103, which consists of an exclusive OR circuit, outputs a binary up flip-flop consisting of 204 T-type flip-flops, 7 AND circuits, and 3 OR circuits. Controls down counter 104. At this time, according to the control signal 3 from the control circuit 103, the up-down counter 104 counts up if the serial pulse 8 is logic "1" and the output signal 2 of the delay circuit 101 is logic "0". If it is "0" and the output 2 of the delay circuit 101 is a logic "1", the count is down; if the logic of the serial pulse 8 and the output signal 2 of the delay circuit 101 match, the count is not counted. A determination circuit 105 consisting of a D-type flip-flop 10, one AND circuit, and one OR circuit
receives the output signal 5 of the up-down counter 104 and makes a majority decision.

As a result, if the number of logic "1"s in the serial pulse train 1 input to the delay circuit 101 becomes 7 or more, the number of logic "1"s becomes greater than the number of logic "0"s, and the determination circuit 105 A determination result output 6 is output.

Comparing the number of parts between the circuit of FIG. 2 according to the present invention and the conventional circuit of FIG. 4 (both 13-bit pulse train), they are almost the same except for the parts corresponding to the arithmetic circuit of FIG. 4. The arithmetic circuit section conventionally required 7 full adders and 14 half adders, but the circuit of the present invention requires 4 T-type flip-flops, 7 AND circuits, 3 OR circuits, and exclusive It has a simple circuit configuration with one target OR circuit.

In this embodiment, the case where the number of logical "1"s for 13 bits is determined is explained.
Similar implementations can be made for logic 0's and other numbers of bits.

〔Effect of the invention〕

As explained above, by using a control circuit, an up-down counter, and a decision circuit in the majority decision circuit, the present invention has a larger circuit size compared to the conventional circuit that uses a half adder and a full adder in the arithmetic circuit. This has the effect of making it smaller. In particular, the effect becomes greater when the number of bits in the serial pulse train subjected to majority decision is large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing a specific example thereof. FIG. 3 is a block diagram showing a conventional example. FIG. 4 is a circuit diagram showing a specific example thereof. 1...Series pulse train, 2, 5...Output signal, 3...Control signal, 4, 4a...Clock signal, 6...Judgment result output, 7...Reset signal, 8...Series pulse, 9...
Digital signal, 10...D flip-flop,
20...T-type flip-flop, 30...full adder,
40...half adder, 101...delay circuit, 102,1
02a...Majority decision circuit, 103...Control circuit, 1
04...Up-down counter, 105, 105a
...judgment circuit, 106... conversion circuit, 107... arithmetic circuit.

Claims (1)

[Claims] 1. In a digital logic circuit having means for making a majority decision on n (n is a natural number) bits of a serial pulse train, a delay circuit 101 that receives the serial pulse train.
a control circuit 103 that compares the output of the delay circuit with the series pulse train and outputs a control signal for instructing a counting operation if they do not match; A digital logic circuit characterized in that it includes an up-down counter 104 that performs up-down operation, and a determination circuit 105 that compares the count value of this up-down counter with a predetermined value and outputs a majority decision result according to the magnitude thereof. .