JPH02304636A - Watch dog timer circuit - Google Patents

Abstract

PURPOSE:To improve the detecting capacity for the runaway of a program by constituting this circuit so that a first and a second FFs output in good order a trigger signal from a microprocessor to a first and a second timers, and the trigger signal to each timer is inhibited, when this order is not observed. CONSTITUTION:An FF 5 selects one of a first timer 1A and a second timer 2 by an address signal 30 from a microprocessor. When the timer 1A is selected and a trigger is outputted at a rise of an output Q of the FF 5, the output Q of the timer 1A becomes H for a prescribed period. Subsequently, even if the timer 1A is selected again and the trigger is outputted, a trigger signal 10 is not outputted to the timer 1A. That is, a retrigger to the timer 1A cannot be executed unless a trigger signal is outputted to a second trigger 2. In such a way, unless the trigger is applied successively and alternately to the timer 1A and the timer 2, the retrigger is not executed. Accordingly, the repeated trigger to the same timer becomes invalid, and the detecting capacity for the runaway of a program is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a watchdog timer circuit for detecting program runaway in microprocessor application equipment and the like.

[Conventional technology]

Figure 3 is a block connection diagram showing a watchdog timer circuit for detecting program runaway in conventional microprocessor-applied equipment. The stable timer IO is a trigger signal output from a microprocessor (not shown) to timer 1, and 20 is a non-maskable interrupt request signal (hereinafter referred to as NMI signal) input to the microprocessor.

Next, the operation will be explained. In the microprocessor program, at intervals shorter than the fixed period of timer 1,
By inserting a command to issue the trigger signal 10 to timer 1, when the program is running normally, the output of timer 1 becomes "L" and the NMI signal 20 to the microprocessor is It is always “°L°゛”.

On the other hand, if the microprocessor program goes out of control, the trigger signal 10 will not be output normally, and the timer 1 will
The output becomes "L". In addition to this, NMI signal 20
becomes “H”. Therefore, an interrupt signal is sent to the microprocessor, allowing the microprocessor to know that the program has run out of control.

[Problem to be solved by the invention]

The conventional watchdog timer circuit is configured as described above, so depending on how the program runs out of control,
For example, if a runaway occurs in which the program address that outputs the trigger signal 10 is looped, the trigger signal 10 will be constantly output, and there is a possibility that the watchdog timer will not work properly.

This invention was made to solve the above-mentioned problems, and it provides a watch that operates normally and can reliably detect program runaway even when a runaway occurs such as looping the program address that outputs the trigger signal. The purpose is to obtain a dog timer circuit.

[Means to solve the problem]

The watchdog timer circuit according to the present invention includes timer selection means for selecting a timer to operate based on an address signal from a microprocessor, and the timer selection means selects either the first timer or the second timer. The output of the first timer or the second timer triggers the first flip-flop or the second flip-flop, respectively, and the output of the first timer or the second timer is The above trigger is prohibited.

[For production]

The first flip-flop and the second flip-flop in this invention are configured to output the trigger signal from the microprocessor to the first timer and the second timer in order. To further ensure the detection of program runaway by not outputting a trigger signal to.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, IA is a first timer whose output is stable for a certain period of time when a trigger signal is input, 2 is a second timer similar to the first timer IA, and 3 is the first timer I.
A first flip-flop 4 latches the input at the rising edge of the output Q of A, and 4 is a second flip-flop similar to this first flip-flop 3; Latch the button. Reference numeral 5 denotes a flip-flop as a timer selection means having the same configuration as each of the flip-flops 3 and 4 above, 6.7 a three-man-powered AND gate, and 8 a two-man-powered AND gate that receives the output of each timer IA and 2. In the NOR gate, 10 is a trigger signal output from a microprocessor (not shown) to a watchdog timer, 20 is a non-maskable interrupt request signal (NMI signal) to the microprocessor, and 30 is an address signal from the microprocessor.

Next, the operation will be explained. Flip-flop 5 is the first
This determines which of the second timer IA and the second timer 2 to select, and is specified by the address signal 30 from the microprocessor.

Now, when the first timer IA is selected and triggered at the rising edge of the output Q of this flip-flop 5, this first timer IA is triggered.
The output Q of timer IA becomes "H'" for a certain period of time. Next, even if the first timer IA is selected again and a trigger is issued, the trigger signal 10 is not output to the first timer IA, as shown in FIG. In other words, this first timer LA
Re-triggering cannot be performed unless a trigger signal is output to the second timer 2. In this way, the first
Unless the timer IA and the second timer 2 are sequentially and alternately triggered, they will not be retriggered. Therefore, repeated triggering of the same timer becomes invalid, and the ability to detect program runaway is improved.

Note that in the above embodiment, two timers, the first timer LA and the second timer 2, are used, but the number of timers can be increased as desired, and the program speed can be increased in proportion to the number of timers. The ability to detect runaway behavior can be improved.

〔Effect of the invention〕

As described above, according to the present invention, the first timer and the second timer are used and configured to trigger them sequentially, so if this order is not satisfied, a trigger signal is output to each of the above-mentioned timers. This has the effect of further improving the ability to detect program runaway.

[Brief explanation of drawings]

FIG. 1 is a block connection diagram showing a watchdog timer circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing signals of each part of the block shown in FIG. 1, and FIG. 3 is a conventional watchdog timer circuit. It is a block connection diagram showing. IA is a first timer, 2 is a second timer, 3 is a first flip-flop, 4 is a second flip-flop, 5 is a timer selection means (flip-flop), IO is a trigger signal from the microprocessor, 30 is the address signal from the microprocessor. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Decoration 1 Diagram IA: Sho 1's Timer 2: Sho 2's Timer 3: Man 1fi Furi...Buflo Noah. 4: 2nd Furi Nfuro Noah. 5: Thailand? Ceremony (Call for the King)
Furi 1o; To 1) Power'i name number 30: Ato°shi sui name number

Claims (1)

[Claims] a timer selection means for selecting a timer based on an address signal from the microprocessor; a first timer and a second timer selected by the timer selection means and triggered by a trigger signal from the microprocessor; a first flip-flop and a second flip-flop that are triggered in response to the output of the first timer or the second timer, respectively, and output a prohibition signal that prohibits input of the trigger signal to the first timer or the second timer; A watchdog timer circuit with two flip-flops.