JPS59214386A - Ghost eliminating device - Google Patents

Abstract

PURPOSE:To perform excellent weighting through simple constitution by generating a pilot pulse at a position corresponding to right before a ghost detection period and inputting it to a delay circuit for a demultiplexer for a preceding and a succeeding ghost, and detecting said pulse in passing signals and controlling switching operation. CONSTITUTION:The input of a synchronizing separator circuit 14 is connected in front of the delay circuit 5 for correcting the preceding ghost. A masking pulses is fitched from a standard waveform forming circuit 15 and differentiated by a circuit 71 to obtain a pilot pulse corresponding to a leading edge, thereby supplying the pulse to an adder 72 in front of a demultiplexer 19. Further, the terminal tap signal of a demultiplexer 20 is supplied to a pilot pulse detecting circuit 73, whose detection output is supplied to a timing generating circuit 74. The circuit 74 is supplied with a t=0 pulse and the masking pulse from the standard waveform forming circuit 15 and generates a timing signal while giving the time difference which is equal to the time difference between the leading edge of the masking pulse and behind the t=0 pulse. Thus, pulses are generated to turn on switches 211-22m.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a ghost removal device for removing ghosts, for example in a video signal stage.

Background technology and its problems Conventionally, the following ghost removal devices have been proposed.

For example, in Figure 1, a signal from an antenna (11) is supplied to a video detection circuit (4) through a tuner (2) and a video intermediate frequency amplifier (3), and a video signal is detected. It is supplied to the ζ combiner (6) via a delay circuit (5) corresponding to the ghost removal period, and a canceling signal simulating a ghost from a transversal filter, which will be described later, is supplied to each combiner (6). A deghosted video signal is taken out from the synthesizer (6) at an output terminal (7).

More video detection part II! The video signal obtained from 8 (41) is connected to a delay circuit (8) that constitutes a transversal filter.
). This delay circuit (8) has a plurality of stages (n) of delay elements each having a sampling period (for example, 10 (ns)) connected to provide a delay time equal to the preceding ghost removal period. n taps are derived. The signals from each tap are weighted by a circuit (91) composed of a multiplier,
(92) ... is supplied to (9n).

Further, the signal from the end of the delay circuit (8) is supplied to the terminal (10f) of the mode switch 00), and the signal from the end of the delay circuit (8) is also supplied to the terminal (10f) of the mode switch 00), and the signal from the end of the delay circuit (8) is
The output signal of 6) is supplied to the terminal (10b) of switch 00). The signal from this switch 001 is transmitted to the delay circuit (
11). In this delay circuit (11), a plurality of stages (m pieces) of delay elements each having a sampling period as a unit are connected to provide a delay time equal to the post-ghost removal period, and rit taps are derived from between each stage. It is something that The signals from each tap are connected to circuits (121) and (122) each consisting of a multiplier.
...(12m).

Also, the video signal from the synthesizer (6) is sent to the subtraction circuit (13).
supplied to Furthermore, the video signal from the delay circuit (5) is supplied to the synchronization separation circuit III (14), and the separated vertical synchronization signal is supplied to the standard waveform forming circuit (15) and the low-pass filter (16) to produce the "CIp direct synchronization signal". leading edge V
A standard waveform approximating the step waveform of E is formed. This standard waveform is supplied to a subtraction circuit (13).

The signal from this subtraction circuit (13) is supplied to a differentiation circuit (17) to detect ghosts.

Here, as a signal for ghost detection and measurement, a signal that is included in a standard television signal and is not affected by an unpacking signal as long as possible, such as a vertical synchronization signal, is used. That is, as shown in FIG. 2, the leading edge VE of the vertical synchronizing signal and ±+H (H is a horizontal period) before and after the leading edge VE are not influenced by other signals b3. Therefore, the above-mentioned standard waveform is subtracted from the signal of this period, and this subtracted signal is differentiated to detect the weighting coefficient.

For example, the phase difference ψ(−ω.τ
, however, ωC is the image 1 repulsion angle frequency at the quotient frequency stage) is 4
When a 5° ghost is included, a video signal with a waveform like a blur appears in fA3 diagram A.

On the other hand, by differentiating this signal and inverting the polarity, a ghost detection signal with a Bozu differential waveform is obtained as shown in Figure 3B, and this differential waveform can be approximately regarded as an impulse response of a ghost. .

The differential waveform ghost detection signal appearing from the differentiating circuit (17) is supplied to demultiplexers (19) and (20) connected in series via an amplifier (18).

These demultiplexers (19) and (20) are connected in multiple stages of delay elements each having a sampling period as a unit, similar to the delay circuits (81 and (11)), and have m and n taps connected between each stage. is derived.The output of each tap is the number of switch times (2h).
, (212) ... (2In), (22z
), (222) ... (22m).

Also, the vertical synchronization signal from the synchronization separation circuit (14) is supplied to the gate pulse generator (23). A corresponding gate pulse is formed at the end of the 1 (1iij edge VB to +I of the plane synchronous signal) section, and this pulse turns on the switch circuits (21r) to (22m).

Signals from these switch circuits (211) to (22m) are sent to analog accumulators (241) and (242), respectively.
... (24n), (25t), (252)
... (25m). Signals from these analog accumulators (241) to (25m) are used for car-mounted reno times vR (9t) to (9n), (12z) to (12m), respectively.
m).

These vehicles are equipped with circuits (91) to (9o), (12z
) to (12m) are added in an adder circuit (26) to form a cancellation signal. This cancellation signal is then supplied to the combiner (6).

As mentioned above, the delay circuit pts+, (11), the weighting circuits (91) to (9n), (121) to (12m), and the adder circuit (26) are configured with ζ transversal filters, and ghosts are eliminated. removed. In this case, after detecting the distortion of the waveform between the leading edge of a certain vertical synchronization signal and the area before and after it and determining the marketization coefficient, if ghosts remain unerased, perform the above-mentioned detection. Analog accumulator (24+) ~
(25m) is provided.

Note that by switching the mode switch 00), the rear ghost removal can be switched to the feedforward mode and the foot hack mode.

Furthermore, Fig. 4 shows the case where ghosts are removed using a manually added transversal filter.
Parts that are equivalent to those in the figures will be designated by the same reference numerals and detailed explanations will be omitted.

In the figure, the video signal from the video detection circuit (4) is supplied to the circuits (91) to (9n), and the signals from the circuits (91) to (9n) are weighted to the delay circuits (91) to (9n), respectively. 8'). This delay circuit (8
') is one in which n delay elements each having a sampling period as a unit are connected, and an input terminal of n (lfil) is provided between each stage.

In addition, the signals on the input and output sides of the synthesizer (6) are connected to the terminals (10f') and (10f') of the mode switch (10').
b'). The signal from this switch (1, 0') is supplied to the weighted circuit (121) to (12m), and the signal from this numbered circuit (121) to (12m) is supplied to the delay circuit (121) to (12m), respectively. 11'). This delay circuit (11') has m delay elements connected in units of sampling periods, and input terminals rn and fllll provided between each stage.

The signals taken out from the respective terminals of these delay circuits (8') and (11') are added in an adder circuit (26') to form a "ζ cancellation signal. Then, this ζ cancellation signal is synthesized. (6).

In this circuit, ghosts are also removed from ζ in the same manner as in the circuit using the output addition type transversal filter described above.

Roughly speaking, in the above Im, without providing the °ζ differentiation circuit (17), the difference between the outputs of adjacent bits of the demultiplexers (19) and (20) is used to obtain the ゛C difference output, and with this difference output, Weighting can also be performed.

There are also demultiplexers (19), (20) and delay circuits +81. (11) is made common, and when the car number is set, the car signal is supplied to the delay circuit, and this is recorded in the memory element. It is also possible to use this stored signal for subsequent market determination.

In this way ghosts can be eliminated, for example in the video signal stage.

By the way, in such a ghost removal device, the timing of the formation of the semi-waveform and the switching of the switch circuits (21z) to (22m) is set, for example, to the leading edge of the vertical synchronization signal as the reference time. Detection of this reference time requires extremely high accuracy, and experimentally
It is said that accuracy within n Sec is required.

However, in the case of conventional sync separation circuits, since the circuit includes a low-pass filter, high-frequency information is lost, and the vertical and vertical lines separated in this way become dull. Detecting the reference time from the synchronization signal may cause a time delay.

On the other hand, ζ, e.g. +l including the leading edge of the vertical synchronization signal]
It has been proposed to form a masking pulse of the order of duration and to directly detect the leading edge transit using this masking pulse and the video signal.

However, with this method, if the formation position of the masking pulse is incorrect due to the influence of noise etc., another transit may be detected and the ζ reference time may be significantly deviated. This is a problem because it is often used in poor S/H conditions such as.

By the way, since the above-mentioned masking pulse only needs to be in the +H period including the leading edge of the vertical synchronization signal, very high precision is not required for forming this masking pulse. Also, 1ft of synchronization including the conventional low-pass filter! Since the circuit includes a low-pass filter, noise is suppressed and there is less risk of malfunction due to noise.

Therefore, the inventor of the present application previously proposed the following circuit. In FIG. 5, (31) is an input terminal to which a video signal is supplied, and the signal from this terminal (31) is input to the comparator (
32) and a low-pass filter (33), and the signal from this low-pass filter (33) (Fig. 6A) is supplied to a vertical synchronization separation circuit (34) consisting of a low-pass filter. This separation circuit (3
The vertical synchronizing signal (FIG. 6B) separated in step 4) is supplied to a masking pulse forming circuit (35), and is converted into a triangular wave (
FIG. 6C) is formed, and this and the group f! The potential (dashed line) forms a masking pulse (FIG. 6D) corresponding to the +14 period including the leading edge of the vertical synchronization signal. This masking pulse is applied to the control terminal of the comparator (36). Further, a signal from the terminal (31) is supplied to the comparator (36) through the amplifier (37). And this comparator (36)
For example, each time a falling edge of the signal is detected, the leading edge of the vertical synchronization signal (Fig. 6 E), which is the reference time, is detected, and the 1=0 pulse (Fig. 6 F) which is the inversion of this is detected at the output terminal. It is taken out at (38).

Alternatively, in Fig. 7, the signal from the input terminal (31) passes through the clamping capacitor (4) to the transistor (42) and resistor (43) that constitute the bias circuit.
, is supplied to the connection midpoint between the resistor (43) and the constant current source (44) in the series circuit of the constant current source (44). Furthermore, the signal at the middle point of this connection is different! It is supplied to the base of one transistor (45) constituting the 1ifJ amplifier. Further, a resistor (48) and a constant current source (49) of a series circuit consisting of a transistor (47), a resistor (48), and a constant current source (49) constituting a bias circuit are connected to the base of the other transistor (46).
9) is supplied with voltage from the connection midpoint. Then, the signal current flowing through the collector of the C transistor (46) is taken out through the current mirror circuit (50).

Furthermore, this signal is supplied to a low-pass filter (52) and a buffer amplifier (53) through a switch (51), and is also supplied to a low-pass filter (54) through a switch (54).
55) and a buffer amplifier (56). Signals from the buffer amplifiers (53) and (56) are added by resistors (57) and (5B) and supplied to a °C comparator (59). Also, the current mirror times 11δ(
The signal from 50) is fed to a comparator (59).

The signal from this comparator (59) is supplied to the D terminal of the 079717121 circuit (60), and at the same time its polarity is inverted and supplied to the clear terminal of the flip-flop circuit (60). Further, the masking pulse from the forming circuit (35) is supplied to the clock terminal of the frisobso amplifier circuit 1/8 (60), and the output of this frisobso amplifier circuit (60) is taken out to the output terminal (38).

In this circuit, a signal as shown in FIG. 8A, for example, is taken out from the current mirror circuit (50). In response to this signal, the switches (51) and (54) are turned on, for example, during the periods shown in FIG. 8B and C, respectively. As a result, potentials (El, Ex) corresponding to the levels of the pedestal and sync chip of the synchronizing signal are obtained from the buffer amplifiers (53) and (56), respectively. These potentials are added by resistors (57) and (5B). Here, if the resistance values of the resistors (57) and (5B) are R and R2, the potential F,3 obtained by addition becomes R1→-R2, and if R2<Rz. By supplying this potential E3 to the comparator (59), a signal as shown in the eighth diagram is taken out from the comparator (59). - Kamasking pulse forming circuit (35
) outputs a signal as shown in FIG. 8E. By supplying these signals to the flip-flop circuit (60), a signal as shown in FIG. 8F is output to the output terminal (3
8).

In this way, the reference time is detected.

However, the smell of these devices ζ, Sui Nochi (2b)
The gate pulse that turns on ~ (2in), (22t) ~ (22m), for example, at the leading edge of the vertical synchronization signal, uses a monostable multivib break, etc. The time point that is delayed by the time equivalent to the delay time of , there is a risk that new memories will not be carried out.

In order to further eliminate this drawback, the following method was devised. In FIG. 9, the signal from the synchronous separation circuit (14) is supplied to the pilot pulse generation circuit (61),
At a time corresponding to the leading edge of the vertical synchronization signal as shown in FIG. 10A, a pilot pulse signal as shown in FIG. 10B is formed. This signal is supplied to an adder (62) provided between the amplifier (18) and the demultiplexer (19), and is superimposed on the ghost detection signal. As a result, when the detection period To shown in FIG. 10C has elapsed, the above-mentioned pilot pulse signal is output to the final stage tap of the demultiplexer (19). This final stage signal is supplied to a pilot pulse detection circuit (63), and this detection signal is supplied to a waveform shaping circuit (64) to form a gate pulse signal.

And at this point, the demultiplexer (19)
, (20), the ghost detection signal of the ghost detection section is distributed, and by generating a repeat pulse signal at this point, the signal of each tap is sent to the analog accumulator (241). 〜(24n),(25
1) to (25m).

In this way, the C ghost detection signal is sent to the vehicle force memory analog accumulators (24z) to (24n) and (25r).
(25m).

However, in the case of this device, the detection of the pilot pulse is performed between the demultiplexers (19) and (20), so that the symmetrical viroft signal is transmitted to the output of the demultiplexers (19) and (20) (both at the output of one of them). , and it becomes impossible to perform correct weighting.

OBJECTS OF THE INVENTION The present invention is intended to address these points and to achieve good weighting with a simple configuration.

Summary of the Invention The present invention provides a leading ghost signal delay circuit, a trailing ghost signal delay circuit, a weighting circuit connected to each tap of the leading and trailing ghost signal delay circuits, and a leading ghost demultiplexer. A transversal circuit having a delay circuit for a rear ghost demultiplexer, a delay circuit for a rear ghost demultiplexer, each tap of the delay circuit for these demultiplexers, and a switching circuit and a memory circuit connected between the circuits. A filter is connected to the video signal source to create a ghost cancellation signal and a complementary signal having a delay time substantially equal to the preceding ghost signal delay circuit.
1: In the ghost removal apparatus, a delay circuit for correction is connected to the video signal source, and the output video signal from the correction delay circuit and the ghost cancellation signal are combined to remove the ζ ghost. The video signal from the previous stage of the delay circuit is supplied to a sync separation circuit, and based on the output from this sync separation circuit, a pilot pulse is formed at a position corresponding to just before the C ghost detection period to detect the trailing ghost and leading ghost. The ghost removal device is manually connected in series to a delay circuit for a multiplexer, detects the bi\' node pulse from the signal that has passed through both the demultiplexers, and controls opening and closing of the switching circuit based on this detection signal. According to this, good market acceptance can be achieved with a simple configuration.

Embodiments FIGS. 11 and 12 show cases in which the present invention is applied to an output addition type transversal filter and a manual addition type transversal filter, respectively.

In these figures, the input of the synchronization separation circuit (I4) is connected before the delay circuit (5) for correcting leading ghosts, that is, to the output of the video detection circuit (4). In addition, a masking pulse is extracted from the standard waveform forming circuit (15), and this masking pulse is supplied to a differentiating circuit (71) to obtain a pyro-nod pulse corresponding to the leading edge, and this pilot pulse is sent to an amplifier (18) and a demultiplexer ( 19). Furthermore, the signal at the terminal tap of the demultiplexer (20) is supplied to a pilot pulse detection circuit (73), and the detected pilot pulse is supplied to a timing generation circuit (74).

A standard waveform forming circuit (15) is added to this output circuit (74).
) and a masking pulse. The 1=0 pulse and masking noise are shown in Figure 5.
In FIG. 7, it is taken out from the terminals (38) and (39).

Then, in the timing generation circuit (74), timing is generated by setting a time difference after the (-〇 pulse) equal to the time difference between the leading edge of the masking pulse and the output pilot pulse. Forming a pulse, Sui Sochi (211) ~ (22m)
Turn on.

In addition, the standard waveform forming circuit (15) and low-pass filter (1
6), a compensation circuit (m-stable multi-noise break, etc.) (75) is provided which provides a delay equivalent to that of the delay circuit (5).

In this way, the C vehicle is detected, but according to this device, the pylon 1-RJ response is detected from the end of the demultiplexer for removing the preceding ghost, and from the middle as in the conventional method. Since it is not detected, there is no risk of adversely affecting the ghost removal operation.

Furthermore, the pilot pulse is obtained at the timing of the leading edge of the masking pulse <)less, and the leading edge of this masking pulse is set sufficiently before the preceding ghost removal range, so that the pilot pulse is sent to the demultiplexer (20).
The period from the output of ζ to the generation of the goo pulse is sufficiently long, and from this point of view as well, the insertion of the pilot pulse has no small effect on the ghost removal operation.

Further, FIG. 13 shows a specific example of the timing generator 1/8 (74). In the figure, C81, ) and (82) are counters, and these counters (81) and C8
2) is supplied with a clock pulse of, for example, four times the color carrier frequency from a clock oscillator (83) and counted.

Further, (84) is a terminal to which a masking pulse is supplied; the masking pulse from this terminal (84) is supplied to a counter (81), and counting is performed during the period of this pulse. In addition, (85) is a demultiplexer (20
), this signal is supplied to the pilot pulse detection circuit 1/& (73), and this detection signal is supplied to the counter (81) to stop counting. Ru. Further, (86) is a terminal to which the 1=0 pulse is supplied, and the L from this terminal (86)
=Q pulse is supplied to the counter (82) and counting is done during this pulse. These count values are supplied to a comparison circuit (87), and the point in time when the count value of the counter (82) reaches the value held in the counter (81) is detected. This detection signal is supplied to a monostable multi-by-break (88), a gate pulse is formed and taken out to a terminal (89). Furthermore, the 1=0 pulse from the i-child (+36>) is supplied to the monostable multi-by-break (91) via the inverter (90), and a reset pulse is formed and supplied to the counters (81) and (82).

In this circuit, for example, a human input signal as shown in FIG. 14A and a delay circuit as shown in FIG. When there is the output signal of old 5), the removal range of the leading ghost and trailing ghost in this case is as shown in the figure. On the other hand, masking pulses and 1=0 pulses are formed as shown in FIG. 14D. Furthermore, the differential pulse at the leading edge of the masking pulse becomes as shown in VI No. 1414, and this differential pulse (pilot pulse) is sent to the demultiplexer (19).
, (20), the output is as shown in FIG. 14F.

In this case, the count (+A
4J: Is I 41g1 G is increased from the leading edge of the masking pulse to the output point of the pilot pulse, and this count value is held thereafter. On the other hand, the count value of the counter (82) is increased until it becomes a full count after the t=O pulse, as shown in FIG. 14.

That is, the counters (81) and (82) each operate as an integrator that integrates the time after the pulse.

And at the counter (81), the demultiplexer (19)
.

The delay time of (20) is measured by the count value, and this value includes variations due to temperature characteristics of the demultiplexer (19) and (20), while the delay time of the counter (8)
In 2), counting is performed after the t=Q pulse, and when the count value reaches a value equal to the delay time of the demultiplexer (19), <20), a gate pulse is formed as shown in FIG. 14I.

Furthermore, from the monostable multibibreak (91), the 14th
A reset pulse as shown in Figure J is taken out.

This allows the demultiplexer (1), (20
) Regardless of variations in delay time due to temperature characteristics, etc., a gate pulse is formed at the time when the signals of the preceding ghost and subsequent ghost detection periods are distributed to the demultiplexers (19) and (20).

By the way, in the above-mentioned circuit, the circuit configuration becomes complicated due to the use of a counter and the like. Therefore, for example, as shown in FIG. 15, timing can be generated using an integrator based on charging and discharging a capacitor. In the figure, a switch (9) is turned on by a masking pulse from a terminal (84) and turned off by a pilot pulse detection signal from a terminal (85').
2) is provided, and current from a constant current dti (93) is supplied to the capacitor (94) via this switch (92). Also provided is a switch (95) that is turned on by a t=0 pulse from the terminal (86), and a constant current source (96).
A current is supplied to the C capacitor (97) through this switch (95). These capacitors (94)
, the terminal voltage of (97) is the buffer amplifier (!18
), (9ri) ゛(compare (100)
supplied to The output of this 21 inverter (100) is supplied to a monostable multi-high break (88). Also a capacitor (94).

(97) in parallel with a reset switch (101),
(102) is provided, and a monostable multibibreak (9
1) is turned on at the output.

In this circuit, capacitors (94), (97)
The terminal voltage of is as shown by L in FIG. 14, and a gate pulse is formed at the same timing as described above.

Since this circuit does not use C, counters, etc., the circuit configuration becomes extremely simple.

Further, FIG. 16 shows a specific circuit configuration of the circuit shown in FIG. 15. The figure shows a circuit designed to be integrated into an IC, and parts corresponding to those in FIG. 15 are marked with the same symbol.

In the figure, a current mirror consisting of transistors Qi and ca2 is provided, and transistors Q3 + Q4, which are controlled by signals from terminals (84) and (85'), are connected in series to the collector of this transistor Q1. Here, the masking pulse supplied to the terminal (84) has a surface potential during that period, and the pilot pulse detection signal supplied to the terminal (85') has a low potential after detection. Therefore, (from the leading edge of the masking pulse until the pilot pulse is detected, 1-transistors Q3 and Q4
is turned on, and a constant current formed with resistor 11 (R+) is passed through the current mirror. This current is passed through the capacitor (9
4), and the charged potential is supplied to the 21st floor (100) via the buffer amplifier (9B).

Also, transistor Q5. A current mirror consisting of transistor Q6 is provided, and a terminal (8
A transistor Q7 controlled by a signal from 6) is connected in series. Here, the t=Q pulse supplied to the terminal (86) is a signal that is set to l'b potential after L=Q.Therefore, after t=6, the transistor Q7 is turned on, and a constant current is formed together with the resistor R2. is passed through the current mirror. This current charges the capacitor (97), and the charging potential is passed through the buffer amplifier (99) to the comparator (10').
0).

As a result, the timing of the ζ gate pulse is detected at the 2 l chamber leak (100).

In Fig. 15 and Fig. 16, the reset switch (
101), (102) to capacitor (94)
, (!17) to 11! , provided in the column ° (there is,
This is not necessarily necessary, and can be left to natural discharge.
You can. However) ＼・7 Soar amplifier (9B),
(99) is the human power impedance of ρ, and if the discharge is not sufficiently performed by the next vertical synchronization pulse, the residual voltage will be added and the voltage will become constant near the saturation level. There is a risk of malfunction. A reset circuit is inserted to prevent this.
The discharge is made at least until the next vertical synchronization signal. In the figure, the reset is performed at the trailing edge of the 1=0 pulse. Further, since the capacitor (94) holds the potential for a certain period of time, the buffer amplifier (9th) may be designed to have a high impedance, and a reset circuit may be provided only for the capacitor (94).

By the way, the inventor of this application previously developed a coupled circuit (81, (11),
We have proposed a device in which the demultiplexers (19) and (20) are divided into a plurality of parts so that the length of the removal period can be changed depending on the state of the ghost. In that case, in the circuit described above, if the removal period becomes long, the capacitor (94
) reaches the saturation level and timing cannot be detected. Also, assuming a 1-short removal period, the capacitance 9 of the capacitors (94) and (97) is increased,
If the current values of the constant current sources (93) and (96) are set small, the charging potential will be low if the removal period is short, and sufficient resolution will not be obtained.

For example, in Fig. 16, by adjusting the emitter resistances of the transistors Q, Q2, Qs, and Q6 that constitute the current mirror, it is possible to control the charging current (time constant of the integrator) according to the length of the removal period. That is, in FIG. 17, at least one of the emitter resistances is made variable. Here, A is both emitter resistors) IV resistance R3, R
4 is external to the IC, a fixed resistor is provided at the emitter of transistor Q1, and a variable resistor is provided at the emitter of transistor Q2.

Further, B is a case where a fixed resistor R3 is provided inside the IC. However, in this case, the fixed resistor and the variable resistor have different temperature characteristics, and there is a risk that malfunction may occur due to temperature changes. At that point, attach the emitter resistor R to C.
3. Both of R4 can be constructed with RIJ variable resistance resistors, or both can be controlled with variable resistor R5 as shown in D.
ζ is also good. Note that these circuits use transistors QG and Q6.
It is also provided in the same way.

Furthermore, FIG. 18 shows another example in which the time constant of the integrator is changed. Corresponding parts in the figure are not given the same reference numerals.

In the figure, a differential switch circuit consisting of transistors Q1□ and Q12 is provided, and one of the transistors Q
Terminals (84) and (85') are connected to the base of transistor Q12, and a predetermined bias circuit is connected to the base of the other transistor Q12. Also, the transistor Q 1'
1 is connected to transistor Q1.

Further, a constant current source transistor Q13 is connected to the emitters of the transistors Q I'l and Q12.

Similarly, transistor QI4. A differential switch circuit consisting of Qts is provided, and one of the transistors Q1
A terminal (86) is connected to the base of transistor QI5, and a predetermined high-speed circuit is connected to the base of the other transistor QI5. Further, the collector of transistor Q14 is connected to transistor Q5. Furthermore, transistor 0141 Q
A constant current transistor Qte is connected to the emitter of 16.

(Transistor Q13. The bases of Qzs are commonly connected to the base of a transistor Ql? forming a current mirror, and a variable resistor Rl's is provided at the collector of this transistor Ql?.

In this circuit, by adjusting the IJ variable resistor R1'1, the constant tU current value flowing through the transistors Q13, QIG is controlled, and the time constants of both integrators are changed. In this case, there is an advantage that only one ζ adjustment point is required for the two integrators.

Furthermore, FIG. 19 shows the case where the time constant of the above-mentioned integrator is adjusted to j, Q% llJ by field hacking. In the figure, the signal from the buffer amplifier (98) is
- (110), this switch (110) is turned on by a gate pulse from the capacitor (100), and the potential at this time (held potential) is sampled. This potential is supplied to a ratio calibrator (113) via a low-pass filter (III) and a buffer amplifier (112), and is compared with the voltage of a reference voltage source (114). This comparison output is supplied to the current control circuit (115), which controls the constant current sources (93) and (96).

As a result, the constant current value is controlled so that the integral value becomes constant according to the length of the removal period, as shown in FIG. 14, M, N, and O, for example. In the figure, when the ζ removal period is short, the slope becomes sharper as shown in a, and when it is longer, the slope is reduced as shown in C.

The specific circuit configuration is shown in FIG. Corresponding parts in the figures are given the same reference numerals. Also, the capacitor surrounded by the broken line is I
C is externally attached.

Furthermore, if such a field hack configuration is adopted, there is a risk of malfunction during a transition period such as when the power is turned on. As shown in Fig. 21, a crystal-injected capacitor amplifier (!18') is provided in front of the buffer amplifier (98), and a limiter circuit (120) connected to, for example, 6 DC current is installed in between. This can be prevented by providing a limiter on the integral output of the masking pulse.

Zunawaji If there is no limiter in the above circuit, the capacitor (94) will
is rapidly charged by the feed hack, and the capacitor (
97), the comparator becomes equal to the saturation level of (1
00) cannot be obtained.

Therefore, the switches (1, 10) are not turned on, sampling of fee hacks is not performed, and the circuit is fixed in this state.

Therefore, by providing a limiter to the output of the capacitor (94), such malfunctions can be prevented.

Effects of the Invention According to the present invention, it has become possible to perform good iχ detection with a simple configuration.

[Brief explanation of the drawing]

Figures 1 to 1O are diagrams for explaining the conventional device;
1 and 12 are block diagrams of an example of the present invention, i!
'S13 to 21 are diagrams e for explanation thereof. (14) is a synchronous separation circuit, (15) is a standard waveform forming circuit, (71) is a differentiation circuit, (73) is a pilot pulse detection circuit, and (74) is a timing generation circuit. Figure 13 Figure 15 Figure 14 Procedural amendment (!!)
11j) 1. Indication of small I'I Patent Application No. 88206 of 1988 2. Title of the invention Ghost removal device-3. Relationship with the person making the correction 9. Yoku Kitashina 6-cho "17-35 name (218)
Representative director of Sony Corporation: ii- role large q′< lll! ,
l('. 4, Deputy 8, 1-V, 8-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo (arrival j (+': building) 5, II visit of the amendment order, Akira +
Month 1-16, 1-16, Number of inventions increased by extraction 7, Addendum λ・] Elephant Detailed description of the invention in the specification and drawings (1) In the specification, page 12, line 9 [
Transistor (461J) "Transistor (45
Correct it to 1J. (2) In the same page, page 13, lines 1 to 3, "D terminal K...to the clear terminal" is corrected to "clock terminal K." (3) Same page, line 5, "Clock terminal pressure" is replaced with "
At the same time as it is supplied to the D terminal, the polarity is reversed and the signal is supplied to the clear terminal of the flip-flop circuit IO1.'' (4) In the same page, page 30, line 8, after ``by this'', add K ``the output waveforms of the buffer amplifier, end, and comparator, respectively''. (5) Same page, line 17, “Feedback”
"Feedback" is corrected. (6) In the drawings, Figures 14, 15, and 21 will be corrected separately. Above Figure 14 Corrected diagram Figure 15 Figure 21

Claims (1)

[Claims] A signal delay circuit for the preceding ghost, a signal delay circuit for the subsequent ghost, a weighting circuit connected to each tap of the signal delay circuit for the preceding and subsequent ghosts, a delay circuit for the demultiplexer of the preceding ghost, and a delay circuit for the demultiplexer of the preceding ghost, and a signal delay circuit for the subsequent ghost. A transversal filter having delay circuits for ghost demultiplexers, each tap of the delay circuit 1 for these demultiplexers, and a switching circuit and a memory circuit connected between the weighting circuits is connected to the video signal source. A correction delay circuit is connected to the video signal source to create a ghost cancellation signal and has a delay time substantially equal to the preceding ghost signal delay circuit, and the output video from the correction delay circuit is connected to the video signal source. In a ghost removal device that removes ghosts by combining a signal and the ghost cancellation signal, the video (1, 1,
3F+ is supplied to the sync separation circuit, and based on the output from this sync separation circuit, a pilot pulse is formed at a position corresponding to just before the ghost detection period, and is sent to the demultiplexer delay circuit for the CC upper, rear, rear, and leading ghosts. The Gose 1 to removal device is manually operated in series, detects the pilot pulse from the signal passing through both the demultiplexers, and controls opening/closing of the switching circuit based on this detection signal.