JPH01151817A - Synchronizing signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain a clock always synchronously with a prescribed period of an inputted synchronizing signal by comparing a charging voltage with excellent linearity obtained through constant current charging and a voltage sampled synchronously with a prescribed timing and generating a clock signal synchronously only when the charging voltage exceeds the sampling voltage. CONSTITUTION:A signal Sb with a proper duty ratio is generated by a resistance ratio of a ladder resistor so as to generate a clock signal only during the period and a signal Sp with an excellent linearity is used as a reference signal to decide the timing, then a highly accurate clock Q is obtained. Moreover, the sampled voltage is divided by the ladder resistor to form a reference voltage of a comparator 11 and the comparison between the said voltage and the charging voltage keeps a prescribed clock period, then the clock signal with the period of a horizontal synchronizing signal is always obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronization signal generation circuit for forming a clock signal of a predetermined period synchronized with a horizontal synchronization signal from a synchronization signal based on a standard television system.

(Prior Art) Conventionally, the circuit shown in FIG. 7 has been used because it is necessary to always obtain a clock signal equal to the period of the horizontal synchronization signal from the synchronization signal (including horizontal synchronization signal and vertical synchronization signal) based on the standard television system. was.

In the figure, 1.2 is a monostable multi-bi break, in which resistive elements R1 and R2 are connected between a predetermined time constant setting terminal and the power supply Vcc, and between the time constant setting terminal and the ground terminal. Capacitive element CI.

C2 is connected, and the output terminal of the monostable multivibrator 1 and the input terminal of the monostable multivibrator 2 are connected. When the synchronizing signal CK is supplied to the input terminal of the monostable multi-bi break 1, the mono-stable multi-bi break 1 outputs a rectangular signal S1 with a pulse width equal to the time constant τ due to R1 and C+ in synchronization with it, and is further cascaded. The monostable multi-bi break 2 has a rectangular signal S2
A rectangular signal S2 having a pulse width equal to the time constant 72 formed by R2 and C2 is outputted in synchronization with . FIG. 8 is a timing chart showing this operation, in which the input synchronization signal CK
The output signal S is inverted from the "L" level to the "H" level in synchronization with the rise of the signal S, is held at the "H" level for a time constant τ1, and then is inverted again to the "L" level. Here, the synchronization signal CK of the standard television system includes a horizontal synchronization signal, an equalization pulse in the equalization period, and a vertical synchronization pulse in the vertical synchronization period, each of which has a different period, but as shown in FIG. Since the synchronization signal generation circuit is a circuit that cannot be retriggered, it is possible to ignore the equivalent pulse and the vertical synchronization pulse during the vertical blanking period and obtain the signal S1 that is synchronized only with the horizontal synchronization signal. As a result, a rectangular signal S2 synchronized with the horizontal synchronization signal can be obtained from the monostable multi-by-break 2.

(Problems to be Solved by the Invention) However, such conventional synchronization signal generation circuits have the following problems. In other words, the monostable multi-bi break itself is small because it is formed from a semiconductor integrated circuit, but the overall circuit becomes large because it requires external components such as resistors and capacitors. The absolute accuracy of attached parts is ±20% to ±30 of the standard value.
% error and large fluctuations due to temperature.Even if the settings are made under the conditions, the characteristics will change over time and the pulse width setting accuracy will be poor. Even if it is formed integrally with the main body, the manufacturing accuracy will have an error of ±20% to ±30%, and furthermore, once it is manufactured, it is extremely difficult to adjust it from the outside, so it is necessary to obtain a high-precision pulse signal. It was not suitable for cases where

(Means for Solving the Problems) The present invention has been made in view of the above problems, and it is an object of the present invention to generate a rectangular signal of an appropriate pulse width with high precision in synchronization with an input clock signal. The purpose of the present invention is to provide a synchronization signal generation circuit.

To achieve this object, the present invention provides a charging means for charging with a current from a constant current source and generating a charging voltage thereby, and discharging the charge of the charging means in synchronization with a predetermined synchronization signal. a discharging means; a sampling means for sampling the charging voltage at a predetermined time point excluding a period during which the discharging means causes the charging means to discharge; a predetermined divided voltage of the output voltage of the sampling means; and the charging voltage. a comparator for detecting whether or not the charging voltage exceeds the divided voltage of the sampling means by comparing the level of the charging voltage with the voltage dividing voltage of the sampling means; By providing a suppressing means for prohibiting the discharging means from discharging during the non-detection period, it is possible to reduce the number of external components and facilitate the integration of semiconductor integrated circuits. The technical point is that it is possible to always output a clock signal with a preset period and to obtain an extremely highly accurate clock signal.

(Embodiment) Hereinafter, one embodiment of the synchronization signal generation circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of this embodiment. First, to explain the configuration, there is a constant current source 3 that outputs a constant current of a predetermined current value, and a constant current source 3 that outputs a constant current of a predetermined current value. First capacitive elements 4 for charging with current from the first MO3 type switching element 3 are connected in series with each other, and a first MO3 type switching element 5 is connected in parallel to the capacitive elements 4. The connection point P of the constant current source 3, the capacitive element 4, and the switching element 5 is connected to one end of the second capacitive element 7 via the second MO3 type switching element 6, and the other end of the capacitive element 7 is connected to the ground terminal. is connected to. The one end of the capacitive element 7 is further connected to the input terminal of a buffer amplifier 8, and two ladder resistors 9.10 are connected between the output terminal of the buffer amplifier 8 and the ground terminal.

A comparator 11 has a non-inverting input terminal connected to a connection contact P, and one inverting input terminal connected to a connection contact V of the resistors 7 and 8.

A first edge detection circuit 12 generates a rectangular signal S6 having a predetermined time width in synchronization with the rising edge of the manually input synchronization signal CK. The signal S6 is logically ANDed with the signal S from the comparison circuit 11 in the AND circuit 13, and then supplied to the second edge detection circuit 14.

Further, this signal Q is supplied to the gate contact of the switching element 6, and is also outputted to the output terminal 15 as a clock signal to be formed in this embodiment. The second edge detection circuit generates a rectangular signal S having a predetermined time width in synchronization with the falling edge of the signal Q. This signal S. is supplied to the gate contact of the switching element 5.

FIG. 2 shows an example of the first edge detection circuit 12, and shows an example of the first edge detection circuit 12.
A human input signal is directly supplied to one input terminal of the ND circuit 16, and a human input signal is supplied to the other input terminal via an inverter circuit that generates a predetermined delay time Δτ. Therefore, a rectangular signal having a width of the delay time Δτ is output in synchronization with the rising edge of the human input signal. The second edge detection circuit 14 has a configuration as shown in FIG. 3, for example. Note that it is possible to apply not only these circuits but other well-known circuits.

Next, the operation of this circuit will be explained based on the timing chart of FIG.

First, at time t1, when the synchronizing signal CK is inverted to the H level, the edge detection circuit 12 generates the signal Sa at the H level for a predetermined period of time in synchronization with the rising edge of the synchronizing signal CK. When the output Sb is at the "H" level, the output signal Q of the AND circuit 13 becomes the "H" level in synchronization with the signal S. During that period, the switching element 6 is turned on, and the voltage at the contact P increases. The capacitive element 7 samples Vp. Note that if this sampled voltage is V, this voltage is also applied to both ends of the ladder resistor 9.10. Next, at time t2 after a predetermined delay time Δτ, the second edge detection circuit 14 sets the signal S to “H” level in synchronization with the falling edge of the signal Q. is generated, and the switching element 5 is turned on. Therefore, the charge accumulated in the capacitive element 4 is discharged to the ground terminal via the switching element 5, and the voltage at the contact P becomes zero volts (the voltage change at the contact P is indicated by the signal S).

). Then, at time t3 after a predetermined period of time has elapsed,
The signal Sc becomes "L" level, and the switching element 4 is turned "off" in synchronization with it. Therefore, time t3
Thereafter, the capacitive element 4 starts charging with the current from the constant current source 3 again, and the voltage Sc across the capacitive element 20 increases at a constant slope, and the other capacitive element 7 charges the voltage sampled before that. holds V.

At a certain time t, when the voltage S at the contact point P exceeds the contact voltage V at the ladder resistors 9 and 10, the output signal S of the comparator 11 is inverted to the "H" level.

Then, at subsequent time points t5 to t, the above time point 1
．． - Repeat the same operation as shown in 13.

Here, if the resistance ratio of resistors 9 and 10 is set to 1:R (for example, resistor 9 is set to 1Ω and resistor 10 is RkΩ), then the period T1 from time t to time t6 is Time t3
The ratio of period T2 from to time t (T2/TI')
becomes R/(R+1), and the signal S of a predetermined duty ratio is synchronized with the synchronization signal CK by simply changing the resistance ratio of the ladder resistors 9 and 10.

The clock signal Q can be generated only during the period when the signal S is at the "H" level.

Although FIG. 4 shows the case where the synchronization signal CK is a part of the horizontal synchronization signal having a period of IH, the operation when the period is shorter than that, such as an equalization pulse, will be explained based on FIG. To explain only the differences from the operation shown in Fig. 4,
When the synchronizing signal CK becomes "H" level at time tM+ (same as time t, 12) within the IH cycle, the first
The output signal S6 of the edge detection circuit 12 becomes "H" level in synchronization with this. However, at this time tXI, the voltage Sp at the contact P is still at the ladder resistances 9 and 10.
Since it is lower than the 0 contact voltage V, the output S of the comparator 11.

remains at the "L" level, and the output signal Q of the AND circuit 13 also remains at the "L" level. Therefore, even if the synchronization signal CK reaches the "H" level within the horizontal synchronization period (IH), it is ignored, and as shown in FIG. Obtainable.

In this way, according to this embodiment, the signal S has an appropriate duty ratio depending on the resistance ratio of the ladder resistor.

Since the clock signal is generated only within that period and the timing is determined based on the signal S having excellent linearity, a highly accurate clock signal Q can be obtained. In addition, the sampled voltage is divided by a ladder resistor to create a reference voltage for the comparator 11, and this voltage is compared with the charging voltage to maintain a predetermined clock cycle, so the cycle of the horizontal synchronization signal is always maintained. A clock signal can be obtained.

(Effects of the Invention) As explained above, according to the synchronization signal generation circuit of the present invention, instead of the conventional type in which the pulse width is set using a time constant using an external capacitive element and a resistor, charging is performed using a constant current. This method compares the charging voltage with good linearity obtained with the voltage sampled in synchronization with a predetermined timing, and generates a clock signal in synchronization only when the charging voltage exceeds the sampling voltage. , it is possible to obtain a clock signal that is always synchronized with the predetermined period of the input synchronization signal. Further, since external parts as described above are not required, the device can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the synchronization signal generation circuit according to the present invention, FIGS. 2 and 3 are circuit diagrams showing a specific example of the edge detection circuit of FIG. 1, and FIGS. 4 and 5 6 is a timing chart for explaining the operation of the circuit shown in FIG. 1, FIG. 7 is a circuit diagram showing an example of a conventional synchronizing signal generation circuit, and FIG. 8 is a diagram of the circuit shown in FIG. 7. 5 is a timing chart for explaining the operation. 3: Constant current source 4: First capacitive element 5.6: Switching element 7: Second capacitive element 8: Buffer amplifier 9.10: Resistor 11: Comparator 12.14: Edge detection circuit 15: AND Circuit agent Patent attorney (8107> Kiyotaka Sasaki (and 3 others)
Figure 2 ΔU Figure 3)! /l Fig. 7 Fig. 8 Procedural amendment document February 16, 1988, 34 years of birth, Agency Ai Miyaden 1, Indication of the case, Patent Application No. 309496, 1988 2, Name of the invention Synchronous signal generation circuit 3, Amendment Relationship with the case of a person who does Contents: As shown in the attached sheet.

Claims (3)

[Claims] (1) Charging means for charging with a current from a constant current source and thereby generating a charging voltage; discharging means for discharging the charge of the charging means in synchronization with a predetermined input synchronization signal; and the discharging means sampling means for sampling the charging voltage at a predetermined time point excluding a period during which the charging means is discharging; and comparing the level of a predetermined divided voltage of the output voltage of the sampling means and the charging voltage. a comparator for detecting whether or not the charging voltage exceeds the divided voltage of the sampling means; and a comparator for detecting whether the charging voltage exceeds the divided voltage of the sampling means; 1. A synchronization signal generation circuit comprising: inhibiting means for prohibiting the means from discharging. (2) The synchronizing signal generation circuit according to claim 1, wherein the charging means includes a capacitive element that charges the current from the constant current source. (3) Control means for controlling the operation timing of the discharging means and the sampling means so that the sampling means first samples the charging voltage and then the discharging means discharges. The synchronization signal generation circuit described.