JPS59213160A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To simplify the process of manufacturing the titled element by reducing the number of electrodes in case of using a CCD as said element. CONSTITUTION:The photo receiving part 15A of said element 15 has a plurality of sensor regions SENS formed by arrangement in the horizontal and vertical directions, respectively, at fixed pitches. Many vertical shift registers VR extending respectively in the vertical direction are formed by arrangement between said regions SENS formed by arrangement in the horizontal direction. A temporarily accumulated region PS wherein a part of photo signal charges photoelectrically converted respectively by sensor regions SENSA and SENSB adjacent to each other in the vertical direction is accumulated is formed between said regions SENS formed by arrangement in the vertical direction. The N<-> type region 23 for a readout gate region ROG is formed at the region between this temporarily accumulated region PS and the vertical shift register VR and between selectively formed P<+> type regions 20, and the region other than that is made as the region CS for a channel stopper. Thus, the electrodes for the readout gate and channel stopper can be omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a solid-state image pickup device using a charge transfer device such as a CCD.

Background Art and Problems Therein For example, when a CCD is used as a solid-state imaging device, the light-receiving region (picture element) may have an MO8 configuration or a PN junction configuration.

Figure 1 is an example of the former, Figure 2 is an example of the latter,
In this example, (1) is a P-type silicon substrate;
Near the top surface r is an N-type region (2) in order to make the vertical shift register Vl (a bulk channel (embedded channel)).
At the same time, a P-type head area (4) for the sensor area 0FCG is formed, and a P-type head area (5) for the channel + last part C8 is formed on the right side. Control gate is shown.

Then, an insulating layer (7
) for vertical transfer through an electrode made of polysilicon, etc. (
8) is formed, and (9) is a transparent electrode that controls the sensor area 5DNS.

In FIG. 1, a sensor region 5DNS having an MO8 configuration is formed by the base (1), an insulating layer (7), and a transparent electrode (9), and in FIG. 2, an N-type region is formed in the base (1). (12+ and the base (11) form a sensor region 5ENS having a PN junction configuration.

In the configuration shown in FIG. 1, since light is absorbed by the transparent electrode (9) formed in the sensor area 5ENS, the sensitivity to red, green, and blue color light decreases overall, and the Since the spread of the depletion layer formed in the VB is shallow, optical signal charges caused by long-wavelength optical signals (red signals, etc.) that enter deep inside the substrate outside the depletion layer are diffused into the substrate, and this is caused by the vertical shift register VB. , and a smear occurs. Since the housing and overflow drain OFD are arranged two-dimensionally, the device surface cannot be used effectively.

In the configuration shown in FIG. 2, since there is no transparent electrode (9) in the sensor region 5ENS, a decrease in sensitivity can be suppressed, but in this case as well, smear occurs because the depletion layer in the substrate (1) is shallow. Additionally, due to the PN junction configuration, when reading optical signal charges, one optical signal charge in the sensor area cannot be completely transferred to the vertical shift register 11 side, resulting in an afterimage.

These conventional problems can be solved by configuring the light receiving section as shown in FIG. 3, for example.

FIG. 3 is an example of a solid-state image pickup device that can be used as an interline transfer configuration or a modification of a frame or field transfer configuration.

This solid-state image sensor a9 includes a light receiving section (15A) and a storage section (
15B), and the light receiving section (15A) has a light receiving area (sensor area that becomes a picture element) SEN8 and this sensor area 5B.
Vertical shift registers VR, which transfer optical signal charges photoelectrically converted by the NS, are provided independently.

On the other hand, the storage section (15B) has a region for storing optical signal charges from each vertical shift register V'R for each sensor region, and is designed to be used in common with this region and the vertical shift register VB. It is something that

Light reception! The charge transfer from (15A) to the storage section (15B) is performed during the vertical blanking period, and the charges transferred and accumulated in the storage section (15B) are transferred to the horizontal shift register (readout register) (15C) sequentially every horizontal period. The data is transferred to and read out.

In such a solid-state image sensor (151), a light receiving section (15
A) is configured as shown in FIG. 4 and below.

In the light receiving section (15A), a plurality of sensor regions 5DNS are arranged at a predetermined pitch in the horizontal and vertical directions, and a plurality of vertical shift registers extending in the vertical direction are arranged between the sensor regions 5BNS arranged in the horizontal direction. V
) L is arrayed. Between the sensor areas 5ENS arranged in the vertical direction, the vertically adjacent sensor areas SDN S and 5BNS j (1 and J are the i-th and j-th sensor areas) perform photoelectric conversion, respectively. A temporary storage region PS is formed in which a portion of the optical signal charges generated are stored. A readout gate region OQ is provided between the temporary storage region PS and the vertical shift register VB, respectively, for reading out and transferring the optical signal charges stored in the temporary storage region PSVc to the vertical shift register vkL.

FIG. 5 shows an example of the cross-sectional configuration of the light receiving section (151) taken along line I-I in FIG. 4. In this example, a P-type silicon substrate (1) is used. An N-type region (2) is formed to form a channel (buried channel) type vertical shift register vR, and a sensor region 5ENS is formed by a base body (1) and an insulating layer (7) such as 5I02.

Figure 6 is a cross-sectional view taken along the line ■-■ in Figure 4;
However, FIG. 7 is a longitudinal cross-sectional view of the temporary storage region PS, in which an N-type head region aD for a bulk channel is formed in a portion corresponding to the temporary storage region PS, and optical signal charges are accumulated in this portion. Ru. The other N-type region (18 is for channel stopper region C8).

On the surface of the substrate (1) corresponding to the areas +21 and aD, electrodes (11) are formed with a predetermined width so as to extend in the vertical direction, and one electrode (181) is formed with a predetermined width. Used as an electrode for channel stopper region C8,
The other electrode α9 is used as an electrode for the charge readout gate region 1 (OQ).A plurality of electrodes l to y4 for vertical charge transfer are further formed on the upper surface of the substrate (1). Ru.

Figure 84 shows an example of the electrode shape. In this example, optical signal charges are vertically transferred by four electrodes O1 to O4, and the substrate il+ has an N-type region +21 formed thereon.
Four electrodes 4 extending in the horizontal direction are sequentially and alternately adhered to the upper surface of the electrode 4 in the vertical direction. Sensor area 5
As shown in FIG. 5, the top of the BNS is covered with electrodes 1 to 4, each having a comb-like shape. The formation positions of the electrodes 2 to 4 are selected so that the teeth of the electrodes 2 and 3 and the teeth 1 and 4 face each other, and their tips partially overlap.

Each of these electrode layers ~g4 is a sensor area 5ENS.
In order to extend horizontally without covering the top, each electrode
A comb-like base portion (common electrode portion) of the electrode 4 is formed on the upper surface of the base body (1) corresponding to the readout gate region OG and temporary storage region PS. Therefore, the electrode structure in those parts becomes a two-layer structure (see FIG. 6).

During the light reception period, the optical signal charges photoelectrically converted in the sensor region 5ENS are diffused in the directions shown by arrows a, b, c, etc. in FIG. (See Figure 6N and Figure 7).

During the readout period (within the vertical blanking period), the gate pulse is controlled to open the readout gate region BOG (FIG. 6B), and the optical signal charge accumulated in the temporary accumulation region P8 is transferred to the vertical shift register vR side. . Thereafter, the optical signal charge is transferred in the vertical direction based on the clock supplied to the electrode layer 4, and is accumulated in the accumulation section (15B).

According to this configuration, (1) Since there is no electrode layer such as polysilicon in the sensor region 5ENS, the sensitivity, especially the sensitivity at short wavelengths, does not deteriorate.

■ During light reception, the charge due to the long wavelength component photoelectrically converted deep inside the substrate (1) is diffused into the light and a part of it is accumulated in the vertical shift register V, but the charge is swept out and transferred. Therefore, it does not become a smear component. Moreover, since the true optical signal charge transfer is performed at high speed, the occurrence of smear is suppressed.

■During the light reception period, excess charge flows into the vertical shift register VR via the readout gate region BOG, so plumping can be suppressed and the vertical shift register can also be used as an overflow drain, making the element surface more effective. It can be used for.

■ Compared to the sensor configuration using PN junction, N″″
Since the charges accumulated in the mold region aη are transferred, complete transfer is achieved and there is little afterimage.

Because it has the following characteristics, it can eliminate the problems of conventional methods.

By the way, in the case of the above-described configuration, in addition to the first to fourth transfer electrodes G1 to D4, an electrode a9 for a readout gate and an electrode aδ for a channel block are required, so that the element This tends to increase the number of manufacturing processes.

OBJECT OF THE INVENTION Therefore, the main purpose of the present invention is to reduce the number of electrodes and simplify the manufacturing process of the device while making use of the above-described characteristics of the solid-state image sensor.

Summary of the Invention Therefore, in the present invention, a solid-state image sensor is provided with a plurality of light-receiving areas arranged at a predetermined pitch in the horizontal and vertical directions, a plurality of vertical shift registers extending in the vertical direction, and a plurality of light-receiving regions arranged in the vertical direction. Temporary storage regions formed between the regions and in which optical signal charges photoelectrically converted in the vertically adjacent light receiving regions are stored, and read gates formed between the temporary storage regions and the vertical shift register. and the first to fourth regions formed on the vertical shift register.
These transfer electrodes are sequentially and alternately deposited in the transfer direction, and the first and third transfer electrodes are formed to extend over the temporary storage area, and the second and third transfer electrodes are The above object is achieved by forming the fourth transfer electrode so as to extend over the readout region.

Embodiment Next, an example of the solid-state image sensing device according to the present invention will be explained in detail with reference to FIG. 8 and subsequent figures. An example is a case where the present invention is applied to a solid-state image sensor shown in FIG.

The light receiving section (15A) of the solid-state image sensor α9 according to the present invention also has a planar configuration substantially similar to that shown in FIG.

Therefore, as shown in FIG. 8, this light receiving section (15A)
A plurality of sensor regions 5ENS are arrayed at a predetermined pitch in the horizontal and vertical directions, respectively.A plurality of vertical shift registers VR extending in the vertical direction are arrayed between the sensor regions 5ENS arranged in the horizontal direction. 4 Ru. Each vertically adjacent sensor area S BN S is located between the sensor areas SEMS arranged in the vertical direction.
, and 5EN8j (1 and j are the fifth and jth sensor regions), respectively, form a temporary storage region PS in which a part of the photoelectrically converted optical signal charge is stored. Of the regions formed between the temporary storage region PS and the vertical shift register VR, a predetermined region is used to read and transfer the optical signal charge stored in the temporary storage region PS to the vertical shift register V)L. A read gate region ROG is provided. The other area is area C8 for channel stopper.
It is said that

FIG. 9 shows an example of the cross-sectional configuration of the light receiving section 05) on the line T in FIG. 8, and shows the sensor area 5BNS.
and the N-type region (2) is a channel stopper region C.
A P-type region f2Ql, +211 functioning as 8 is formed. One P type region (2) is selectively formed in the vertical transfer direction, as is clear from the planar configuration of FIG.

FIG. 10 is a cross-sectional view taken along line IT-IV in FIG. 8, and FIG. 12 is a cross-sectional view taken along line VI-VI in FIG. An N-type region Q7) for a no-silk channel having a planar shape as shown by diagonal lines in FIG. 8 is formed, and optical signal charges are accumulated in this region.

FIG. 11 is a cross-sectional view along the line ■-■ in FIG.
An N-type region (to) for the readout gate region ROG is formed in the region between the selectively formed P-type region (20) and the vertical shift register VR. 1), an electrode layer 4 is formed on the upper surface for reading charges and vertically transferring the read charges.

FIG. 8 shows an example of the electrode shape. In this example, optical signal charges are vertically transferred by four electrodes y1 to d4, and the substrate (1) formed with an N-type region (21)
Four electrode portions 04 extending in the horizontal direction are sequentially and alternately adhered and formed on the upper surface of the electrode. Sensor area 5
As shown in FIG. 9, on the BNS, in order to prevent the electrodes 1 to 04 from being covered, each has a comb-like shape, and the electrodes 2
The formation positions of the electrodes A to D4 are selected such that the teeth of D3 and D1 and G4 face each other, and their tips partially overlap.

Each of these electrodes is connected to the sensor area 5ENS.
In order to extend horizontally without covering the top, each electrode
The comb-shaped base (common electrode part) of the holder 4 is connected to the base (1) corresponding to the readout gate region I (, OG, and temporary storage region PS).
) is formed on the top surface of the However, the upper surface of the P-type region □□□ for the readout gate is connected to the second and fourth electrode groups 2. The first and third electrodes Ox
+03 shape is selected (see Figure 8).

This is done for the second and fourth electrode parts.

clock CK2. By CK4?
This is to enable control of the Jr output gate region ROG.

1. In order to form a potential well as shown in FIG. 11, the second and fourth electrodes 2 + /lJ4 are connected to the first and third bipolar electrodes 961 and J2' as shown in FIG.
3. J: Selected to be located in the upper layer. Next, readout and transfer of optical signal charges will be explained with reference to FIG. 14 and subsequent figures.

FIG. 14 is an example of reading out all optical signal charges field by field in the sensor region 5ENS, where one field period is divided into a light reception period and a vertical blanking period V-BLK, and the blanking period V-BLK is further divided into a sweep transfer period, an optical signal charge readout period, and a charge transfer period for the optical signal charges. Therefore, during the vertical blanking period V-BLK, as shown in FIGS. 14 to 16, the first and third electrodes are transferred to the lock CK1. CN3 is the second and fourth electrode 12. J2'
4 is the transfer lock CK2. CK4 is added.

During the light reception period, the vertical shift register VR also functions as an overflow drain, so that the second and fourth electrodes G2 and D4 are provided with a predetermined potential V1 (as shown in FIG. 14B).
>0) at a constant level of the clock CK2. C.K.
4 is added to the first and third electrodes 11.1
213 is a clock CK with a lower potential than this and a constant level.
IICK3 is added respectively. As a result, the potential of the sensor region 5BNS, readout gate region ROG, and temporary storage region PS with respect to the substrate surface becomes 11th.
The button is as shown in Figure A.

During the light reception period, the optical signal charges photoelectrically converted in the sensor region 5ENS are diffused in the directions shown by arrows a, b, c, etc. in FIG. (See Figure 12).

At this time, as shown in FIG. 11A, the read gate region R
Since the potential of OQ has a depth corresponding to the potential Vl, when charges exceeding this potential flow into the temporary storage region PS during the light reception period (the potential at that time is shown by a broken line), all of those charges become excess charges. This causes an overflow to the vertical shift register VR. Therefore, in the first half of the vertical blanking period V, BLK, it is necessary to sweep out and transfer this excess charge.

In the sweep-out transfer period, clocks CK1 to CK4 selected to have potential relationships different from those described above are supplied to the electrodes A-y4 to sweep out and transfer excess charges. This transfer operation can be easily understood from the following explanation of the video signal charge transfer operation, so detailed explanation thereof will be omitted.

4. The excess charge accumulated in the vertical shift register VR is transferred to the horizontal shift register (15C) without being accumulated in the accumulation section (1, 5B). and throw it away. That is, it is not used as a signal carrier. When the sweep transfer is completed, a read period for optical signal charges begins.

During the readout period, the second and fourth electrodes 12. A read clock (pulse) PR shown in FIGS. 14B and 15 is applied only to P4. As a result, a predetermined potential is commonly applied to the vertical shift register VB and the readout gate region BOG, so the potential well at that time becomes as shown in Figure 1B, and is stored in the temporary storage region PS. The optical signal charge is transferred to the corresponding well of the vertical shift register Vl (111th Song 81, FIG. 13A) through the readout gate region BOG.

When this transfer is completed, a charge transfer period begins.

FIG. 15 shows an example of clocks CKl to CK4 used for charge transfer. Clock CK, ~CK4 are both 600
The clocks CKl and CN3 and CN3 and CN3 are the same high-frequency pulses of about kHz, respectively, and have opposite phases, and the clocks CK1, CN3, and CN3 are the same high-frequency pulses of approximately kHz, and the clocks CK1, CN3, and CN3 are the same high-frequency pulses. If the clocks CK1 to CK4 used in the odd field are those shown in FIG. 15, the clocks CK1 to CK4 used in the even field are as shown in FIG. The shifted clocks CK1 to CN3 are used, and at the start of the transfer of the corresponding charge transfer period of each field, the second and fourth electrodes 12t04 are each supplied with a start pulse, in this example - a level start pulse Ps ( 15, 16)
is inserted.

Reference E in FIG. 12 shows a transfer mode in an odd field, and time to-t4 corresponds to time t□ to t4 in FIG.

The optical signal charges are accumulated in potential wells corresponding to the second and fourth electrodes J'2 + Ji14 of the vertical shift register V (FIG. 13A). By the start pulse Ps, only the potential under the second and fourth electrodes 2 and 4 changes, and the optical signal charges accumulated in the potential wells formed on both sides of the first electrode are mixed (the first Figure 13B). Optical signal charge width and 8n (m, n
The result of mixing the light of the th sensor region 5ENS (indicating the i-th charge) is indicated by Smn.

Transfer lock CKl to CK4 following start pulse Ps
The optical signal charge Smn is transferred as shown in FIG.
B) is stored in the corresponding position.

In the even field, transfer locks CK1 to C shown in Figure 16 are used.
Note that K4 and the start pulse Ps are supplied, and the optical signal charge 5n (r+
+1) is stored in the well shown in FIG. 3F. This makes it possible to obtain optical signal charges on a horizontal line different from the horizontal line in the previous field. Time points t5 to t7 shown in FIG. 13 correspond to time points t5 to t7 in FIG. 16.

FIG. 17 shows an example of frame transfer of optical signal charges. Frame transfer refers to a method in which optical signal charges corresponding to the second electrode g2 and optical signal charges corresponding to the fourth electrode 4 are read out alternately for each field and transferred.
In this case, each optical signal charge is read out in units of one frame. Therefore, the read gate pulse Ps inserted between the clocks CK2 and OK.
The inserted fields are frame-by-frame, and the fields to be inserted are separated (FIGS. 17B and C). As a result, for example, when the optical signal charges of odd frames are read out and transferred by the readout gate pulse PR applied to the second electrode 2, the optical signal charges of even frames are read and transferred by the readout gate pulse PR applied to the fourth electrode 4. is read and transferred.

In frame transfer, clock CK2. Either one of the clocks shown in FIG. 15 or FIG. 16 may be used for CK4. There is no particular need to insert a start pulse Ps into the clocks CK1%CK4 during sweep transfer.

The present invention can also be applied to solid-state image pickup devices using a normal interline transfer method or other transfer methods.

As described in detail, according to the configuration of the present invention, it is possible to realize a highly sensitive solid-state image pickup device that does not cause smear or afterimage and can effectively utilize the device surface, and also achieves the first to fourth aspects. By selecting the shape of the electrode layer 4 as described above and making the structure inside the base film as described above, it is possible to provide these electrodes even if the readout gate electrode and the channel stopper electrode are not provided. It is possible to realize the same behavior as when

As a result, compared to the configuration shown in Figure 4, the light receiving section (15A)
According to this invention, the manufacturing process can be simplified.
It has the feature that it can perform either field transfer or frame transfer, so it can be used depending on the purpose.

Note that an N-type region is formed in the sensor region 5ENS (
If the sensor region 5DNS is based on the sensor region 8ENS, the optical signal charges photoelectrically converted in the sensor region 8ENS can be effectively and efficiently stored in the temporary storage region PS.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of essential parts of a conventional example of a solid-state image sensor, FIG. 3 is a plan view of an example of a solid-state image sensor used to explain the present invention, and FIG. A plan view showing an example, Fig. 5 is a cross-sectional view on the I-■ line and a diagram showing the potential with respect to the substrate surface, Fig. 6 is a cross-sectional view on the ...-■ line and a diagram showing the potential, and Fig. 7 is a diagram showing temporary accumulation. FIG. 8 is a plan view showing an example of the light-receiving section of the solid-state image sensor according to the present invention; FIG. 9 is a cross-sectional view along the line ll-1 in FIG. 8 and the potential thereof. Fig. 10 is a cross-sectional view on the line IV-IV and its potential, Fig. 11 is a cross-sectional view on the v-■ line and its potential, and Fig. 12 is a cross-sectional view on the line Vl-Vl. Figure 13 is a vertical cross-sectional view of the vertical shift register and a potential diagram of the charge transfer state, Figures 14 to 16 are explanatory diagrams of the transfer lock used during field transfer, Figure 17 is a diagram EiA of a transfer lock used during frame transfer. (I9 is the solid-state image sensor, (]5 is the light receiving unit, (15B)
(1), (201, +211 are negative conductivity type substrates, (2j, αn are other conductivity type regions, VR is a shift register, older brother OG is a readout gate region, 5ENS is a sensor region, C8 is a Channel stopper area, PS is temporary storage [J area, town ~ 14 is transfer electrode. 7゜Figure 14Figure 17

Claims (1)

[Claims] A plurality of light-receiving regions arranged at predetermined pitches in the horizontal and vertical directions, a plurality of vertical shift registers extending in the vertical direction, and a plurality of light-receiving regions each formed between the light-receiving regions arranged in the vertical direction, A temporary storage region in which optical signal charges photoelectrically converted are stored in each region, a readout gate region formed with a gap between the temporary storage region and the vertical shift register, and a first gate region formed on the vertical shift register. ~4th transfer electrodes, these transfer electrodes are sequentially and alternately deposited in the transfer direction, and the first and third transfer electrodes are formed extending over the temporary storage area, and . A solid-state imaging device, wherein the second and fourth transfer electrodes are formed to extend over the readout region.