JPS59213149A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59213149A JPS59213149A JP8811183A JP8811183A JPS59213149A JP S59213149 A JPS59213149 A JP S59213149A JP 8811183 A JP8811183 A JP 8811183A JP 8811183 A JP8811183 A JP 8811183A JP S59213149 A JPS59213149 A JP S59213149A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- case
- angle
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、例えばエポキシ系の樹脂で封止加工される
集積論理回路等を構成する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device constituting an integrated logic circuit or the like sealed with, for example, an epoxy resin.
上記のような半導体装置は、第１図に示すように、エポ
キシ等の樹脂で形成した樹脂封止ケース１１で封止加工
されている。この樹脂封止ケース１１には、回路網の形
成された半導体チップが封止されるもので、この内部回
路網の電極は複数本のリードフレーム１２ｔｈ＋１２ｂ
。As shown in FIG. 1, the semiconductor device described above is sealed with a resin sealing case 11 made of resin such as epoxy. A semiconductor chip on which a circuit network is formed is sealed in this resin sealing case 11, and the electrodes of this internal circuit network are connected to a plurality of lead frames 12th+12b.
.
・・・によシそれぞれ位置設定され４出される。この場
合、樹脂封止ケース１１０表裏面部１３ａ・１３ｂは、
倒れも平坦な形状に形成されている。. . . Each position is set and 4 are output. In this case, the front and back parts 13a and 13b of the resin-sealed case 110 are
It is also formed into a flat shape.
ここで、この半導体装置を、例えば半導体装置検査工程
で搬送する場合には、半導体装置のリードフレーム１２
ａ ＋ ｌ ２ ｂ ＋・・・が、一定額斜角の付い
ｆｃＴ型のシュートレール１４上に跨るように設定する
。これにより半導体装置はシュートレール１４上をその
傾斜方向に滑走し搬送されるもので、この場合、半導体
装置の裏面部１３ｂは、シュートレール１４に対する滑
走面となっている。Here, when this semiconductor device is transported, for example, in a semiconductor device inspection process, the lead frame 12 of the semiconductor device is
a + l 2 b + . . . are set so as to straddle the fcT type chute rail 14 with a constant bevel. As a result, the semiconductor device is transported by sliding on the chute rail 14 in the direction of inclination thereof, and in this case, the back surface portion 13b of the semiconductor device serves as a sliding surface with respect to the chute rail 14.
しかしこのように構成された半導体装置では、例えばこ
の半導体装置をシュートレール１４で搬送するような場
合に、半導体装置の滑走面に相当する樹脂封止ケース１
１の複面部１３ｂが平坦に形成されている為、シー−ト
レール１４との接触面積が大きく、滑走摩擦係数の高い
状態となる。すなわち、この半導体装置は、シュートレ
ール１４の傾斜角度を急角度に設定しない限り滑走しな
い°ものであるため、多数の半導体装置を円滑に搬送す
るのは非常に困難である。However, in the semiconductor device configured in this way, when the semiconductor device is transported by the chute rail 14, for example, the resin-sealed case 1 corresponding to the sliding surface of the semiconductor device is
Since the double-sided portion 13b of 1 is formed flat, the contact area with the seat rail 14 is large, resulting in a high sliding friction coefficient. That is, since this semiconductor device does not slide unless the inclination angle of the chute rail 14 is set to a steep angle, it is very difficult to smoothly transport a large number of semiconductor devices.
この発明は上記のような問題点に鑑みなされたもので、
例えば半導体装置検査工程において、シー−トレールの
傾斜角度をも角度に設定することなく、円滑に滑走し搬
送することができる半導体装置を提供することを目的と
する。This invention was made in view of the problems mentioned above.
For example, an object of the present invention is to provide a semiconductor device that can be smoothly slid and transported without setting the inclination angle of a seat rail to a certain angle in a semiconductor device inspection process.
すなわちこの発明に係る半導体装置は、滑走面に相当す
る樹脂封止ケースの裏面部に、少なくとも３つ以上の突
起状部を形成するようにしたものである。That is, in the semiconductor device according to the present invention, at least three protrusions are formed on the back surface of the resin-sealed case, which corresponds to the sliding surface.
以下図面によシこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第２図はその構成を示すもので、この半導体装置は回路
網の形成された半導体チップを封止した樹脂封止ケース
２ノを外囲器として備えている。この樹脂封止ケース２
ノの両側部には、上記半導体チップの回路網電極に接続
された複数本のリードフレーム１２ａ＋１２ｂ、・・・
が位置設定して突設されるもので、この樹脂封止ケース
２ノの裏面部２１ａには、例えば半球形の突起状部２２
ａ〜２２ｃを形成する。この突起状部２２ｈ〜２２ｃは
、例えば図示しない半導体装置用樹脂封止金型によって
、樹脂封止ケース２１に一体成型されるもので、これに
より樹脂封止ケース２ノの裏面部２Ｊｈを凹凸状面とす
る。FIG. 2 shows its structure, and this semiconductor device includes a resin sealing case 2 as an envelope in which a semiconductor chip on which a circuit network is formed is sealed. This resin sealed case 2
A plurality of lead frames 12a+12b, . . . are connected to the circuit network electrodes of the semiconductor chip on both sides of
For example, a hemispherical protrusion 22 is provided on the back surface 21a of the resin-sealed case 2.
a to 22c are formed. The protrusions 22h to 22c are integrally molded on the resin-sealed case 21 by, for example, a resin-sealed mold for semiconductor devices (not shown), and thereby form the back surface 2Jh of the resin-sealed case 2 into an uneven shape. Make it a face.
すなわちこのように構成される半導体装置を、第３図に
示すように、例えはＴ型のシュートレール１４で搬送す
ると、シュートレール１４の面上には樹脂封止ケース２
ノ裏面部２１ａに形成した突起状部２２ａ〜２２ｃそれ
ぞれの先端のみが接触するようになシ、樹脂封止ケース
２ノの本体部は、突起状部２２ｈ〜２２ｅの高さだけシ
ュートレール１４面から浮き上がる状態となる。つまシ
、樹脂封止ケース２１とシュートレール１４との接触面
積は極めて小さく設定されるようになシ、その相互間の
摩擦係数は従来に比較して大幅に低下するようになる。That is, as shown in FIG. 3, when a semiconductor device configured in this manner is transported by, for example, a T-shaped chute rail 14, a resin-sealed case 2 is placed on the surface of the chute rail 14.
The main body of the resin-sealed case 2 should touch the chute rail 14 surface by the height of the protrusions 22h to 22e so that only the tips of the protrusions 22a to 22c formed on the back surface 21a come into contact with each other. It becomes a state where it floats up from the surface. The contact area between the tab, the resin-sealed case 21, and the chute rail 14 is set to be extremely small, and the coefficient of friction therebetween is significantly reduced compared to the prior art.
したがって、この半導体装置は、シュートレール１４上
を極めて小さな推進力で滑走し搬送されるようになるも
ので、シュートレールＪ４の傾斜角度を急角度に設定す
る必要はない。また、樹脂封止ケース２ノに突起状部２
２ａ〜２２ｃを形成したことによシ、ケース２１自体の
表面積が広げられ、放熱効率が向上するようになる。Therefore, this semiconductor device is transported by sliding on the chute rail 14 with an extremely small propulsive force, and there is no need to set the inclination angle of the chute rail J4 to a steep angle. In addition, a protrusion 2 is provided on the resin-sealed case 2.
By forming 2a to 22c, the surface area of the case 21 itself is expanded, and the heat dissipation efficiency is improved.
同、上記実施例では、突起状部２２ａ〜２２ｃを樹脂封
止ケース２ノ裏面部２１ｍの３ケ所に形成しているが、
第４図に示すように、この樹脂封止ケース２ノの裏面部
２１ａには、上記突起状部２２ａ〜２２ｃ以外に、多数
の小形突起状部２３ａ・、−・２３ｂ、・・・を形成し
、ケース２１自体の放熱効率をさらに高めるようにして
もよい。Similarly, in the above embodiment, the protruding portions 22a to 22c are formed at three locations on the back surface portion 21m of the resin-sealed case 2.
As shown in FIG. 4, in addition to the projections 22a to 22c, a large number of small projections 23a, 23b, . . . are formed on the back surface 21a of the resin-sealed case 2. However, the heat dissipation efficiency of the case 21 itself may be further improved.
以上のようにこの発明によれば、樹脂封止ケースの裏面
部に突起状部を形成するようにしたので、例えば半導体
装置検査工程において、多数の半導体装置を搬送するよ
うな場合でも、シュートレールの傾斜角度を急角度に設
定する必要なく、円滑に滑走し搬送することが可能とな
ると共に、この半導体装置自体の放熱効率を向上するこ
とができる。As described above, according to the present invention, since the protruding portion is formed on the back surface of the resin-sealed case, even when a large number of semiconductor devices are being transported in the semiconductor device inspection process, the chute rail can be easily used. It is not necessary to set the inclination angle of the semiconductor device to a steep angle, and it is possible to smoothly slide and transport the semiconductor device, and the heat dissipation efficiency of the semiconductor device itself can be improved.
成を示す図、第３図はこの半導体装置の搬送状態を示す
図、第４図はこの発明の他の実施例における下面部の構
成を示す図である。
１２ａ、１２ｂ・・・リードフレーム、２１・・・樹脂
封止ケース、２１ａ・・・ケース裏面部、２２ａ〜２２
ｃ・・・突起状部、２３ ａ Ｈ２３ｂ ＋・・・小形
突起状部。FIG. 3 is a diagram showing the state of transportation of this semiconductor device, and FIG. 4 is a diagram showing the configuration of the lower surface portion in another embodiment of the present invention. 12a, 12b...Lead frame, 21...Resin sealing case, 21a...Case back part, 22a-22
c... Projection, 23 a H23b +... Small projection.
Claims (1)
の電極に接続されるリードフレームを位置設定する樹脂
封止ケースの裏面部を少なくとも３ケ所の突起状部を有
する凹凸状面に形成したことを特徴とする半導体装置。The back side of the resin sealing case that seals the semiconductor chip on which the circuit network is formed and positions the lead frame connected to the electrodes of the circuit network is formed into an uneven surface having at least three protrusions. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8811183A JPS59213149A (en) | 1983-05-19 | 1983-05-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8811183A JPS59213149A (en) | 1983-05-19 | 1983-05-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59213149A true JPS59213149A (en) | 1984-12-03 |
Family
ID=13933769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8811183A Pending JPS59213149A (en) | 1983-05-19 | 1983-05-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59213149A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6197848U (en) * | 1984-11-30 | 1986-06-23 | ||
| US5563773A (en) * | 1991-11-15 | 1996-10-08 | Kabushiki Kaisha Toshiba | Semiconductor module having multiple insulation and wiring layers |
-
1983
- 1983-05-19 JP JP8811183A patent/JPS59213149A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6197848U (en) * | 1984-11-30 | 1986-06-23 | ||
| US5563773A (en) * | 1991-11-15 | 1996-10-08 | Kabushiki Kaisha Toshiba | Semiconductor module having multiple insulation and wiring layers |
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