JPS59212967A - Monitor system for runaway of program - Google Patents

Abstract

PURPOSE:To attain a monitor system for runaway of a program with no oversight by comparing the comparison data which serves as the final address of an executing program set at a comparison value setting circuit with an address signal delivered from a microprocessor. CONSTITUTION:The execution is started at the head address AOS of an initializing program PO prior to an executing program P1. The final instruction OPE in the program PO sets the value of the final address AIE of the program P1 within a comparison value setting circuit 1 as the comparison data via a data bus DB and then executes the program P1. Hereafter the comparison data is compared with an address signal AB1 delivered from a microprocessor CPU by a comparator 2 up to the address AIE. If the signal AB1 is larger than the comparison data of the circuit 1, the output signal 21 of the comparator 2 is delivered at L. While the output signal G31 of an NOR gate G3 is set at H. Thus a program runaway is decided, and a latch circuit 4 is set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a program runaway monitoring system for a system using a microprocessor.

[Prior art and its problems]

Generally, as a simple program runaway monitoring method for systems using microprocessors, the address signal output from the microprocessor is decoded, and the decoded signal, for example, a chip select signal that specifies the FROM number, is used to implement the program. The area, that is, the maximum possible area of the program that can be stored in the installed memory, in other words, the final address of the program that can be stored in the memory, and the unimplemented area, that is, the area that exceeds the final address, are determined, and the unimplemented area is identified. By the time I accessed it, it was considered a runaway program. However, in this method, the value of the final address for determining runaway is a unit of memory capacity determined by the number of FROMs used, and is larger than the final address of the program actually stored in it. It is not possible to monitor the area of the installed memory that has not been written to.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks and provide a new system that allows for complete monitoring.

[Key points of the invention]

According to the present invention, an initial setting program executed by a microprocessor prior to an execution program,
By comparing comparison data set in a programmable comparison value setting circuit as the final address of the execution program with an address signal output from the microprocessor each time each instruction statement of the execution program is read. The point is that it allows for leak-free monitoring of runaway behavior.

[Embodiments of the invention]

Next, the present invention will be explained based on FIGS. 1 and 2.

FIG. 1 shows an example of the configuration of the present invention. A CPU is a microcomputer as a central processing unit in a computer system, and this figure shows an example using an Intel 8085A. M is a memory such as PR, OM or RAM, and DC is a decode circuit that decodes the address signal ABI of the address bus AB and outputs a decode signal DC1 that addresses the comparison value setting circuit 1. The comparison value setting circuit 1 is connected to the data bus DB, and receives the decode signal DCI via the address signal ABI and the write signal function as a write control signal by the microprocessor CPU, and sets an address as arbitrary comparison data. Ru.

The output signal 11 of the comparison value setting circuit 1 is input to the comparison circuit 2, and is compared in magnitude with the value of the address bus AB (address signal ABI). NOT read signals R and D as read control signals output from the microprocessor CPU.
AND from the output signal Nil inverted by the element N1 and the status signal So, s1 of the microprocessor CPU.
Created through NO gate, microprocessor CP
The fetch signal FH indicating the timing at which U reads (fetches) each instruction statement is the output signal G21 through the NAND gate L, which is the output signal 2 of the comparator circuit 2.
1 and becomes an output signal G31 through the NOR gate G3, and is input to the latch circuit 4. The output signal 41 of the latch circuit 4 is input to the NOR gate G4.
The reset input signal 1 (E8IN) of the microprocessor CPU is output from the OR gate G4. An OR condition is taken at point 5a and is input to NOT element N2λ as output signal 51. Output signal N21 of NOT element N4
is input to the NOR gate G4, and NOT
It becomes an output signal N31 via element N3, and is inputted to the latch circuit 4 as a reset signal. Note that the reset signal RE8ET outputted when the microprocessor CPU is reset is input to the comparison value setting circuit 1 and resets the setting data in the comparison value setting circuit 1.

Next, the operation of the present invention will be explained with reference to an example of the configuration of the memory M shown in FIG. In the following explanation, IH "or 11" indicates logic High h, ILI or w Q
It is assumed that w means logic LOW.

Immediately after the power is turned on, the potential at point 5a is ILI because capacitor C1 is not charged, so the output signal N21 of NOT element N2 becomes lH1', and the reset input signal RESIN, which is the output signal of NOR element G4, becomes wLy, which causes the comparison value to become As will be described later, during the execution of the initial setting program, the value of the comparison data in the setting circuit 1 is set as the maximum possible address value from the comparison circuit 2 to prevent output of the output signal 21 as an abnormal signal. "11 ("FFFFH") is set as the initial value. Instead of using the hardware means described above, this initial value can be set by using the first command of the initial setting program (PO in Figure 2) described later. Software means may be used to write at least an address equal to or higher than the final address AOE of the initialization program as the initial value using +OPS or an earlier instruction.

Next, the execution of the program is the execution program (Fig. 2 Pi)
Prior to the execution program P1, the final unit 4 (oPE) in the initial setting program PO starts execution from the first address AO8 of the initial setting program (PO) provided corresponding to the execution program P1. The comparison value setting circuit 1 uses the value of the final address AIR of the program P1 as comparison data.
This is a command to write into. However, this write command may be placed in a step before the final unit 40PE in the initial setting program PO. In this way, after the last address AIE is set as comparison data in the comparison value setting circuit 1 via the data bus DB by executing the last unit+OPE, the start address AI8 of the execution program P1 is set.
Execution begins.

After this first address AIS, this setting value (comparison data), which is the value of the last address AIH, is outputted from the microprocessor CPU up to the last address AIE of the execution program P1. The comparison circuit 2 compares the address signal ABI with the address signal ABI. When the microprocessors C and PU are reading each instruction statement, that is, when the read signal RD is Ll,
And when the fetch signal FH is output as 1H'', the output signal G21 of the NAND gate 1C2 is ILI
Then, the NOR gate G3 is unlocked, and on the other hand, if the address signal ABI is thicker than the comparison data of the comparison value setting circuit 1, that is, the final address AIFlt, the output signal 21 of the comparison circuit 2 becomes l'L''. is output as N
The output signal G31 of the OR gate G3 becomes ILI, and the latch circuit 4 is set as a program runaway. The reason why the program is considered to have runaway is that in this case, the area beyond the final address AID in FIG. 2, which is the area where the program is not stored, up to the maximum address IFFFFHI has been accessed.

The above comparison is also performed during the execution of the initial setting program PO, but at this time, the set value in the comparison value setting circuit 1 (initial value - comparison data) is -F as described above.
FFF Hl (or at least the final address iowo
(above value), the output of 'L' from the comparator circuit 2 is blocked (or at least runaway detection is performed as in the case of the execution program PO).

Now, based on the above-mentioned setting of the latch circuit 4, its output signal 41 becomes wHw, which drives the reset input signal ESIN to active low ('L) via NOR and gate G4.
') to reset the microprocessor cPU.

In other words, the operation of the microprocessor CPU is stopped. The operation stop state is canceled by turning on the switch 5.

That is, at this time, the output signal 51 at point 5・a is l
J, 1, therefore, the output signal N21 of the NOT element N2 becomes 'H', and the output signal N31 of the NOT element N3 becomes 'Ll', resetting the latch circuit 4. As a result, the output signal 41 of the reset element 4 becomes '1L'. return.

After this, when switch 5 is turned off again, capacitor C1 is charged from the +5■ power supply via the resistance ratio 1, and point 5
The output signal 51 of a returns to "Hl", and the output signal N21 of NOT element N2 becomes ILI, which leads to NOR, Ku1-G.
The reset input signal RESIN as the output of 4 is 1H1
Returning to , the operation of the microprocessor CPU is started.

In this circuit, if the latch circuit 4 is deleted and the output signal G31 of the NOR gate G3 is directly applied to the NOR gate 4 as an input signal in place of the output signal 41 of the latch circuit 4, a reset input is input only at the moment of runaway detection. Signal RESIN
becomes "L", resulting in an instantaneous reset, that is, an automatic restart circuit configuration.

In addition, in the above explanation example, the microprocessor CPU is 8
085A was used, but since some other microprocessors directly output the fetch signal FH, if such a microprocessor is used, the fetch signal FH can be output directly.
ND gate G1 can be omitted.

〔Effect of the invention〕

According to the present invention, the final address of the execution program as a set value (comparison data) is set by the microprocessor in the comparison value setting circuit by an initial setting program corresponding to the execution program prior to the execution program; Since the address signal output from the microprocessor is compared each time each instruction statement is read, detailed runaway monitoring can be performed. Also, since the setting values are programmable in this way, even if a program is loaded from a floppy disk, etc., the stored program can be changed by changing the setting values as described above using the initial setting program that is paired with the execution program. Automatic monitoring can be performed according to the size of the area.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of the present invention, and FIG. 2 is a diagram showing an example of the configuration of a memory according to the invention. Code explanation

Claims (1)

[Claims] In a system including a central processing unit, a memory stores an execution program of the central processing unit, an initialization program that precedes the execution program and includes a final address of the execution program as data; Before executing the first instruction of the setting program, at least an address higher than the last address of the initial setting program is set via the initial value setting means or the central processing unit, and when the initial setting program is executed, the last address of the execution program is set. A comparison value setting means sets the address as comparison data via the central processing unit, and receives an output signal from the central processing unit to determine the time point at which the central processing unit reads each instruction statement of each program. a comparison abnormality detection means that inputs a fetch signal shown in the table, compares the address of the instruction statement with the comparison data each time the fetch signal is input, and outputs an abnormality signal when the address of the instruction statement exceeds the comparison data; A program runaway monitoring system comprising: reset signal output means for detecting the abnormal signal and providing a reset signal to the central processing unit.