JPS5921180B2 - hand tie memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor memory cell and a memory using the same.

Conventionally, the IMOST cells shown in Figures 1 to 3 have been proposed as suitable for high density (Reference 1972 ISSCC).
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As is well known, this cell also uses the capacitance between the inversion layer I and the electrode PL located directly above it via a thin oxide film (with a certain thickness) as the storage capacity of the memory cell. However, the drawback of this cell is that the word line W is formed of a single layer of metal, so if you try to apply a normal manufacturing process, the gate of the transistor Q called GM is formed after the data line D is formed by diffusion. It is necessary to use a mask for As a result, a thin oxide film with a mask alignment accuracy S of 11 is formed, resulting in a large capacitance between D and W. Therefore, the capacitance CD of the data line D increases. As we all know, CD
If Cs is large, Cs must be correspondingly large, and this is a factor in increasing the area of the memory cell. An object of the present invention is to improve the S/N ratio of a memory cell. In the present invention, the data line connected to the diffusion layer is formed of polysilicon, reducing the memory cell area and
The aim was to improve the N ratio. This will be explained in detail in Examples below. 4 and 5 are cross-sectional views of memory cells using the Si gate process. It is well known that the poly-Si used in the examples becomes conductive when impurities are implanted, and hereinafter, when poly-Si is referred to, it is assumed that the poly-Si is implanted with impurities. After forming the storage capacitor forming electrode PL with the first type of poly-Si and the word line W with the second type of poly-Si, the second type of poly-Si is formed.
Using a seed poly-Si formation mask, a diffusion region is formed in a self-aligned manner (it can also be equivalently formed by ion implantation).
Form D. After this, data line TAT is made using poly-Si etc.
Form A. Poly-Si is generally easier to microfabricate than Al. In other words, if you try to form a data line with Al, it will have a wide width, whereas with polyS
If a data line is formed using i, a narrow width line can be formed.
Since the IMOST cell semiconductor memory reads cell signals based on the relationship between the data line capacitance and the cell capacitance, narrowing the data line width means that the data line capacitance CD can be reduced. Become. That is, forming the data line with poly 51 has the effect of increasing the read signal and improving the S/N ratio. Furthermore, forming the data line with poly-Si has the effect that the area of the diffusion layer D of the MOST can be reduced.

That is, since poly-Si is easy to process, even if the area of the contact portion CT with the diffusion layer D is small, it can be processed so as to be embedded therein. As a result, the area of the contact portion CT may be small, and the area of the diffusion layer can also be made small. If the area of the diffusion layer is small, the noise coupled to the Si substrate through the diffusion layer can also be reduced, and the W. This has the effect of reducing the capacitance between 15D and 15D. It also has the effect of reducing soft errors caused by alpha rays. Furthermore, since the diffusion layer D is formed in a self-aligned manner, the coupling capacitance with WI::D (connected to DATA through contact CT) is extremely small, and therefore the capacitance of the data line can be made small. 6 and 7 are examples of other memory cells. This is an example in which D is diffused in a self-aligned manner using a mask for forming the gate of Q in FIG. 3, which is connected to the word line W in the same manner as above. A feature of this cell is that most of the data line is formed of a diffusion layer, whereas a part of the data line of the memory cell shown in FIGS. 5 and 6 is formed of a diffusion layer. The contact CT of W (5G) can be taken almost directly above the inversion layer forming Cs. In this case, the coupling capacitance between W and D is also extremely small, so the area occupied by the memory cell can be made small. T
.

The magnitude relationship between and be. If L is too small, Q characteristics (for example, punch-through breakdown voltage) may become poor. To avoid this, it is necessary to make the depth of D shallow so that there is no problem in terms of characteristics even if L becomes small. This can be easily accomplished by ion implantation. However, in general, in ion implantation,
Since the leakage current is large, ion implantation cannot be used in memory cells where ions are implanted at point J in FIG. 3, as is well known. This is because the charge stored in Cs disappears in a short time. In this regard, since the present invention does not require a special junction capacitance at the J point, even if ions are implanted into the memory array, there is no adverse effect on the refresh time or the like. In this case, if shallow ion implantation is performed, the sheet resistance forming the joint will increase, but peripheral circuit areas other than the array, where this resistance is particularly problematic, should be selected from the array area by deep ion implantation or diffusion. The advantages of this memory cell can be further utilized by changing the structure.

Another means to ensure that there is no problem in terms of characteristics even if L is small is as follows:
As is well known, the thin oxide film (
[1] The threshold voltage is selectively increased by implanting ions into the portion.

8 and 9 are examples in which the memory cell shown in FIG. 7 shares a contact CT with an adjacent memory cell. It is obvious that depending on the layout, a diffusion layer may exist in the DMC region in the cell shown in FIG. 7 as shown in FIG. 10.

A manufacturing process suitable for the above embodiment is shown in FIG. However, since the process of forming contacts is well known, it is omitted. That is, (1) first oxidize the P-type substrate 1 to form SiO2
A film 2 is formed.

2) Remove the SiO2 film 2 by photoetching.

3) Form SlO23.

4) Deposit polysilicon 4.

5) Form a SiO2 film 5.

6) Remove the necessary parts using photoetch.

7) Form the SlO2 film 6.

8) Deposit polysilicon 7.

9) After photo-etching, the diffusion layer 8 is formed in a self-aligned manner.

Thereafter, a data line is formed using poly-Si above the diffusion layer 8. According to the present invention, since the data line capacitance can be reduced in the 1M0ST cell, there is an effect that the S/N ratio is improved.

Furthermore, since the area of the diffusion layer region can be reduced, soft errors due to alpha rays can be reduced and coupling noise with the substrate can be avoided.

[Brief explanation of the drawing]

Figures 1 to 3 show conventional charge transfer type 1M0ST cells. Figures 4 to 10 show a charge transfer type 1M0ST according to an embodiment of the present invention.
cell. FIG. 11 shows the manufacturing process. W: word line,
PL: storage capacitor formation electrode, 1: inversion layer, S: mask alignment margin, D: p-n junction, TO, tl: thin oxide film, MC: memory cell, GM: gate formation mask, C
s: storage capacity, Q: transistor forming the memory cell, CD: data line capacitance, connection between Q and Cs, DATA
data line, L: channel length, CT: contact, CH: channel region, G: gate mask.

Claims (1)

[Claims] 1. Each memory cell includes a field effect transistor having a gate electrode connected to a word line, a source or drain electrode made of a diffusion layer connected to a data line, and a capacitive part for information storage connected to the field effect transistor. 1. A semiconductor memory comprising: a data line made of polysilicon.