JPS59211305A - Bias circuit - Google Patents

Bias circuit

Info

Publication number
JPS59211305A
JPS59211305A JP58085281A JP8528183A JPS59211305A JP S59211305 A JPS59211305 A JP S59211305A JP 58085281 A JP58085281 A JP 58085281A JP 8528183 A JP8528183 A JP 8528183A JP S59211305 A JPS59211305 A JP S59211305A
Authority
JP
Japan
Prior art keywords
circuit
transistor
bias
input terminal
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58085281A
Other languages
Japanese (ja)
Other versions
JPH0349207B2 (en
Inventor
Hisashi Sotokari
外狩 久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58085281A priority Critical patent/JPS59211305A/en
Publication of JPS59211305A publication Critical patent/JPS59211305A/en
Publication of JPH0349207B2 publication Critical patent/JPH0349207B2/ja
Granted legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To decrease the leakage component of an AC signal voltage by inserting an emitter follower circuit including a current mirror circuit between a DC power supply terminal and a DC bias input terminal of an amplifier as a DC bias circuit of the amplifier. CONSTITUTION:The current mirror circuit consisting of PNP transistors (TR) Q<3>, Q<5> and a bias supply circuit comprising the emitter follower consisting of an NPN TRQ<4> and a PNP TRQ<6> are provided between a DC bias input terminal (a) of voltage amplifiers 7, 9 and a common connecting point (b) of TRs Q<1>, Q<2>. Further, a voltage at a power supply terminal 2 is divided by resistors R<1>, R<2> and diodes Q<1>, Q<2> and a DC bias is given to an input terminal of the voltage amplifier through the emitter follower circuit comprising the TRs Q<4>, Q<6> and by connecting the input terminal 1 of the voltage amplifier 7 to a connecting point between the emitter of the TRQ<6> and the collector of the TRQ<5> via a resistor R<3>.

Description

【発明の詳細な説明】 (発明の属する技術分野) 本発明は電圧増幅器の直流のバイアス回路、特に集積回
路化に適したバイアス11:!4路に関するものである
DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a DC bias circuit for a voltage amplifier, particularly a bias circuit suitable for integration into an integrated circuit. It is related to the 4th road.

(従来技術) 第1図は、従来よく知られた直流バイアス回路である。(Conventional technology) FIG. 1 shows a conventionally well-known DC bias circuit.

これを説明すると* ’rh、’ d’A Q+r:子
2の■も圧が抵抗R1,R2によって抵抗分割され、抵
抗R□、1石の接続点4と増幅器70入力端1との1μ
]に抵4ノi:Raが接続されて増幅器7の入力端1へ
のi−&+流バイアスが与えられている。増幅器9につ
いても同和・の     □ことが言える。信号入力端
子6に与えられた交流入力信号鵬直流阻止用コンテしザ
C2?;l!Iして電圧増幅器7の入力端1 vC与え
られる。ここで、交流入力信号印加時における抵抗R1
,R2の接続点4への交流入力信号のもれ分■4 は以
下の(2)式で与えられ、一般的にコンデンサC+の容
量11jによって支配され、他増幅器9への彩管を無視
できる値に設寞される。
To explain this, *'rh,'d'A Q+r: The ■ voltage of the child 2 is divided by the resistors R1 and R2, and the resistor R□, the 1μ between the connection point 4 of the 1st resistor and the input terminal 1 of the amplifier 70
] is connected to a resistor 4 (i:Ra) to provide an i-&+ current bias to the input terminal 1 of the amplifier 7. The same thing can be said about amplifier 9 as well. Is the AC input signal applied to the signal input terminal 6 connected to the DC blocking circuit C2? ;l! I is given the input terminal 1 vC of the voltage amplifier 7. Here, resistance R1 when applying an AC input signal
, R2 to the connection point 4 is given by the following equation (2), and is generally controlled by the capacitance 11j of the capacitor C+, and the chromatic tube to the other amplifier 9 can be ignored. set to the value.

ここで、πは円周率、fは入力信号周波数、 CIは容
佑、値、 Z4は端子4から接地側を見たインピーダン
ス、  VIは交流入力信号電圧値を表わしている。た
たし、1着(ly7.器9全見ftインピーダンスは無
視できるぐらい大きいとする。実際には、−汐I]をあ
げると、f=IKHz 、CI=47μF、RI=R2
=10にΩでZn=3.39Ωとな9、R3=50にΩ
としで、v4中6.8X ] 0 ’ v+となる。
Here, π is pi, f is input signal frequency, CI is value, Z4 is impedance when looking at the ground side from terminal 4, and VI is AC input signal voltage value. Assume that the impedance is so large as to be negligible.In reality, -ShioI], f=IKHz, CI=47μF, RI=R2
= 10 with Ω, Zn = 3.39Ω, 9, R3 = 50 with Ω
Then, it becomes 6.8X] 0' v+ in v4.

ところで、集積回路においては、外部接続端子の増加お
よび外部付加部品(集積回路の外部接続端子に@続され
て、集積回路と共に回路全構成する単体部品ンの増加は
、その価格、形状において。
Incidentally, in integrated circuits, the increase in the number of external connection terminals and the increase in the number of external additional parts (single components that are connected to the external connection terminals of the integrated circuit and make up the entire circuit together with the integrated circuit) have affected their prices and shapes.

大きな欠点である。第1図の回路を集積回路化した場合
、破線5の内側が集積回路化され、1,2゜3.4,8
,10.および11が外部接続端子とな9、コンデンサ
CI’、 C2、C375外部伺加部品となる。つまり
外部接続端子は7個、外部付加部品は3個となる。
This is a big drawback. When the circuit in Fig. 1 is integrated, the area inside the broken line 5 is integrated, and
,10. and 11 are external connection terminals, and 9 and capacitors CI', C2, and C375 are externally added parts. In other words, there are seven external connection terminals and three external additional parts.

次に、他の従来例として、第2図を薄明する。Next, as another conventional example, FIG. 2 will be shown in twilight.

第2図において、第1図と対応する部分妹同一番号で示
し、その故明は省略する。槓1,1図と醒なる点は、電
源端子2と接地端子3間に直列接h″じされた抵抗Ru
 、 R2に、コレクターベース知絡のトランジスタQ
□lQ2金的夕1]帰U1.シた点だけで、jljj1
作状況は、前記第1図で薄明したのと同等でめる。
In FIG. 2, parts corresponding to those in FIG. 1 are indicated by the same numbers, and the explanation thereof will be omitted. The point that stands out from Figures 1 and 1 is the resistor Ru connected in series between the power supply terminal 2 and the ground terminal 3.
, R2 is a collector-base connected transistor Q.
□lQ2 Kinteki 1] Return U1. Just the point, jljj1
The cropping conditions are the same as in the twilight shown in Figure 1 above.

第2図のr1路ケ集枦化した穂゛1合、イνヴ1tlj
5の内側の部分が東伽回路化される。第1(ン1と同4
)’y Ifこ1,2゜3.4.8.10および11が
外部接す酪^)子となりコンデンサCI、C2,C3が
外部イに1’ 7Jll TSI−品となる。
In Figure 2, the r1 path has become a condensation, and the eve1tlj
The inner part of 5 is converted into a Toga circuit. 1st (n 1 and 4
)'y If this 1, 2° 3.4.8.10 and 11 are connected to the outside, capacitors CI, C2, and C3 are connected to the outside.

つまり外部勿和″r、シ1′1.1子は7個、外81;
イτ]加部品は3個となる。
In other words, there are 7 external children, 81 outside;
τ] The number of processed parts is three.

(発明の目的) 本発明の目的は1%L圧粕幅器の直流バイアス91、船
端電圧が電圧増幅器への交流入力信号印加時に変動する
ことf椿力少なくシ、かつ4に=4)1回路化において
外部接’f5e Qm子と外部付加部品を削減したバイ
アス回路全提供することにある。
(Object of the Invention) The object of the present invention is to reduce the fluctuation of the DC bias 91 and the terminal voltage of the 1% L pressure lees width meter when applying an AC input signal to the voltage amplifier, and to reduce the power to 4 = 4) The object of the present invention is to provide a complete bias circuit in which external connections and external additional parts are reduced in one circuit.

(発明の構成) 本発明の回路は、少くとも一個の電圧増1幅、器を有し
該電圧増幅器Iの入力嬬子へrlV流、バイアスを供船
するバイアス巨1路において、カレントミラー回路ケ横
越する一導ル、型の第1.&!2のトランジスタと、エ
ミッタを前記カレントミラー回路のコレクタ出力に接細
−導7ネ19の第3のトランジスタと、 −エミッタを
前記第3のトランジスタのペースに。
(Structure of the Invention) The circuit of the present invention includes a current mirror circuit in a bias circuit which has at least one voltage amplifier and supplies an rlV current and a bias to the input signal of the voltage amplifier I. The first guide that goes beyond the curve, the first type. &! 2 transistors, with their emitters connected to the collector output of said current mirror circuit - a third transistor with conductors 7 and 19, - their emitters connected to the collector outputs of said third transistors;

コレクタを前記カレントミラー回路のコレクタ入力に接
続された反対脚車型の第4のトランジスタとを含み、該
第4のトランジスタのベースを直流バイアスの入力端、
前記カレントミラー回路のコレクタ出力と前記第゛3の
トランジスタのエミッタの共i11’、]接=点V+自
流バイアスの出力喘とすることからなっている。
a fourth transistor of an opposite caster type, the collector of which is connected to the collector input of the current mirror circuit, the base of the fourth transistor being a DC bias input terminal;
The collector output of the current mirror circuit and the emitter of the third transistor are jointly i11', and the contact=point V+the output of the free current bias.

実施例 以下本づ6明について1図面を参照して肛細に説明する
EXAMPLES Below, the present invention will be described in detail with reference to one drawing.

第3図は1本発明の一実が11」を示す回路図である。FIG. 3 is a circuit diagram showing one embodiment of the present invention.

なお第1図、第2図と対応する部分は同一番号で示して
、その鯵明は省略する。
Note that parts corresponding to those in FIG. 1 and FIG. 2 are indicated by the same numbers, and the numbers are omitted.

第3図において、第2図の従来レリと異なる点は、電圧
増幅器7,9の直流、バイアス入力端■と、トランジス
タQl、 Q2 の共辿接続点@との間に、PNP)ラ
ンジスタQa 、 Q5  から構成されるカレントミ
ラー回路と、NPNトランジスタQ4とPNI)トラン
ジスタQ6のエミッタホロワからなるノ(イアス供給回
路全σけたことにある。
In FIG. 3, the difference from the conventional relay shown in FIG. 2 is that PNP) transistors Qa, A current mirror circuit consisting of a transistor Q5 and an emitter follower of an NPN transistor Q4 and a PNI transistor Q6 are provided.

第3図において、電源端子2の”rM LEが、抵抗R
+ 、 R2とタイオードQJ、Q2 に工9分割され
、分割点よりトランジスタQ4.Q6 のエミッタホロ
ワ回路を介して、トランジスタQ6のエミッタとトラン
ジスタQ5のコレクタとの交点に電圧増幅器70入力端
1が抵抗Raを介して体軌−され。
In Figure 3, "rM LE" of power supply terminal 2 is
+, R2 and diode QJ, Q2 are divided into 9 parts, and transistor Q4. The input terminal 1 of the voltage amplifier 70 is connected to the intersection of the emitter of the transistor Q6 and the collector of the transistor Q5 via the emitter follower circuit of the transistor Q6 via a resistor Ra.

電圧増幅器7の入力端1への1り流バイアスが与えられ
る。e+41圧増幅器9についても同4〉砦なことが官
える。
A single current bias to the input terminal 1 of the voltage amplifier 7 is provided. The same holds true for the e+41 pressure amplifier 9.

信号入力端子6に与えられた交流入力信号は、直流阻止
用コンデンサC2を介して電圧増幅器7の入力端1に与
えられる。ここで、交流入力信号印加時におけるトラン
ジスタQ5のコレクタ、トランジスタQ6のエミッタ及
び抵抗Rs、R4との交虚((R1点にの交流入力信号
のもれ分v 、/は以下の(4)式で与えられる。
The AC input signal applied to the signal input terminal 6 is applied to the input terminal 1 of the voltage amplifier 7 via the DC blocking capacitor C2. Here, when the AC input signal is applied, the collector of the transistor Q5, the emitter of the transistor Q6, the resistor Rs, the intersection with R4 ((the leakage of the AC input signal to the R1 point v, / is the following equation (4) is given by

・・・・・・(3) ここで、 ZQ5i’! )ランジスタQ5 の出力イ
ンピーダンス、γ11Q6ハトランジスタQ6のエミッ
タ抵抗、  hFEQ4.hFEQ6はトランジスタQ
4.Q6の′tピ流増幅1率、z4/はトランジスタQ
4のエミッタかhFEQ4 、 hFEQ6 は100
前後でγ。、6は数Ω前後であるため24′はトランジ
スタQ6のエミッタ抵抗幅器9への彩管を錘視できるよ
うにR3の抵抗顧を大きく設定ブーる。抵抗R4に陽1
しても回ト)−である。実際には、−例ケあげると、Z
4′中310゜R3=50にΩとして、v 、 /キロ
、25XIO’v、  となり、容易に従来回路よりも
もれ分v 、 /全小さくできる。
・・・・・・(3) Here, ZQ5i'! ) Output impedance of transistor Q5, γ11Q6, emitter resistance of transistor Q6, hFEQ4. hFEQ6 is transistor Q
4. Q6's current amplification rate, z4/ is transistor Q
4 emitters hFEQ4, hFEQ6 is 100
γ before and after. , 6 are around several ohms, so the resistance value of R3 is set large so that the resistance value of 24' can be seen from the emitter resistance amplifier 9 of the transistor Q6. Positive 1 to resistor R4
Even if it is, it is -. In fact, - to give an example, Z
When Ω is set to 310°R3=50 in 4', v,/km, 25XIO'v, can be obtained, and the leakage v,/total can be easily made smaller than that of the conventional circuit.

次に第4図に他の実:l/Iii 1+llの回路図を
示す。第4図において、;J’−3図と相醒なる点U、
PNP)ランジスタ’tNPNトランジスタに、N1)
Nlランジスタ(i−PNP)ランジスタ代えた点で、
回路す!11作状況+′i第3図で示したのと同様であ
る。
Next, FIG. 4 shows a circuit diagram of another example: l/Iii 1+ll. In Figure 4, the point U that coincides with Figure J'-3,
PNP) transistor'tNPN transistor, N1)
By replacing the Nl transistor (i-PNP) transistor,
Circuit! 11 production situation +'i It is the same as shown in Fig. 3.

ここで、本発明ケ東槓回1硲化した」い合、第3図。Here, the present invention has been integrated into one embodiment, as shown in FIG.

第4図に示すように破豚5の内側が月相(L11路化さ
れ、第1図1.第21囚の従来例に比して外部接糾☆N
V子1個、外部付加部品1イIL′1jをf:l117
+・kした441回11?、の提供が可能である。
As shown in Fig. 4, the inside of the broken pig 5 is converted into a lunar phase (L11 path), and compared to the conventional example of the 21st prisoner in Fig.
1 V element, 1 external additional part IL'1j, f:l117
+・k 441 times 11? , can be provided.

(発明の効果) 以上詳細に6W明したとおり、本づれ明によれば、増幅
器のIC原流747回路として1向流′市源端子と増幅
器の直がしくイアス入力斡、1間に′dt流ミラー回路
を含んだエミッタホロワ回路全挿入しているので、交流
信号電圧のもれ分子極めて少くして、かつ外部接続喘子
、外部付加部品の少ない集積回路化に適したバイアス回
#Sを提供することができる。
(Effects of the Invention) As explained in detail above, according to the present invention, as the IC source 747 circuit of the amplifier, there is a Since the emitter follower circuit including the current mirror circuit is fully inserted, the leakage molecules of the AC signal voltage are extremely small, and the bias circuit #S is suitable for integrated circuits with few external connection terminals and external additional parts. can do.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は、従来例の回路図、第3図は本発明
の一実施例の回路図、第4図は本発明の仙の実雄例の回
路図である。 図において、1,6.11.12・・・・・・入力端子
。 2・・・・・・電椋端子、3・・・・・・接地端子、4
・・・・・・バイアス端子、訃・・・・・集積回路化部
分、7,9・・・・・・電圧増幅器、8.10・・・・
・・出力端子、R1−R5・・・・・・抵抗。 C□〜C3・・・・・・コンデンサ、Ql、Q2.Q4
.Q□。、Q□1゜Q1□・・・・・・NPN)ランジ
スタ+ Q3 + Q61 Ql + Q7 rQ8.
Q、・・・・・・PNP )ランジスタ。 I71ζ 千 1 旧 タナレ イ、 工2]    上〜6
1 and 2 are circuit diagrams of a conventional example, FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is a circuit diagram of an actual example of the present invention. In the figure, 1, 6, 11, 12...input terminals. 2...Electric terminal, 3...Grounding terminal, 4
...Bias terminal, ...Integrated circuit part, 7,9...Voltage amplifier, 8.10...
...Output terminal, R1-R5...Resistance. C□~C3... Capacitor, Ql, Q2. Q4
.. Q□. , Q□1゜Q1□...NPN) transistor + Q3 + Q61 Ql + Q7 rQ8.
Q,...PNP) transistor. I71ζ 1,000 1 Old Tanarei, Engineering 2] 1~6

Claims (1)

【特許請求の範囲】 少くとも一個の電圧増幅器分有し該電圧増幅姦解の入力
端へ1〔流バイアスケ供給する。<イアス回路において
、カレントミラー回路全構成する一導電型の第1.第2
のトランジスタと、エミッタを前記カレントミラー回路
のコレクタ出力に接続された一導電型の第3のトランジ
スタと、エミッタを前記第3のトランジスタのベースに
コレクタ?前記カレントミラー回路のコレクタ入力に接
続された反対導電型の第4のトランジスタとを含み。 該第4のトランジスタのベースを直流)くイアスの入力
端、前記カレントミラー回路のコレクタ出カド前記第3
のトランジスタのエミッタの共通接続点を直流バイアス
の出力端とすることを特徴とするバイアス回路。
[Scope of Claims] It has at least one voltage amplifier and supplies one current bias voltage to the input terminal of the voltage amplifier. <In the IAS circuit, the first . Second
a third transistor of one conductivity type whose emitter is connected to the collector output of the current mirror circuit, and whose emitter is connected to the base of the third transistor and the collector output of the current mirror circuit. a fourth transistor of an opposite conductivity type connected to a collector input of the current mirror circuit. The base of the fourth transistor is connected to the input terminal of the input terminal (DC) of the fourth transistor, and the collector output terminal of the current mirror circuit is connected to the third transistor.
A bias circuit characterized in that a common connection point of the emitters of the transistors is used as a DC bias output terminal.
JP58085281A 1983-05-16 1983-05-16 Bias circuit Granted JPS59211305A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58085281A JPS59211305A (en) 1983-05-16 1983-05-16 Bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58085281A JPS59211305A (en) 1983-05-16 1983-05-16 Bias circuit

Publications (2)

Publication Number Publication Date
JPS59211305A true JPS59211305A (en) 1984-11-30
JPH0349207B2 JPH0349207B2 (en) 1991-07-26

Family

ID=13854180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58085281A Granted JPS59211305A (en) 1983-05-16 1983-05-16 Bias circuit

Country Status (1)

Country Link
JP (1) JPS59211305A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216504A (en) * 1985-03-22 1986-09-26 Toshiba Corp Reference potential generating circuit for amplifier circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS555883A (en) * 1978-06-30 1980-01-17 Nippon Signal Co Ltd:The Method of driving exothermic element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS555883A (en) * 1978-06-30 1980-01-17 Nippon Signal Co Ltd:The Method of driving exothermic element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216504A (en) * 1985-03-22 1986-09-26 Toshiba Corp Reference potential generating circuit for amplifier circuit

Also Published As

Publication number Publication date
JPH0349207B2 (en) 1991-07-26

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