JPS5921112B2 - address detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address detection device suitable for use in an editing device, etc., and is capable of always specifying an address accurately.

In order to detect the position of the magnetic tape in a conventional editing device, an SMPTE time code signal is deep-recorded in advance on the magnetic tape 1, and the position of the magnetic tape 1 is known by detecting this SMPTE time code signal. something is proposed.

This SMPTE time code signal is 1 as shown in Figure 2.
The frame period F is one word period, and the number of seconds, minutes, and hours of the frame are expressed by digital signals in this one word period.

In this case, 30 frames can be set to 1 second, 60 seconds to 1 minute, and 60 minutes to 1 hour. This SMPTE
A time code signal is deeply recorded on a time code track 2 of a magnetic tape 1 as shown in FIG.

In this case, since deep recording is performed, the SMPTE time code signal will not be erased even if the high frequency signal, ie, the video signal, is erased.

In this FIG. 1, 3 is a video signal track, and in this example, one frame of video signal is recorded on this one video signal track, and 4 is a control pulse track recorded on a control pulse track 4a. This control pulse 4 is a pulse, and this control pulse 4 is one pulse for one video signal track.
recorded. Further, 5 is an audio track on which an audio signal is recorded. In the case of a device that detects an address by detecting a SNPTE time code signal recorded in advance on a conventional magnetic tape, it is possible to know the absolute address in normal times, so it is possible to specify the address very well. ,
When the running speed of the magnetic tape is slow, for example, when the running speed is less than 1 during normal operation, use this SMPTE.
If the MPTE time code signal is not recorded or the SMPTE time code signal cannot be recorded for some reason, there is a drawback that the address of the magnetic tape cannot be specified.

5 In view of these points, the present invention aims to eliminate the above-mentioned drawbacks.

Hereinafter, one embodiment of the address detection device of the present invention will be explained with reference to FIG.

In this Figure 3, 1 is ■0SMPT as shown in Figure 1.
A magnetic tape is shown having a time code track 2 on which an E time code signal is recorded, a video signal track 3 on which a video signal is recorded, a control pulse track 4a on which a control pulse 4 is recorded, and an audio track 5.

Reference numeral 6 indicates an SMPTE time code signal reproducing head for reproducing the SNPTE time code signal arranged corresponding to the time code track 2 of this 35 magnetic tape 1. is supplied to the time code reading device 8 via the time code reproducing amplifier 7.

In this time code reading device 8, SMPTE
The time code signal is converted into a BCD code and supplied to the signal selection circuit 9, and it is determined whether the SMPTE time code signal is present and whether it can be determined, and a determination signal is obtained at this terminal 8a. In this case, a signal for one word, that is, a signal of 8 digits, or 32 bits, is supplied in parallel from the time code reading device 8 to the signal selection circuit 9. The content of this signal is 1 of the number of frames.
1 digit for the digit, 1 digit for the tens digit, 1 digit for the second
1 digit for the digit, 1 digit for the tens digit, 1/10 digit
1 digit for the digit, 1 digit for the tens digit, 1 digit for the hour
The digit is one digit, and the tens digit is one digit.
The signal selection circuit 9 is designed to obtain a switching signal for switching the switch circuit 10 as a discrimination signal when the SMPTE time code signal is absent or cannot be determined. Reference numeral 11 denotes a control pulse generating circuit which is configured such that one digit pulse is obtained every four clock pulses at the first output terminal 11a of the control pulse generating circuit 11, and a digit pulse and a digit pulse are obtained at the second output terminal 11b. The synchronization is such that one word pulse is obtained every 36 clock pulses or every 9 digits. The digit pulse obtained at the first output terminal 11a is supplied to the signal selection circuit 9, and the 4-bit signal sequentially selected for each digit pulse is sent to the switch circuit 1 in parallel.
0 to one input side. The 4-bit parallel signal obtained at the output side of this switch circuit 10 is supplied in parallel to the parallel input terminal of a 4-bit shift register 12. The output signal obtained at the serial output terminal of this 4-bit shift register 12 is supplied to a 28-bit shift register 13. The output side of this 28-bit shift register 13 is supplied to the serial input terminal of a 4-bit shift register 12 via an adder/subtractor circuit 14. In this case, the addition/subtraction circuit 14 is constituted by a 4-bit shift register. The 4-bit shift register 12, the 28-bit shift register 13, and the addition/subtraction circuit 14 constitute an accumulator. Further, 15 corresponds to the control pulse track 4a of the magnetic tape 1, and the SMPTE
A control pulse reproducing head disposed at a position corresponding to the time code signal reproducing head 6 is shown, and the control pulse 4 regenerated by the control pulse reproducing head 15 is transmitted to the control pulse reproducing amplifier 16.
The signal is supplied to the synchronization circuit 17 via.

Further, the word pulse obtained at the second output terminal 11b of the control pulse generation circuit 11 is supplied to the synchronization circuit 17.
This synchronization circuit 17 is designed to synchronize this control pulse 4 with a signal circulating through the shift registers 12 and 13. The control pulse 4 obtained at the output side of the synchronization circuit 17 is supplied to the addition/subtraction signal supply terminal of the addition/subtraction circuit 14 . In this case, in the addition/subtraction circuit 14, the control pulse 4 is used to convert the 1 digit of the frame number into a digital signal in which 1 is added in decimal notation.
In addition, the rear 3-bit signals W, W, W3 of the 4-bit shift register 12 and the first bit signal W4 of the addition/subtraction circuit 14 are supplied in parallel to the correction detection device 18, and the digits of the frame number and seconds are supplied in parallel. It is detected whether a digit, minute digit, etc. is required, and this detection result is supplied to the correction pattern signal generation circuit 19 in synchronization with the digital pulse, and the correction pattern signal generation circuit 19 of C generates a 4-bit signal. A predetermined correction pattern signal is generated, and this 4-bit correction pattern signal is supplied to the other input side of the switch circuit 10 in parallel. In this switch circuit 10, when an SMPTE time code signal is present, the 4-bit signal selected by the signal selection circuit 9 is supplied to the 4-bit shift register 12, and the 4-bit signal is changed depending on the selected 4-bit signal. The contents of the shift register 12 are changed. Also, when there is no SMPTE time code signal or it cannot be determined, the correction pattern signal from the correction pattern signal generation circuit 19 is
The correction pattern signal is sent to the 4-bit shift register 12 every digit pulse, and the stored contents of the 4-bit shift register 12 are changed to a predetermined value based on this correction pattern signal. Further, the signal obtained at the output side of the 28-bit shift register 13 is displayed on a predetermined display device, and various control signals are obtained from the signal obtained at the output side. Since the present invention is constructed as described above, under normal conditions, the SMPTE time code signal reproduced by the SMPTE time code signal reproduction head 6 is transferred to the shift register 1.
2 and 13, thereby knowing the absolute address and making it possible to specify the address accurately.

In this case, the control pulse 4 regenerated by the control pulse regeneration head 15 is supplied to the addition/subtraction circuit 14, but the stored contents of the 4-bit shift register 12 depend on the 4-bit signal selected by the signal selection circuit 9. Therefore, the existence of this control pulse 4 does not affect it in any way. Also, the running speed of the magnetic tape 1 is slow SM
When it becomes impossible to judge the PTE time code signal,
Or when this SMPTE time code signal is not recorded on the magnetic tape 1 or when it is not recorded, S
The MPTE time code signal is sent to shift registers 12 and 1.
At this time, the control pulse 4 regenerated by the control pulse reproducing head 15 is supplied to the adder/subtractor circuit 14, which counts the control pulse 4 and receives the correction from the correction pattern signal generation circuit 19. The pattern signal is supplied to the 4-bit shift register 12, and the count signal of the control pulse 4 is converted into an SMPTE time code and displayed, so that the address can be specified accurately at this time as well.

As described above, according to the present invention, the SMPTE time code signal is detected and the control pulse 4 is counted, so when the tape running speed becomes extremely slow and it becomes impossible to determine the SMPTE time code signal. Even when this SMPTE time code signal does not exist or cannot be inserted, address designation can be performed by counting the control pulses 4.

Furthermore, according to the present invention, even if there are times when both the SMPTE time code signal and the control pulse 4 cannot be detected, even if the SMPTE time code signal is detected once and only the control pulse 4 can be counted thereafter, the correct absolute address can be determined. There are benefits to knowing. In the above-described embodiment, an example of specifying an address on the magnetic tape 1 has been described, but it goes without saying that the present invention can be applied to specifying an address on a recording tape by other means.

Although SMPTE time code signals are used in the embodiments described above, it will be appreciated that other time code signals may be used instead. Furthermore, it goes without saying that the present invention is not limited to the above-mentioned embodiments, and can take various other configurations without departing from the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a magnetic tape used in the present invention;
FIG. 2 is a diagram for explaining the present invention, and FIG. 3 is a configuration diagram showing an embodiment of the address detection device of the present invention. 1 is a magnetic tape, 2 is a time code track, 4a is a control pulse track, 6 is a time code signal reproducing head, 8 is a time code reader, 9 is a signal selection circuit, 10 is a switch circuit, 12 is a 4-bit shift 13 is a 28-bit shift register, 14 is an addition/subtraction circuit, 15 is a control pulse regeneration head,
19 is a correction pattern signal generation circuit.

Claims (1)

[Claims] 1. In an address detection device having an accumulator that changes the stored contents depending on the time code signal recorded on the tape, the stored time code can also be changed by the control pulse recorded on the tape. An address detection device characterized in that the content stored in the accumulator can be changed according to the rules of the signal.