JPS6139981A - Time code signal recording method - Google Patents

Abstract

PURPOSE:To decrease editing errors at the time of editing a video tape by controling data of a bit for a user so that biphase modulation may be executed and the number of bits of data ''1'' or ''0'' in time code data of one frame may be a constant value. CONSTITUTION:A time code generating circuit 1 sends a frame address corresponding to an image signal to be recorded to a video tape recorder to a data control circuit part 2. The frame address, for example, is installed as a pair in which a word for address information and a word for a user are alternately distributed, and the remainder is a word for synchronization. the circuit part 2 controls the data of a bit for a user so that the number of data ''1'' or ''0'' can be a constant value during a frame period. The controlled data are stored in a memory 3, and after that, biphase mark modulation is executed by a biphase modulation circuit 4 and the data are outputed from an output terminal 5. Thus, the nearly precise time code data can be obtained and editing errors can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for recording time code signals used, for example, in videotape editing, and in particular to a method for recording time code signals that are biphase modulated and in an l-frame format. The present invention relates to a method for recording a time code signal that stores user bits.

(Prior Art) When editing images recorded by a video tape recorder, it has been conventional to record a time code signal as an address signal on the tape in advance, and edit while reading this time code signal. This time code is known as the longitudinal time code (so-called L
TC) and a vertical interval time code (so-called VITC) recorded in a vertical synchronization interval on a video track, both of which contain a kind of address information indicating hours, minutes, seconds, and frames.

Here, a so-called bi-phase modulation method or a digital FM method is adopted as a modulation method for the LTC signal. This modulation method has a transition (inversion or transition) for the bit clock at the boundary of each data bit of the signal, and also has a transition at the center of the bit period depending on the value of each data bit. This is a self-clocking modulation method. In general, a biphase mark modulation method is known that has a transition at the center of the bit period only when the value of each data bit is 11+''; There are also biphase space modulation schemes that have transitions only when in the middle of the bit period. Since such a nosophase modulation method includes a clock signal component in the signal, it can generally be said to be a modulation method that is resistant to fluctuations in the time axis direction of the signal, so-called jitter.

[Problems to be solved by the invention] ``By the way, when editing a videotape, there are various playback modes such as fast forwarding, rewinding, slow motion playback, quick motion playback, still image playback, etc. It is necessary to frequently switch and select the LTC, the tape running speed has a wide variation range, and the acceleration applied to the tape at the time of mode switching may make it impossible to read the LTC accurately. When the tape running speed fluctuates significantly, for example, the time axis of the bi-phase mark modulated signal is compressed to nearly %, causing data II 0" to be misread as °'1", or vice versa. to 2
This is because "Ill" may be mistakenly read as "0" due to being expanded nearly twice as much, and it is difficult to reliably detect such an error.

Here, although the editing point of the videotape is determined according to the above-mentioned time code data, it is desirable to read the LTC signal without error, but furthermore, if a reading error occurs, In order to prevent a fatal negative effect, so-called editing error, in which an editing point is determined based on this incorrect data, it is extremely important to reliably detect reading errors.

Furthermore, LTC has a data format of, for example, 1 frame 80 bits, and one set of time code data can be obtained in units of this frame, but a synchronization word is used to detect the period of this 1 frame. teeth,
It consists of a specific data pattern that does not occur in other data parts, for example, 12 consecutive Tadar "1"s, and if this synchronization word is read incorrectly, all 80 bits of data will be incorrect. This synchronization word part consists of the above 12 consecutive data “before and after 1°” o o
'",'"O'l".

There are 16 bits including 16 bits, and if a reading error occurs during this period, all the data in one frame may become erroneous data, and the probability of a reading error occurring increases accordingly.

The present invention has been made in view of the above-mentioned circumstances, and it is possible to reliably detect the occurrence of reading errors in LTC signals when acceleration is applied to the tape, and to detect incorrect time code data. It is an object of the present invention to provide a time code signal recording method which can effectively prevent editing mistakes caused by the above and which can detect frame periods more reliably.

[Means for solving problems]

A feature of the time code signal recording method according to the present invention is that when recording a time code signal that has user bits in the data format of one frame and is biphasically modulated, The object of this invention is to control the data of the user bits so that the number of bits or the number of data "'1°" or "0°" in the time code data becomes a constant value.

More specifically, for example, in the frame data formant, a plurality of pairs (for example, 8 pairs) of address information words and user words each having a certain number of bits (for example, 4 bits) are arranged alternately, The number of Teda "1°" in the remaining part (for example, the frame synchronization word part) is always constant (
For example, 13), by placing the complement of the binary data of each of the address information words in the corresponding or adjacent user words, a pair of address information words that correspond to each other and The number of data "1" included in the user word can always be controlled to a constant value (for example, 4), and the number of data "1" in an l frame can be controlled to a constant value (for example, 45). I can do it.

[Two effects] As described above, by controlling the number of data 1°1°° (or "°0°") in an l frame to a constant value, for example 45, and performing biphase mark modulation, for example, , the number of transitions (inversions or transitions) of the obtained time code signal is constant, for example 125.

Therefore, when the time code signal is reproduced, the tape running speed changes rapidly and acceleration is applied, and the time axis of the reproduced signal changes by % or nearly twice, and the data ``0'' changes to 1 degree or 1 degree. Even if 1"° is erroneously read in II OII, the frame period can be detected accurately by counting the number of signal transitions.Also, the frame period can be accurately detected by counting the number of signal transitions. It is possible to reliably detect reading errors.In other words, while the number of data items within an l frame period is constant (e.g. 80 pieces), the data “0” of the biphase mark modulated signal is changed to °゛l゛. If you misread it as °, then l
The number of data between frames (for example, 125 transitions) decreases, and if II Ill is misread as °"0, the number of data increases, so make sure that the read data is incorrect. The current timecode data can also be calculated by counting the frame period based on (the address information of) the correct timecode data immediately before the reading error occurred. By making each data of a pair of address information word and user word complementary to each other as in the example, if a reading error occurs in part of the synchronization word, the frame period can be changed by the above 125 count. If each pair of address information word and user word is detected and the complement relationship between them is correct, it can be confirmed that the address information is correct, and as a result, it is possible to reduce the probability of reading errors. .

〔Example〕

An embodiment of the time code signal recording method according to the present invention will be described below with reference to the drawings.

First, FIG. 1 is a block circuit diagram showing a configuration example of a time code signal recording side applied to a time code signal recording method as an embodiment of the present invention.

Referring to FIG. 1, the time code generation circuit 1 expresses the frame address corresponding to the video signal to be recorded on the video tape recorder using, for example, frames, seconds, minutes, and hours. Address information data is output as, for example, 4-bit parallel data. The above address information data from the time code generation circuit 1 is sent to the data control circuit section 2, which is the main part of the present invention, and the data control circuit section 2 generates the data ladder °1" (or +1011) during one frame period. ) is controlled to be constant and sent to a storage means, so-called memory 3.The time code data read out from the memory 3 is subjected to, for example, bi-phase mark modulation by a bi-phase modulation circuit 4, and Time code (so-called L
TC) signal and is taken out from the output terminal 5.

By the way, the above-mentioned longitudinal time code (so-called LTC)
) is defined as SMPTE time code or EBU time code, and has a frame data format as shown in Figure 2.
A total of 80 bits up to 9) are allocated. The bit period is 1/80 of the frame period, and the frame data is continuous with the previous and subsequent frame data, with the bit number 0 of the current frame following hint number 79 of the previous frame. In addition, address information words of a certain number of bits (for example, 4 bits) and user words are arranged alternately starting from bit number 0 at the beginning of one frame, and these address information words and user words are arranged alternately. A total of 8 pairs, ie, a total of 64 bits, are arranged to form a part for various data, and the remaining 16 bits are a word for frame synchronization. Each word of 4 bits for the above address information contains a binary code (so-called B
CD code), the ones digit of the frame, the IO digit, the seconds digit, the tens digit, the minutes digit, the tens digit, the hour digit, and the IO digit are sequentially determined. Each is displayed separately, and in SMPTE time code, 0 to 2
9 frames.

It is possible to express θ~59 seconds, 0~59 minutes, and 0~23 hours. Note that in the case of EBU time code, the frame values expressed are 0 to 24 frames. Here, for each lO digit, all 4 bits of one word are not required, and the 10's digit of the frame, second, minute, and hour can be expressed with 2 or 3 bits, so the remaining bits can be used for other bits. information is assigned. For example, it is sufficient to represent 0, 1.2 for the word in the tens place of the frame, so two bits with bit numbers 8 and 9 are used to represent the numerical value in the tens place of the frame, and the remaining 2 bits are used to represent the numerical value in the tens place of the frame. Of the bits, the focus bit number 10 is used for the drop frame bit, and the bit number 11 is used for the color frame hit. Next, 8 for the above user.
The 32 bits allocated to each word are left to the user's discretion as user bits (so-called user's bits). The present invention utilizes this user bit to control so that the number of 1 degrees (or the number of 0 degrees) of all data in one frame is always constant. Next, the word for frame synchronization (synchronization word) is set at the center position of the synchronization word, taking into account that the number of consecutive 1 degrees is 11 bits or less among the 64 bits for various data mentioned above. 12 consecutive bits °l
By arranging "00" and 'O1' at the front and back positions of this continuous portion, it is possible to detect a frame synchronization signal and to determine whether the tape running direction is forward or backward.

Here, 48 bits are allocated as frame data (including the synchronization word) other than the 32 bits for the user, but all of these 48 bits do not become "1", and the above Due to the nature of the BCD code and the number of frames, the maximum number of °°1° is 37. That is, first, the number of 11111 in 16 synchronization word bits is fixed at 13.Next , each 4 to display the ones digit of each address information word.
For bits, display 7 out of 0 to 9.
The maximum number of °'1" when 111"° is 3, and the lO digit of the frame and the lO digit of time are 0 and 1.
．． Since only one of 2 is displayed, the number of 'l゛ is 4I! I Maximum 1 session, O for each tens place of seconds and minutes
The maximum number of l゛ when displaying 3 or 5 out of ~5 is 2, so for all bits used to display address information, the maximum number of 1°° is 1.
There will be 8 pieces. Furthermore, among the 4 bits per word for address information mentioned above, the remaining 6 bits allocated to each word for displaying the 10's digit are all "l". The maximum number is six, which is the number at that time. Among these, what changes depending on the data content is the number of towns in the valley word for address information, and the maximum value of this total number is 18+6, 24, so 5, 32 of the user bits above. If the user bit data is controlled so that the number of ``1 + 1'' is always 24, for example, together with the bit data, then the total number of ``1'' of all data in the frame will be It is always controlled to a constant number of 37, including 13 which is the number of 1°. The number of transitions in the biphase mark modulated time code signal at this time is 117 from 8'0+37. In addition, among the data of one frame, the 64-bit various data parts other than the synchronization word part include all 32 of the words for address information.
It consists of a bit and a total of 32 bits for the user.
Considering that the number of "1's" in a word for address information can range from 0 to a maximum of 24, depending on the data content, the number of "1's" for each of the 64-bit data parts mentioned above When controlling the number of "" to be constant, it is necessary to set the constant value to any value between 24 and 32 in advance. This means that the above constant value is 2
If it is set to less than 4, constant value control cannot be performed when the total number of ``1'' in each word part for address information reaches 24, and if the above constant value is set to more than 32, the address When the total number of °′1゛° in the information valley word part becomes 0, all the user bits are set to “
This is because even if the angle is 1", the upper limit is 32, making it impossible to perform constant value control.

Controlling the data of the user bits in accordance with the contents of all 32 bits of the address information word in one frame of data is performed in the data control circuit section, but in this implementation. In this example, in order to simplify the hardware configuration, the binary data is complemented for each address information word, and this complement data is used as the user word.

In other words, in FIG. 1, the address information word is output one word at a time from the time code generation circuit 1 in the form of, for example, 4-bit parallel data, and this data is sent to the changeover switch 6 of the data control circuit section 2. The signal is sent to one selected terminal a and the complement generation circuit T, respectively. The complement generation circuit 7 generates 1 of the address information word.
Each time a word of data is input, it takes the complement of the input data or a value obtained by inverting ``1'' or ``0''.

The 1-word, 4-bit complement data from the complement generation circuit 7 is sent to the other selected terminal of the selector switch 6 as user word data corresponding to the input address information word. . The changeover switch 6 is controlled in response to a pulse signal (with an 8-bit cycle) in which H'IIL11 is switched every 4 bits as shown in FIG. 3A from a timing circuit 8, which will be described later. Therefore, regarding the data of each word in the pair of address information word and user word, one is in a complementary relationship with the other, that is, 1° and 0° are opposite, and there is a pair of 8-bit data. The number of I11' in one frame is always 4. Also, since there are 8 pairs of address information words and user words in the various data parts other than the synchronization widened in one frame, The total number of "'1'" in the data part is 32 from 4X8.The number of °1° in the synchronization word part is fixed at 13, so the data 11111 in the time code data of one frame is The total number is always controlled to 45.By bi-phase manic modulation of such frame data, signal transitions (transitions,
The total number of inversions or edges is 125.

Next, a configuration for generating clock pulses, various timing pulses, etc. provided in connection with the time code generation circuit 1 shown in FIG. 1 will be described.

First, a vertical synchronization signal of a video signal to be recorded on, for example, a video tape recorder is supplied to the time code generation circuit 1 via a terminal 11.

The time code generation circuit 1 outputs a frame pulse signal based on this vertical synchronization signal, and this frame pulse signal is sent to the timing circuit 8 and the reset terminal R of the switching counter 12, respectively.

Here, the switching counter 12 is supplied with an output signal from an oscillator 13 that oscillates at a frequency of 9.6 MH2, and by counting this oscillation output signal, the frequency division ratio when dividing the frequency is 1/1001 and 1/1. 1200 and is configured to be switchable. This is because the clock required to generate the above-mentioned longitudinal time code is different between the 8MPTE standard and the EB[J standard, so two types of oscillators are required to be able to use both standards. , two crystals, etc. are required, which doubles the effort and cost of adjustment. Therefore, in this embodiment, a simpler circuit is configured to be compatible with both of the above standards. That is, LTC
(Longitudinal time code) Each frame consists of 80 bits, and when generating LTC, the bit clock frequency (80 times the frame frequency) is 4 G) uses a twice as high speed clock. Here, the Lua L/-me frequency fpl in the SMPTE standard is 4.5 x 10 fF1 = 286 x 525 = 30000 (H2), and the frame frequency fp in the EBU standard is
z is fF2 = 25 Hz [Hz]. Therefore, in order to obtain the frame frequency of each standard, the 3 QkHz signal must be converted to 1/1001 or l or 1
It is sufficient to divide the frequency by /1200. Regarding the high-speed clock signal 80×4 times the frame frequency, the 9.6 MHz (t) signal obtained by multiplying the 3.0 kHz by 320, that is, the signal from the 9.6 MHz oscillator 13, is converted to l/l by the switching counter 12. By dividing by 1001 or 1/1200, respectively, the SMPTE standard or EB
A high-speed clock signal for U-standard LTC generation can be obtained. Note that switching the frequency division ratio of the switching counter 12 is as follows.
This is done in response to the SMPTE/EBU selection signal provided via terminal 14.

In this way, the switching counter 12 converts the above 9.6 MHz to 1/1001 or 1/1200 depending on whether the video signal to be recorded is the SMPTE standard or the EBU standard.
A high-speed clock signal whose frequency is divided into 1 and 2 is output, and this high-speed clock signal is sent to the time code generation circuit 1 and the timing circuit 8. Here, since the high-speed clock signal has a frequency 80 x 4 times the frame frequency fv, it is difficult to synchronize with the synchronization signal of the video signal to be recorded by dividing it into 1/320. It is necessary to obtain a frame pulse signal that is In the process of frequency division, a pulse signal corresponding to the cheetah formant of the time code of the (2) frame is obtained, for example, as shown in FIGS. 3A and 3E. For example, FIG. 3A shows an 8-bit period pulse signal in which 1) (II, IIL'' are inverted every 4 bits of the frame data format, and this pulse signal is sequentially divided by % to obtain the 3rd pulse signal. The pulse signals shown in Figures B to 3E are obtained.However, when dividing the signals from Figure 3B onward in % increments, the pulse signals are divided into 1 frame period (80 bit period).
Since each signal is reset at the frame boundary position (frame leading edge position), each signal in Fig. 3 C, D, and E becomes °L at the frame leading edge, and from this timing, the signals for frequency division are applied. A pulse signal having a period of one frame is obtained to start counting. Then, by detecting the rising edge of the pulse signal shown in Fig. 3E, the frame pulse signal shown in Fig. 3F can be obtained. These pulse signals A-, F in FIG. 3 are also used as various timing signals from the timing circuit 8. For example, every 4 bits in FIG. 3A are alternately IHII, I
The 8-bit periodic pulse signal that becomes ILI+ is the first
It is used as a switching control signal for the switching switch 6 of the data control circuit section 2 shown in the figure. In this case, when the pulse signal in FIG. Sent, 3rd
When the pulse signal shown in FIG. In addition, when outputting the 16-bit data of the synchronization word from the time code generation circuit 1, the pulse signal obtained by inverting the signal shown in FIG. 3E and the pulse signal shown in FIG. 3N are ANDed. The changeover switch 6 may be controlled by a pulse signal.

By the way, in order to keep the direction of the transition constant at the frame boundary position (the leading edge of the frame or the end of the synchronization word) of a time code signal subjected to biphase mark modulation, for example, the bit number 27 in FIG. is equipped with a biphase correction bit, and when this bit is enabled, so-called biphase correction mode, the total number of 1° in one frame is an even number. The biphase correction bits °'1'' and '0' are automatically determined. For example, when controlling the above frame boundary position to always be a falling transition, the current state is a rising transition. Then, the total number of °111" in the next frame period is an odd number and it changes to a falling edge, and from then on, the total number of °11" in the frame period becomes an even number, and the instantaneous Or, temporarily “l” in the frame.
The biphase correction bits are changed so that even though the number of `` may be odd, it is always an even number.

In this way, when the bi-phase correction bit is ON or in the bi-phase correction mode, the method of simply assigning the complement of the address information word to the corresponding user word will result in "I I
Since the total number of I's is 45, which is an odd number, a contradiction occurs and some countermeasure is required. For this reason, for example, as shown in FIG. 1, a user word (bit numbers 28 to 31
By partially destroying the complement relationship for the word (word) and fixing the user bit of bit number 31, which corresponds to the biphase correction bit of bit number 27, to "0, 1", the biphase correction in one frame is performed.・The total number of 79 bits other than bits is 44.
As a result, the high phase correction bit becomes “0°”, so the II of 1 frame 80 bits is
The total number of I II will always be controlled to a constant number of 44. That is, bit numbers 24 to 27 in FIG.
Since the bit is "'1010", the 4 bits (focus numbers 28 to 31) of the corresponding user word are "010".
It should be 1”, but the bi-phase collection
User bit (bit number 27) corresponding to bit (bit number 27)
Bit number 31) is fixed to '0'', so 01
00°. The total number of transitions within one frame period of the time code signal at this time is 124 from 80+44.

Next, FIG. 5 shows the L recorded by the above-mentioned recording method.
An example of the configuration of a time code signal reproduction side for reading a TC (longitudinal time code) signal is shown. In FIG. 5, a reproduced LTC signal is supplied to an input terminal 21, and this reproduced LTC signal is supplied to an LTC reader (reading circuit) 22 and a transition (both edge) detection circuit 23, respectively. There is. The transition detection circuit 23 detects all the rising and falling transitions of the reproduced LTC signal and sends them to the 1/124 counter 24. This 1/124 counter 24 is for detecting the frame period of the reproduced LTC signal, and corresponds to the case where the /<if/s correction monid is selected at the time of recording. Note that if the total number of °"1 °" in one frame during recording is 45 and the total number of transitions is 125, then 1/125
Of course, a counter may be used. Next, L
The TCIJ-der 22 extracts the 11 data QI numbers and the bit clock signal from the reproduced LTC signal,
These signals are sent to the synchronization word detection circuit 25, a bit clock signal is sent to the timing circuit 26, and a data "Il+" signal is sent to the data memory 27.The frame synchronization signal from the synchronization word detection circuit 25 is sent to the timing circuit 26. is being sent to.

In addition, a frame period detection pulse based on the number of transitions from the ° counter 24 is sent to this timing circuit 26, so that frame synchronization correction etc. can be performed when the above frame synchronization signal cannot be obtained. It has become.

Note that when the synchronization word detection circuit 25 normally detects the synchronization word, a reset pulse is sent to the counter 24 for each frame. From the timing circuit 26, 1
The above various data parts in the frame (bit numbers ゛0 to 6)
Timing pulses corresponding to the timing of each word in 3) are sent to the data memory 27, and various data in one frame are written to predetermined addresses in the memory 27. By reading the data memory 27 in address order, the time code data is transferred to the output terminal 2.
It is taken out from 8.

Note that the counter 24 determines 1/124 or 1/
In the process of frequency division by 125, the number of data II Ill in the 8-bit pair of address information word and user word is
(Hira) Excluding exceptions when ON, the number of transitions is always 4, and the number of transitions is 12. Therefore, by sequentially counting 12 transitions from the leading edge of the frame, it is possible to obtain pulse signals that sequentially indicate the positions of word pairs as shown in FIG. 2B. That is, each 8-bit section of the address information word and user word pair can be detected from the transition of the reproduced LTC signal.

When reproducing such LTC data, even if the tape speed fluctuates greatly, the time axis fluctuates, and an error occurs in reading the iphase modulation data, the number of signal transitions (transitions or inversions) will be reduced. Since it can be detected almost reliably, the frame period can be obtained by dividing this into 1/124 (or 1/125). Therefore, by counting the number of frames based on the time code data (tape position address data) immediately before a data reading error occurs, substantially accurate time code data can be obtained even when a data reading error occurs. becomes possible.

In addition, the frame format of time code data (
Since the pair of address information word and user word (see Figure 2) have a complementary relationship with each other, it is essentially equivalent to double writing of data, and this can be used to prevent data errors. Detection can also be performed, and if a reading error occurs only in the synchronization word part, each address information word and user word is detected according to the frame period based on the transition of the above signal and the correct time code data is generated. It is also relatively easy to obtain.

Note that the present invention is not limited to the above embodiments, and the frame format of the time code data is as follows:
It can also be applied to formats other than standards such as SMPTE and FliBU, and the above embodiment can also be applied to a constant value when controlling the total number of data pars 1" (or °"0"') in a frame to a constant value using user bits. is not limited to the numerical value.

〔Effect of the invention〕

According to the time code signal recording method according to the present invention, the total number of data ``l11'' (or 0'') in one frame of the time code signal is controlled to a constant value, and is recorded after being subjected to piezoelectric distortion modulation. Therefore, even if a data reading error occurs due to time axis fluctuations in the signal due to tape speed fluctuations when playing back the data and reading the data, it is possible to detect the frame period based on the signal transition, and read the data. The correct time code before the error occurred
Substantially accurate time code data can be obtained by counting the number of frames based on the data. Therefore, it is possible to significantly reduce editing errors during videotape editing. In other words, if the frame data format of the time code is a pair of address information word and user word with the same number of bits, the complement data of the address information word is paired with the user word. Place it in the word and in the frame...
If the number of 1... or "°0"° is controlled constant, the circuit configuration can be simplified, and even if an error occurs only in the synchronization word part during playback, the address information word 1- and the complement of the user word If the relationship is correct, data can be played back correctly.
As a result, the incidence of reading errors can be reduced.

Furthermore, the frame period can be detected by scanning the transition of the signal, and within this frame period a predetermined number (e.g. 80) determined by the data format is detected.
Of course, it is possible to reliably detect the occurrence of a reading error by determining whether or not data has been obtained.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the recording side circuit configuration used in an embodiment of the time code signal recording method of the present invention, FIG. 2 is a diagram showing the frame format of time code data, and FIG. 3 is a frame pulse Fig. 4 is a diagram for explaining an example of operation in biphase control mode, Fig. 5 is a block circuit diagram showing an example of the reproduction side circuit configuration. be.

Claims (1)

[Claims] When recording a time code signal that is bi-phase modulated and has user bits in one frame data format, the number of bits of data "1" or "0" in the one frame time code data is a constant value. A time code signal recording method characterized by controlling the data of the user bits so that the following is achieved.