JPS59210586A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To speed up operation, reduce power consumption and stabilize output level by providing MOSFET that make positive feedback operation to each other and MOSFET that makes loaded MOSFET off during non-operation period in the side of a pair of amplifying MOSFET source. CONSTITUTION:The p-channel MOSFETs Q12, Q13 are connected in current mirror form and constitute an active load circuit, and the drain is connected to drains of amplifying MOSFETs Q10, Q11 consisted of n-channel MOSFET. A read signal from complementary data lines D, D' is inputted to the gates of MOSFETs Q10, Q11, and drain output is supplied to the gates of n-channel MOSFETs Q14, Q15 between the source and grounding, and positive feedback motion is performed. Further, an operation timing signal phipa is supplied to the gates of n-channel MOSFET Q17 and p-channel MOSFET Q16, and amplifying output is sent out from the drain of the MOSFET Q11.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor memory device composed of MOSFETs (insulated gate field effect transistors).
The present invention relates to a technique effective for S static type RAM (Random-Access Memory).

[Background technology]

Conventionally, 0MO3 (complementary MO3) static type R
A circuit as shown in FIG. 1 is known as a sense amplifier used in a semiconductor memory device such as an AM.

This sense amplifier circuit has the disadvantage that the amount of change in the output level is small and the operating speed is relatively slow. Furthermore, since a direct current flows during the amplification operation, there is a drawback that current consumption is relatively large.

In addition, especially when using a data output cover sofa configured with a CMOS inverter circuit, since the amount of change in the output level is small, a relatively large through current flows through the CMOS inverter, and the output level increases during the non-operating period. There are disadvantages such as instability.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device including a sense amplifier circuit that operates at high speed.

Another object of the present invention is to provide a semiconductor memory device including a sense amplifier circuit with low consumption pI power.

Still another object of the present invention is to provide a semiconductor memory device including a sense amplifier circuit whose output level is stabilized during non-operation periods.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, there is a MOSF on the source side of a pair of amplifying MO3FETs that performs a positive feedback operation by receiving the drain signal of the other.
ET and load MO during the non-operating period.
By providing a MOSFET that turns off the 3FET, high-speed operation, low power consumption, and stabilization of the output level are achieved.

〔Example〕.

FIG. 2 shows a CMOS static type RAM in this invention.
A circuit diagram of an embodiment of a sense amplifier used in the present invention is shown.

p-channel MO8FETQ12. Ql3 constitutes an active load circuit by being connected in a current mirror configuration. That is, their sources are respectively connected to the power supply voltage terminal VDD, their gates are commonly connected, and the gate and drain of the Mo SF ETQ12 are commonly connected.

Above MO3FETQI 2. The drain of Ql 3 is an amplification MO, each composed of an n-channel MO3FET.
3FET QI o (connected to the drain of Ql 1).

A read signal from the complementary data line D is input to the gates of these amplifying MO3FET'QIO, Q1. And these amplification MO3FETQI O,Ql
There is n between the source of 1 and the circuit ground potential (OV).
Channel MO3FETQ14. Ql5 is provided at its gate, and the other amplification MOS FETQ
By being supplied with the drain outputs of 11 and Q10, a positive feedback operation is performed together with the amplifying MO3FETs Q'lO and Qli.

Also, is an n-channel MO3FETQ17 provided in parallel with the MO3FETQ14? L, above MO3FET
QI 2. A p-channel MO3FET Q16 is provided between the gate of Ql3 and the power supply voltage terminal VDD,
An operation timing signal φpa is commonly supplied to each gate.

Note that the amplified output of this sense amplifier circuit is
C is sent out from the drain of FET QI 1, and is composed of a p-channel MO3FET Q18 and an n-channel MOSFET Q 19, although it is not particularly limited.
It is transmitted to the input of the MOS inverter.

This CMOS inverter constitutes a data output sofa.

Next, the operation of the sense amplifier will be explained. .

During the non-operating period when the timing signal φpa is at a low level, the p-channel MO3FE is
TQ16 is in an on-state grudge.

The ON state of MO3FETQI 6 causes the load MO3FETQI 2. When Ql 3 are both in the off state, σ is also true. In this way, the load MO3FETQI2. Q
By turning off the sense amplifier 13, consumption of direct current during the non-operation period of the sense amplifier is prohibited. By the ON state of MO3FETQI6 mentioned above, MO3
Since the gate voltage of the FET QI 5 is at the high level of the power supply voltage VDD, the MO3FET QI 5 is also in an on state. At this time, since the level of the complementary data line D is at an intermediate level of the power supply voltage VDD, the amplifying MO
3FET QI 1 is also turned on. therefore,
The drain potential of this amplification MO5FETQ'll is set to a low level. This amplification MO3FETQI 1
The low level of the drain output of MO3FETQI
Since MO8FET Q10 is in the OFF state due to the above-mentioned intermediate level, its drain signal becomes high level even if MO8FETQ10 is in the operating state.

As a result of the above operation, the output signal of the sense amplifier transmitted to the data output cover sofa becomes low level, so that the p-channel MO3FETQ18 of the data output cover sofa is turned on, and the n-channel MO3FETQ19 is turned off. This stabilization of the output of the sense amplifier prevents a large through current from flowing through the data output sofa.

Next, when the timing signal φpa is set to high level to start the amplification operation of the sense amplifier, the p-channel MO3FETQ16 is turned off, and the n-channel MO3FETQ16 is turned off, and the n-channel
O3FETQI 7 is turned on. During the non-operating period, the MO3FET QI5 is in the on state, so an operating current flows through both the amplifying MO3FETs QIO and Qll. In this state, if the read level from the data line is at a higher level than the data line, the conductance characteristic of the amplification MO3FETQI 1 becomes larger than the conductance characteristic of the amplification MO5FETQI 0. Then, the drain current of the amplified MO3FET QI O is supplied to the drain of the amplified MO3FET QII through the loads MO3FET QI2 and Ql3, so the difference current causes the drain of the MO3FET QI
The gate voltage of 4 is lowered or the amplified MO3FF
, the drain current of TQ10 is made smaller and smaller. As a result, the drain potential of the amplification MO3FET QIO rises and the current flowing through the MO3FET Qi5 is increased, so that a positive feedback amplification operation is performed in which the drain current of the amplification MO3FET QI1 is further increased.

Due to this amplification operation, the output signal of the sense amplifier suddenly becomes low level.

On the other hand, if the read level from the data line is low level compared to the data line, ill@M OS F ETQ
The conductance characteristic of II becomes smaller than that of the amplification MO3FET QIO. The drain of this amplification MO3FETQI 1 is connected to a load MO3.
FETQ12. Increase through Q13+yMo S F E
Since the drain current of TQ 1 [) is supplied, the difference current increases the gate voltage of MO3FET Q14, so that the drain current of the amplification MO3FET QI O is made thicker.
The drain potential of FETQIO decreases and MO3FETQ
Since the current flowing through I5 is reduced, the amplification becomes even greater.
A positive feedback amplification operation is performed to reduce the drain current of FETQII. Through this amplification operation,
The output signal of the sense amplifier suddenly becomes high level.

When the output of the sense amplifier is stabilized at high level or low level, MO3FETQ15 or MO3FETQ1
4 is turned off, no direct current flows through the sense amplifier. Note that although the MO5FET Q17 is turned on by the high level of the timing signal φpa, its conductance characteristic is set to be relatively small, so that a very large current does not flow there.

FIG. 3 shows a circuit diagram of a memory cell used in a CMOS static RAM.

Memory MO3F with gate and drain cross-connected to each other
ETQ20. Q21 and the above MO3FETQ20. Q2
A high resistance R1 formed of a polysilicon layer for information retention is connected between the drain of R1 and the power supply voltage VDD.
, R2 are provided.

And the above MO3FETQ2'0. A transmission gate MO3FE is connected between the common connection point of Q21 and the complementary data line, D.
TQ22. Q23 is provided.

The memory cells are arranged in a matrix.

Transmission gate type MO3F of memory cells arranged in the same row
ETQ22. The gates such as Q23 are commonly connected to the corresponding word line W, and the input/output terminals of the memory cells arranged in the same column are respectively connected to the corresponding pair of complementary data (or bit) lines D. Ru.

In the above memory cell, in order to make it consume low power, its resistor R1 is set to be high enough to maintain the gate i-voltage of MO5FET Q21 above the threshold voltage when MO3FET Q20 is turned off. It is made into a resistance value. Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistor R1 has a current supply capacity sufficient to prevent the information charge N multiplied by the gate capacitance (not shown) of the MO3FET Q21 from being discharged due to the drain leakage current of the MO3FET Q20. be done.

According to this embodiment, although the RAM is manufactured by CMO3-IC technology, the memory cell is composed of an n-channel MO3FET and a polysilicon resistance element as described above. Compared to the case where a p-channel MO3FET is used in place of the polysilicon resistance element, the size of the memory cell and memory array can be made smaller. That is, if a polysilicon resistor is used, the memory MO5FET
It can be formed integrally with the gate electrode of Q20 or Q21, and its size can be reduced.

Then, as when using p-channel MOS FETs, storage MO3FETQ20. Since there is no need to separate it from Q21 by a relatively large distance, no unnecessary blank space is created.

Although not particularly limited, the static type RA of this embodiment
M has a multi-bit storage structure such as 32 bits x 64 words, and constitutes a general-purpose register in a large computer or the like. Therefore, such a multi-bit (32
In order to read out bits in parallel, the number of sense amplifiers and data output buffer sofas is 32 each.

〔effect〕

(1) The positive feedback amplification operation of the sense amplifier as described above has the effect of increasing the speed of operation.

(2) During the non-operating period of the sense amplifier,
Since the output level is quickly stabilized to a low level, the operation of the data output sofa is also stabilized, and there is an effect that unnecessary current consumption is not performed.

(3) When the drain outputs of a pair of amplifying MO3FETs are subjected to positive feedback so as to control the operating current of the other, when the output is stabilized at one level, 1. Since a relatively large direct current no longer flows, it is possible to achieve the effect of reducing power consumption. This effect is particularly significant in the multi-pint static type RAM as described above.

Although the invention made by the present inventor has been specifically explained based on the embodiments described above, this invention is not limited to the above-mentioned embodiments, and it should be noted that various changes can be made without departing from the gist of the invention. Not even. For example, the memory cells constituting the static RAM are n-channel M
OS F TE T and p-channel M OS F E
A flip-flop circuit configured with T may also be used. Further, the specific circuit configuration of the data output sofa and the specific circuit configuration of the peripheral circuit of the memory array can take various embodiments.

[Application field]

This invention is a static type RAM including a CMO3 circuit.
It can be widely used in semiconductor memory IQ devices such as programmable ROM (read only memory).

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a sense amplifier that is an example of the conventional technology. FIG. 2 is a circuit diagram that shows an embodiment of a sense amplifier used in a static RAM according to the present invention. FIG. 2 is a circuit diagram showing an example of a cell.

Claims (1)

[Claims] 1. MO3FETQ12 of the first conductivity type in the form of a current mirror
．． A load means composed of Ql3 and the above MO3FETQ
I 2. Amplifying MO3FETs QIO and Q11 each consisting of a second conductivity type MOSFET whose drain is connected to the drain of Ql3, and the above amplifying MO3FET.
It is provided between the source of QI O, Ql 1 and the ground potential of the circuit, and its gate is connected to the MO3FET QII, QI
MO3FE of the second conductivity type cross-connected with the drain of O
TQ14, Ql5 and the above MO3FETQ12. Q13
M of the first conductivity type, which is provided between the shared gate and the power supply voltage vpp, and receives the operation timing signal φpa.
O3FETQI 6 and a second conductivity type M, 05FETQ17 which is provided in parallel with the MO3FETQ14 and receives the timing signal φpa,
A semiconductor memory device comprising a sense amplifier circuit that sends out an amplified output from the drain of a FETQII. 2. The sense amplifier circuit amplifies a read signal from a selected memory cell in a CMOS static RAM and transmits the amplified signal to a data output sofa formed of a CMOS inverter. The semiconductor memory device according to item 1. 3. The CM OS static type RAM writes/reads multi-focus information in parallel,
3. The semiconductor memory device according to claim 1, wherein the sense amplifier circuits are provided in a number corresponding to the number of bits.