JPS59207723A - Pulse shaping circuit - Google Patents

Abstract

PURPOSE:To enable to form a pulse signal having optional inclination by using a signal forming device such as a kind of inverter, thereby enabling to make rise and fall speed of a signal equal and to set to desired inclination. CONSTITUTION:Signal forming devices 20c and 20d are constituted in the same way as signal forming device 20a and 20b consisting of constant current sources 11a, 12a or 11b, 12b and MOSFETs Q1a, Q2a or Q1b, Q2b that consist a CMOS inverter connected between power source voltage VDD and VSS with said current sources between. For the constant current source 11a-12b, MOSFET that works as a constant current element by receiving the constant bias voltage in the gate is used, and able to form a signal of optional inclination by changing the magnitude of bias voltage. Above-mentioned signal forming devices 20a- 20d output a signal of inverted input signal, and can be regarded as a kind of inverter.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to logic circuit technology and switching circuits, such as analog switches, switched capacitor filters, etc. It is about effective techniques.

[Background technology]

The background of the present invention will be described based on studies conducted by the inventor.

By replacing the resistive element in the RO active filter with an analog switch and a capacitor, MO
A switched capacitor filter that can be integrated into an integrated circuit has been proposed.

In such switched capacitor filters, MOSFETs (insulated gate field effect transistors) are used as analog switches. However, if only 10,000 p'-channel type or n-channel type MO8FFliTs are used as an analog switch, the switch will not be turned on sufficiently due to the relationship between the power supply voltage and the signal level, and the relationship between the substrate effect and the signal. may not be transmitted. Additionally, when a fast-changing signal is supplied to the gate terminal of a MOSFET, the change in the gate input signal is transmitted to the signal line via the capacitance between the gate and the source or drain, causing noise. It has become clear that a so-called feed-through phenomenon occurs.

Therefore, as an analog switch for a switched capacitor filter, a CMO consisting of a pair of p-channel MO8FETQP and an n-channel 7-channel MO8F'ETQn arranged in parallel on the signal line is used as an analog switch for a switched capacitor filter.
S analog switch is used. And this 0
p-MO3FETQ that constitutes the M0S analog switch
, and n-MO8FETQn are supplied with clocks φ and φ having opposite phases to each other to turn them on and off simultaneously. This ensures signal transmission.

Also, p-MO3FETQ and n-MO8FETQn
If the clocks φ and φ applied to the gates of the clocks φ and φ have a completely opposite phase relationship, the noise generated by the feedthrough will be positive and negative, respectively, and will cancel each other out. As a result, the effects of feedthrough are offset.

By the way, if you need a clock with an anti-phase relationship,
A possible method is to connect inverters in two stages as shown in FIG. However, if a general inverter is used to create clocks with opposite phases, the rise and fall of the clocks φ and φ will not match, as shown in FIG. 3, due to the delay in the inverter.

Therefore, p-MO8FETQ and n-MO8FETQ, which constitute the OMQS analog switch to which clocks φ and φ are supplied,
n-MO8T even after 8FETQn is turned off! “BT
Since the clock changes on the Qo side continue, noise due to feedthrough cannot be completely canceled. the result,
Characteristics such as the S/N ratio in switched capacitor filters operated by these clocks deteriorate, and DC amplifiers using switched capacitors have the problem of generating offset voltage. Do you get it.

Moreover, if an inverter is used as a clock forming means, the rising and falling speeds of the clocks φ and φ will differ due to variations in the process of elements constituting the inverter. However, if the rising and falling speeds of the pair of signals that operate the 0M0S switch are different, the amount of feedthrough will be different between the p-MOS side and the n-MOS side, and the effect of the feedthrough will be completely canceled out. The inventors have discovered that there are problems such as the inability to do so.

[Purpose of the invention]

One object of the present invention is to enable the rising and falling speeds of a signal to be equal and set to a desired slope, thereby making it possible to form a pulse signal with an arbitrary slope.

One object of the present invention is to create a set of signals having opposite phases to each other with almost no delay.

One object of the present invention is to use such a signal (clock) K
Therefore, the object of the present invention is to improve the S/N ratio in a MOS analog circuit such as a switched capacitor filter that is operated. Another object of the present invention is to prevent the occurrence of offset voltage in a DC amplifier and improve the characteristics of the circuit.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention connects a constant current element and one switch element constituting an inverter in series between one power supply voltage terminal of a circuit and an output node, and connects a constant current element and one switch element constituting an inverter in series between one power supply voltage terminal of the circuit and an output node. By using a signal forming means such as a type of inverter in which a constant current element and the other switch element constituting the inverter are connected in series between the two, the rising and falling speed of the signal is passed through the constant current element. The above object is achieved by making it possible to set a constant speed determined by the magnitude of the current flowing.

The present invention will be specifically explained below using the drawings.

〔Example〕

FIG. 4 shows an embodiment in which the present invention is applied to a clock generator for a switched capacitor filter.

In this embodiment, the output signal of the NAND gate 2, to which the reference clock OLK is supplied to one input terminal, is connected to the p-MO8FETQ which constitutes the 0M0S inverter.
and is supplied to the gate terminal of n-MOS FETQ2aa. And p-MO8F
ETQ and n-MO8FETQ2a are connected to the output node n via constant current a sources 11a and 12a. is connected to form a clock φ. Further, the output signal of the NAND gate 2 is connected to the constant current source 11b between the power supply voltage VDD and vss via the inverter 3, as described above.

p-MO8I"ETQ connected in series with 12b in between
, b and n are supplied to the gate of the MO8FET Q2b to form a clock φ1.

Furthermore, the clock φ1 is inverted by an inverter 4, and is supplied to the other input terminal of a NAND gate 5, which has one input signal as the output of the inverter 1 which inverts the reference clock OLK.

This NAND gate 5 is connected to a constant current source and 0M0S
The signal is supplied to a signal forming means 20c consisting of an inverter to form a clock φ. Further, the output signal of the NAND gate 5 is supplied to the signal forming means 20d via the inverter 6, so that the clock φt is formed.

The signal forming means 20c and 20d include a constant current source 11a,
12a or 11b, 12b, and MO8lli'ETQ1a, Q2a or Q1b*Q2b forming an 0M0S inverter connected between the power supply voltage ■DD and 788 in such a way as to sandwich it, the same configuration as the signal forming means 20a and 20b. It is being done. Further, the constant current sources 11a to 12b are MOSFETs which are controlled to operate as constant current elements by receiving a constant bias voltage at their gates.

Furthermore, the constant current sources 11a to 12b can form a signal having an arbitrary slope by changing the magnitude of the bias voltage.

Each of the signal forming means 20a to 20d outputs a signal obtained by inverting the input signal, and therefore can be regarded as a type of inverter. FIG. 5 shows signal forming means 20a to 20.
The clock generator of FIG. 4 is expressed by a circuit symbol, assuming that d is an inverter.

In this clock generator, the output of the inverter 20b is in phase with the output of the inverter 4, and the output of the inverter 20c is in phase with the output of the inverter 4.
Since the output of the inverter 7 is in phase with the output of the inverter 7, the two sets of clocks φ, having an opposite phase relation, whose on periods do not overlap with each other.

φ1 and φ2. Outputs φ.

Moreover, in the circuit of the embodiment, the final stage inverter forming each clock is constituted by a pair of constant current sources and a 0M0S inverter, as shown in FIG. Therefore, the MOSFE that makes up the CMOS inverter
If T is designed to have a high driving capacity, 0M0
The 8FET acts as a switch that operates at high speed, and the rising and falling speed of the output clock is determined by the constant current source 1.
1.12.

Therefore, since the current flowing through the constant current sources 11 and 12 has little dependence on process parameters, the current flowing through the constant current sources can be kept constant without being affected by process variations. Further, the signal forming means 20a to 2
The rising and falling speed of the 0d output signal is determined by the time required to charge up the stray capacitance parasitic on the output line with the current flowing through the constant current source 11, and the time required to charge up the stray capacitance parasitic on the output line with the current flowing through the constant current source 11, and the charge of the stray capacitance by the constant current source 2. It is determined by the time required to discharge the current flowing through the battery. Therefore, if the charging and discharging current is constant, the rising and falling speeds will be constant,
The slope of the signal change becomes linear.

Moreover, if the driving capabilities of inverters 3 and 6 are increased, the delay time in inverters 3 and 6 becomes negligible. Therefore, the clocks φ and φ output from the signal forming means 20a and 20b.

The delay between the clocks φ7 and φ outputted from the signal forming means 20c and 20d becomes almost zero, and the two sets of clocks φ7. φ1 and φ
1. φ, can be obtained.

Then, if the outputs of the signal forming means 20a and 20c are inverted and supplied to the NAND gates 2 and 5, inverters 4 and 7 have an appropriate delay, the clock φ1
K can be set so as not to overlap the periods of the 1-repel periods of and φ.

Moreover, in this case, the logical shereshield of the inverters 4 and 7 can be set to a desired value by appropriately designing the size ratio of the p-MOSFET and n-MOSFET constituting the inverters 4 and 7. Therefore, together with the fact that the slope of the signal change in the signal forming means 20a and 20c can be made constant, the amount of delay in the inverters 4 and 7 can be determined accurately.

As explained above, the clock generator V-
In the evening, the delays of the clocks φ, and φ, and φ, and φ can be made almost zero, and the rising and falling speeds can be made equal. Therefore, the clock φ
1. φ, and φ1. φ.

The 0M0S switch operated by the supply of p-M
The OS side and the n-MOS side are turned on and off at the same time, and the amount of feedthrough is also equal between the p-MOS side and the n-MOS side. As a result, the noise caused by the feedthrough is completely canceled out, and there is no possibility that noise will be added to the signal line.

Furthermore, in the clock generator of the embodiment, the rate of change of the clock can be freely designed, so that even if the rate of change is slowed down, noise due to feedthrough can be offset. As a result, the S/N ratio and other characteristics of switched capacitor filters, etc., which are operated by receiving the lock supply, can be improved, and the offset of DC amplifiers using switched capacitor circuits can be improved. Voltage generation is prevented.

Note that in the above embodiment, two sets of clocks φ1. φ, and φ,.

Although the description has been given of a clock generator configured to generate φ, the present invention can of course be applied to a lock generator that generates only a pair of clocks φ and φ having an antiphase relationship with each other.

Further, the NAND gates 2 and 5 in the above embodiment can be replaced with NOR gates.

Furthermore, in the above embodiment, the constant current sources 11 and 12 are sandwiched between the power supply voltage DD and the MO8FBTQ.
1- Qt is connected in series to signal forming means 20a~
20d, however, the connection positions of the constant current sources 11 and 12 are not limited to this. For example, as shown in FIG. 6, a MOS FBT Qr-Qt constituting an 0M0S inverter may be sandwiched between the constant current sources 11 and 12, and connected in series between the power supply voltage vDD and 88. Alternatively, (8) in the same figure, (as in 01, power supply voltage v) between D-788, constant current source 11.12 and MOS
FETQr-Qt may be arranged alternately and connected in series.

Next, a second embodiment of this invention will be described.

FIG. 7 shows an embodiment in which the present invention is applied to a triangular wave forming circuit in a pulse width modulator.

In this embodiment, the signal forming means 20 in the previous embodiment is
As in a to 20d, there is a charge/discharge switching circuit 20 constituted by a set of constant current sources 11 and 12 and a 0M0S inverter, and a capacitor 0 connected between the output node n0 of this circuit 20 and the ground. A triangular wave forming circuit 30 is configured by these. 0 in the charge/discharge switching circuit 20
MO8FETQ, by supplying a clock signal to the gate of the MOS inverter (Qr - Q!).

Q is alternately turned on and off to switch the charging/discharging path for capacitor C. That is, when MO8FETQ is turned on and Q is turned off by the clock signal OLK, charge flows into the capacitor C through Q, and the capacitor is charged toward the power supply voltage vDD. Next, when MO8FETQ is turned off and Q is turned on, the electric charge charged in capacitor 0 is transferred to Q.
The voltage is passed through to the power supply voltage v8s, and the voltage between the terminals of capacitor 0 gradually decreases.

At this time, the magnitude of the current flowing through capacitor 0 and the current flowing from capacitor C are the same as that of constant current source 11.
12. Therefore, if the bias voltages of the constant current sources 11 and 12 are determined in advance so that the current flowing through the constant current source 11 and the current flowing through the constant current source 12 are equal, the rate of charging and discharging of the capacitor C, The rate of rise and fall of the voltage will be equal. As a result, the triangular wave forming circuit 30 generates a symmetrical triangular wave whose rising speed or slope is exactly equal to the falling slope.

If this triangular wave is supplied to one input terminal of the comparator 40 and the input signal Vio is supplied to the other input terminal of the comparator 40, a pulse corresponding to the magnitude of the input signal vin will be output from the output terminal of the comparator 40. A signal having a width or a pulse width modulated output signal V. u
t is obtained.

In the pulse width modulator, if the triangular wave supplied to one input terminal of the comparator 40 is not symmetrical,
In other words, when the rise speed and fall speed of the triangular wave signal are different, accurate modulation cannot be performed because the delay time of the comparator 40 when the triangular wave signal rises is not equal to the delay time when it falls. .

However, according to the triangular wave forming circuit 30 of the above embodiment,
A very clean triangle with equal rising and falling speeds is formed and fed to the comparator 40. Therefore, the delay times in the comparator at the time of rising and falling are equal, and accurate pulse width modulation becomes possible.

Note that also in the second embodiment, the triangular wave forming circuit 3
The charging/discharging switching circuit 20 as a signal forming means within 0 is not limited to the one having the configuration shown in FIG.
Of course, it is possible to use a structure as shown in FIG.

[Effect] A pair of constant current sources and a pair of switch elements that make up an inverter are connected in series to generate a signal.

Since signal forming means is provided that can set the falling speed to a constant speed determined by the magnitude of the current flowing through the constant current source, the rising and falling speeds (slopes) of the signal are equal. It becomes possible to form a pulse signal.

Therefore, when applied to a pulse width modulator or the like, highly accurate modulation is possible. In addition, by changing the bias voltage of the constant current source, it is possible to form a signal with a slope of the same direction, and there is almost no delay when creating a set of signals (clocks) that have opposite phases to each other. can do.

As a result, the CMOS is turned on and off by this signal.
Feedthrough effects in analog switches now completely cancel each other out, reducing S/N in analog circuits that include switched capacitor circuits that sample and hold analog signals, such as switched capacitor filters. Characteristics such as ratio become better.

Further, in a cross-current amplifier equipped with a switched capacitor circuit, generation of offset voltage due to feedthrough is prevented and circuit characteristics are improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Application field]

This invention is not limited to pulse shaping circuits such as the clock generator for switched capacitor filters and the triangular wave forming circuit of pulse width modulators, but is applicable to all applications where the slope of signal change is desired to be constant. It can be applied to the following circuits.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the configuration of a CMOS analog switch. Figure 2 is a circuit diagram showing an example of a general circuit configuration when forming a negative phase signal. Figure 3 is the timing of the signal formed in that case. FIG. 4 is a circuit configuration diagram showing an example of a clock generator according to the first embodiment of the present invention, and FIG. 5 is a configuration diagram showing this using circuit symbols. FIG. 6 is a circuit diagram showing another example of the configuration of the signal forming means, and FIG. 7 is a circuit diagram showing an example of the case where the present invention is applied to a triangular wave forming circuit of a pulse width modulator. Qt e Qt * Q13 * Q1b * Q
23* Q2b H...Switch element (OMOS inverter), 11.12° 11a, llb, 12a, 12
b Constant current source, 20a, 20b, 20c, 20d - Signal forming means, 20... Signal forming means (charge/discharge switching circuit), 30... Pulse shaping circuit (triangular wave forming circuit). Agent Patent Attorney Akio Takahashi ／′-1（・ ・

Claims (1)

[Claims] 1. A first constant current source and a first switch element are connected in series between the first power supply voltage terminal and the output node of the circuit, and A second constant current source and a second switching element are connected in series between them, and the first and second switching elements are turned on and off in a complementary manner, thereby changing the rising speed and falling speed of the signal. A pulse shaping circuit characterized by comprising a signal forming means configured to set a constant speed determined by the magnitude of the current flowing through the first and second constant current sources.