JPS59207089A - Artificial static memory - Google Patents

Abstract

PURPOSE:To redeuce power consumption at the time of automatic refresh causing the reduction of yield by using a programmable element for an automatic refreshing timer and changing the period of automatic refreshing time in accordnace with the holding characteristics of a memory cell. CONSTITUTION:Differently from an ordinal static memory, a capacitor C1 is connected to a node N1 through a programmable element P1. The holding characteristics of the memory cell is checked, and when the holding characteristics is high, the programmable element P1 is connected, the load capacity of the node N1 is increased and the period of the automatic refresh timer is expanded to reduce power consumption. When the holding characteristics is low, the programmable element P1 is disconnected, the load capacity of the node N1 is reduced and the period of the automatic refresh timer is shorted to prevent the reduction of the yield. Although one programmable element is used in this example, plural programmable elements also can be arranged. Althrough the capacity is reduced by the programmable element in this example, the increment of the capacity can be also attained in the same manner.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and particularly to a dynamic semiconductor memory having the function of automatically refreshing memory cells by activating an external manual refresh control clock to activate an internal refresh control circuit having a timer. -Relates to semiconductor memory consisting of random access memory (hereinafter referred to as DRAM).

Such DRAM is pseudo-static RAM (hereinafter referred to as P
This improves the drawback of high power consumption during automatic refresh mode (hereinafter referred to as ATRF mode), since data needs to be refreshed at a fixed cycle (usually 2m5ec).

FIG. 1 is a block diagram for explaining the structure of the P S RAM. Memory cell 1, row address decoder 2,
It includes a column address decoder 3, an internal clock generator 4, an off-lator 5 for a substrate voltage generator, a substrate voltage generator 6, and an internal pulse control circuit 7. Also, the internal refresh core circuit 7 has an external refresh control clock input terminal 8, an automatic refresh timer 9, and a refresh clock generator 1.
0 and a refresh meeting address counter 11. Next, the ATRF mode, which is a feature of the P S RAM, will be explained. The external refresh control clock RFsH input to terminal 8 is activated (low level) for a certain period of time (for example, 16 μsec or more)
When the automatic refresh timer 9 is activated, the automatic refresh timer 9 starts operating and generates an automatic refresh signal. In response to the automatic refresh command, internal refresh is performed via refresh clock generator 10 and refresh address counter 11. When the internal refresh operation is completed and automatically returns to the precharge state, the automatic refresh timer 9 is activated and the time interval required to automatically refresh all memory cells (automatic refresh timer 9 is activated).
For example, the worst case is 2m5ec/
Count 128 == 15.625 μsec. When this time has elapsed, auto-refresh timer 9 outputs an auto-refresh signal to start internal refresh of the next address. During the refresh operation period, the automatic refresh number timer 9 is reset, and when the refresh operation is completed and the precharge state is entered,
Restart cycle timing. As long as RFSH is activated in this way, all memory cells are automatically refreshed.

Next, the operation of the automatic refresh timer circuit will be explained using the conventional example shown in FIG. MOS) The drain of transistor Q1 is the power supply voltage, the gate is the clock φ1, the source is the node Nl MOS) The drain of transistor Q2 is the node Nl
, the gate is grounded, the source is connected to the node N2, the drain gate of the MOS transistor Q4 is connected to the power supply voltage, the source is connected to the output φ3, the drain of the MOS transistor Q5 is connected to the output φ3, the gate is connected to the node Nl, and the source is connected to the ground voltage. each connected. Also, capacitor C1 is connected to clock φ2 and node N2.
, the capacitor C2 is connected to the node Nl and the ground voltage, respectively.

FIG. 3 is a timing chart for explaining the operation of the automatic refresh timer circuit.

During the first refresh operation period, the automatic refresh 0 timer is reset by clock φ1, and node N1 is charged to high level. After that, the output of the substrate voltage generator oscillator is input as clock φ2, and when clock φ2 changes from low level to high level, the level of node N2 temporarily becomes a positive potential due to the coupling of capacitor C1, but MOS transistor Q3 To turn on, VT (&i
When the next clock φ2 settles at the 0S transistor threshold voltage (0S transistor threshold voltage) level and changes to the high level and low level, the level of the node N2 temporarily becomes negative due to the coupling of the capacitor C1, but the MOS transistor Q2 turns on. To do this, it settles down to -VT level.

At this time, nodes A and N1 are discharged, and the level of node Nl decreases. In this way, each time the clock φ2 is input, the level of the node Nl gradually decreases, and the level of 1 at the node becomes VT.
When the current level also decreases, MOS transistor Q4. The output φ3 of the inverter constituted by Q5 becomes high level, an automatic refresh signal is generated, and internal refresh is performed. During the refresh operation period, the node Nl is charged to a high level by the clock φ, the inverter output φ3 becomes a low level, and the refresh operation is repeated thereafter.

As explained above, in conventional P S RAM, the operating cycle of the automatic refresh timer is the refresh cycle determined by the worst-case specifications, for example, 2m5ec/128' = 15
．． If it is set to 625μsec, A
The TRF mode had little effect on reducing power consumption compared to refreshing using an external clock. On the other hand, since the retention time of the DRAM is longer than 1 sec in the groove, it is possible to reduce power consumption by lengthening one cycle of 7 retrievals in the T'fLF mode.

An object of the present invention is to eliminate the power consumption in ATRF mode without causing a decrease in yield. The purpose of this invention is to provide a method for lowering the power source.

The present invention will be described in detail below with reference to the drawings.

An inventive embodiment is shown in FIG. The difference from the conventional example (FIG. 2) is that a capacitor C1 is connected to the node via a programmable element P1.

The retention inertia of the memory cell is checked, and if the retention characteristics are good, the programmable element P1 is connected, and the node Ni
Increase the load capacity of the IJ refresh timer and lengthen the period of the IJ fresh timer to reduce power consumption. On the other hand, if the retention characteristics are not good, the programmable element P1 is disconnected, the load capacity of the node Ns is reduced, and the cycle of the automatic refresh timer is shortened to prevent a drop in yield.

J', L JlAs explained above, by using a programmable element in the automatic refresh timer and changing the period of the automatic refresh time according to the retention characteristics of the memory cell, a decrease in yield can be caused. It is possible to reduce power consumption in the ATR and F modes.

In the above example, the case of one programmable element was explained, but it is also possible to arrange several programmable elements. 1
However, it is also possible to increase the capacitance using a programmable element (as explained in Section 8 above).

[Brief explanation of the drawing]

Fig. 1 is a block diagram for explaining the configuration of PS RAM, Fig. 2 is a diagram showing a conventional example of an automatic refresh timer, and Fig. 3 is a timing chart showing the operation of the automatic refresh timer between stations. , FIG. 4 is a diagram showing an embodiment of the automatic refresh timer of the present invention. 1...Memory cell, 2...Row address decoder, 3...Column address decoder, 4...
...internal clock generator, 5 ... oscillator for substrate voltage generator, 6 ... substrate voltage generator,
7...Internal fresh control I'E
'l path, 8... External refresh control clock input terminal, 9... Automatic refresh timer, 10... Refresh clock generator, 11... ...Refresh address counter, Q1 to Q5...MOS) transistor, C1
~C3... Capacitor element, P]... Programmable element. Agent Patent Attorney Uchihara ,''::V,H;
-2 days...-) ゛<', ・-' Figure 1

Claims (1)

[Claims] Automatic refresh timer, refresh eyelid address
In a pseudo-static memory equipped with an internal refresh circuit composed of a counter and a refresh clock circuit that controls the circuit, a programmable element is used in the automatic refresh timer circuit to change the timer period! Pseudo-static memory characterized by enabling.