JPS59205756A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To prevent the remaining of a smear, and to obtain an element having high sensitivity by constituting the element by light-receiving regions arranged in the horizontal and vertical directions at regular pitches, a plurality of vertical registers extending in the vertical direction, photo-charge signal temporary storage regions positioned among the light-receiving regions disposed in the vertical direction, and reading gate regions positioned among the temporary storage regions and the vertical shift registers. CONSTITUTION:A light-receiving section 15A and a storage section 15B are formed to a solid-state image pickup element 15, and picture elements SENS and vertical shift registers VR transferring optical signal charges photoelectrically converted by the picture elements are each mounted independently. On the other hand, regions in which optical signal charges from each register VR are stored at every light-receiving region are formed to the storage section 15B, and the regions and the registers VR are used in common. According to such constitution, charges are transferred to the storage section 15B from the light-receiving section 15A for a vertical blanking period, and charges transferred and stored into the storage section 15B are read at every one horizontal period, and transferred to a register 15C and read.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a solid-state imaging device using a charge transfer device such as a COD.

Background Art and Problems Therein For example, when a CCD is used as a solid-state image sensor, the light-receiving region (picture element) may have an MO8 configuration or a PN junction configuration.

Figure 1 is an example of the former, Figure 2 is an example of the latter,
In this example, (1) is a P-type silicon substrate;
There is an Nfi area (2) near the top surface of the vertical shift register VR as a bulk channel (embedded channel).
is formed, and an N+ type region 3) for overflow drain OFD is sandwiched between the sensor region 5EN81.
Furthermore, by sandwiching this N+ type region 3), a controller for nitrogen flow on the left side is formed (P for 0-kl'-to 0FCG).
A + type region (4) and a P+ type region (5) for channel stock AC8 are formed on the right side. ROG indicates readout control f-)k. And the base (1)
An electrode (8) made of polysilicon or the like for vertical transfer is formed on the upper surface of the (
9) is a transparent electrode that controls the sensor area 5ENS'e.

In FIG. 1, a sensor region 5gN5 having an MO8 structure is formed by the base (1), an insulating layer (7), and a transparent electrode (9), and in FIG. 2, an N+ type region is formed in the base (1). A sensor region 5EN8 having a PN junction configuration is formed by the region 2) and the base body (1).

In the structure shown in FIG. 1, the light is absorbed by the transparent electrode (9)K formed in the sensor area 5INS, so the sensitivity to each color of red, green, and blue light decreases as a whole, and the substrate (1 ) Due to the shallow spread of the depletion layer formed inside the depletion layer, optical signal charges due to long-wavelength original signals (red signals, etc.) that penetrate deep into the substrate outside the depletion layer are diffused into the substrate, resulting in a vertical shift. It flows into the register VR and causes smear. Furthermore, since the overflow drain OFD is arranged two-dimensionally, the element surface cannot be used effectively.

In the configuration shown in FIG. 2, since there is no transparent electrode (9) in the sensor region 5ENS, a decrease in sensitivity can be suppressed, but in this case as well, smear occurs because the depletion layer in the substrate (1) is shallow. In addition, because of the PN junction configuration, when reading optical signal charges, the optical signal charges in the sensor region cannot be completely transferred to the vertical shift register VR side, resulting in afterimages.

As described above, the conventional configuration of the sensor area and other areas has advantages and disadvantages.

OBJECT OF THE INVENTION Therefore, the present invention proposes a highly sensitive solid-state image pickup device that does not generate smear or afterimage and can effectively utilize the device surface.

Summary of the Invention In order to achieve the above object, the present invention includes a plurality of light receiving areas arranged at a predetermined pitch in the horizontal and vertical directions, a plurality of vertical shift registers extending in the vertical direction, and a plurality of vertical shift registers arranged in the vertical direction. formed between the light-receiving areas n,
A solid-state image sensor is formed by a temporary storage area in which photoelectrically converted A7'c original signal charges are stored in the adjacent light receiving areas, and a readout dirt area formed between this temporary storage area and the vertical shift register. It is composed of

Embodiment Next, an example of the solid-state image sensing device according to the present invention will be described in detail with reference to FIG. 3 and subsequent figures. The embodiment is a case in which the present invention is applied to a solid-state image sensor, which can be called a modification of an interline transfer structure or a frame-based field transfer structure. The outline is shown in Figure 3.

That is, this solid-state image sensor (G) has a light receiving section (15A).
) and an accumulation part (15B), and the light receiving part (15A) has a light receiving area (pixel) 5ENS and a light receiving area 5ENS"'
Vertical shift registers for transferring the r′9-converted signal charges are independently provided, and a force storage unit (15B
) has a region for storing optical signal charges from each vertical shift register VR for each light receiving region, and is designed so that this region and the vertical shift register VR are commonly used.

Charge transfer from the light receiving section (15A) to the accumulation section (15B) is performed during the vertical blanking period, and the charge transfer from the light receiving section (15A) to the accumulation section (15B)
The accumulated charges are sequentially transferred to the horizontal shift register (read register) (15C) every horizontal period.
and read out.

In such a solid-state image sensor a0 according to the present invention, the light receiving section (15A) is configured as shown in FIG. 4 and subsequent figures.

The light receiving section (15A) has a plurality of light receiving areas (sensor areas) S ENS with predetermined pitches in the horizontal and vertical directions.
A plurality of vertical shift registers vR extending in the vertical direction are arranged between the sensor regions 5ENS arranged in the horizontal direction. Between the vertically arranged sensor regions 5EN8, vertically adjacent sensor regions 5ENS and 5ENSj (1, j
is a temporary storage region ps in which a part of the optical signal charge photoelectrically converted is stored in the i-th and j-th sensor regions, respectively.
is formed. A read dirt region ROG is provided between the temporary storage region PS and the vertical shift register VR, respectively, for reading and transferring the original signal charges stored in the temporary storage region ps to the vertical shift register VR.

FIG. 5 shows an example of the cross-sectional configuration of the light receiving section (2) taken along line II in FIG. 4, and in this example, a P-type silicon substrate (1) is used. An N-type region (2) is formed in the base (1) to form a bulk channel (buried channel) type vertical shift register VR, and a sensor region 5ENS is formed between the base (1) and an insulating layer (7) such as SiO2. formed by.

Figure 6 is a sectional view taken along the line [-1 in Figure 4;
FIG. 7 is a vertical cross-sectional view of the temporary storage region PS, in which an N-type region (, 4) for a bulk channel is formed in a portion corresponding to the temporary storage region PS, and original signal charges are stored in the lever portion. The other N type region αQ is for the channel stopper region C8.

On the surface of the substrate (1) corresponding between the region (2) and αη, electrodes α frame and (to) are formed with a predetermined width so as to extend in the vertical direction, and one electrode The α barrel is used as an electrode for the channel stopper region C8, and the other electrode α is used as an electrode for the charge reading dart region ROG. A plurality of electrodes φ1 to φ4 for vertically transferring charges are further formed on the upper surface of the base (1).

FIG. 4 shows an example of the electrode shape. In this example, optical signal charges are vertically transferred using four electrodes φl to φ4, and the substrate (1) has an N-type region (2) formed thereon.
There are four electrodes φl to φ4 extending horizontally on the upper surface of the
are sequentially and alternately deposited in the vertical direction. Above the sensor region Shl:Ns are electrodes φ1 to φ4 as shown in FIG.
In order to avoid combing, each electrode has a comb-teeth shape, and the teeth of electrodes φ2 and φ3 and φ1 and φ4 face each other, and the tips of each electrode are partially overlapped. φl~
The formation position of φ4 is selected.

Each of these electrodes φl to φ4 is a sensor area BEN.
In order to extend horizontally without covering 1c on B, each electrode φ! The comb-shaped base (common electrode part) of ~φ4 is connected to the base (
1) A hole formed on the top surface. Therefore, the electrode structure in those parts becomes a two-layer structure (see FIG. 6).

However, in order to form a potential well as shown in FIG. 6, the second and fourth electrodes φ2. As shown in FIG. 8, φ4 is selected to be located below the first and third electrodes φl and φ3.

An example of the manufacturing method of such a light receiving section (15Q will be described later).The readout dart signal S shown in FIG. 9A is supplied to the readout dart electrode (1), and the transfer electrode φl~ Of φ4, the electrode part and φ2 are shown in Figure 9B.
The transfer lock CKI + CK2 shown in Figure C is connected to the other electrode φ3 and φ4, and the transfer lock CK3 shown in Figure C is connected to the other electrode φ3 and φ4.
+ CK4 is supplied.

The period of one field is divided into a light receiving period and a vertical blanking period V-BLK, and a blanking period V-BLK.
It is further divided into a Km output transfer period and an original signal charge transfer period. During these transfer periods, transfer locks CK1-CK4 of a predetermined level and a predetermined phase shown in FIG. 10 are supplied to the corresponding electrodes φ1-φ4.

During the light reception period, a dart signal S0 of a predetermined potential Vl (>0) is applied to the reading dart electrode (to), and the electrodes φ1 to φ4v are connected so that the vertical shift register VR also functions as an O-Murflow drain. In order to accumulate the overflowing optical signal charge, clocks CK1 to CK4 of a partial level selected to a predetermined potential are applied respectively. FIG. 6A shows an example of the potential well at that time.

During the light reception period, the optical signal charges photoelectrically converted in the sensor region 8EN8 are diffused in the directions shown by the arrows a r b h c... in FIG. 4 and accumulated in the potential well under the temporary storage region PS. (See Figure 7). At this time, the 611th
As shown in A, the potential of the bladder outlet region ROG has a depth corresponding to the t position 1, so during the light reception period, charges exceeding this potential are temporarily accumulated in the storage region PSK flow I.
When L is input (the potential at that time is shown by the dashed line), all of those charges become excess charges and flow into the vertical shift register (see Figure 8A).
. Therefore, it is necessary to sweep and transfer this excess charge in the first half of the vertical blanking period V-BLK.

During the sweep transfer period, the ff-) signal S. The read dirt area ROG is closed with full control (FIG. 9A). The potential at this time is shown by a dashed line in FIG. 6A. This is to prevent the optical signal charges accumulated in the temporary accumulation region ps from flowing out to the vertical shift register vR1111. In this state, excess charges are swept out and transferred based on the clocks CK, ~CK4 supplied to the electrodes φl~φ4.
Ru.

Transfer locks CKI and CK as shown in FIG.

are in phase, but their levels are different. Similarly, transfer locks CK3 and CK4 are in phase and have different levels.

The transfer lock CK1 + CKz is selected to have an opposite phase relationship. The transfer lock CK, ~CK40 level during the light reception period is selected as shown in Figure 9 B and C, so that the excess charge is are the second and fourth electrodes φ2. of the vertical shift register VR.
n is accumulated in the potential well corresponding to φ4.

During the sweep transfer period, the transfer lock CK shown in FIG.
~CK4 is added to the third and fourth transfer locks CKI-CK4 (time ta) at the start of the transfer.
The electrode φ3. Only the potential under φ4 changes, and every other stored charge (S, 8 in this example) is transferred and mixed with the remaining stored charges SB and SD (FIG. 8B). Next transfer timing (time tb
), the levels of all transfer locks CK, ~CK4 are reversed, so the formation position of the potential well shifts, and along with this, the charges (RA+SB) and (Sc+SD)
) moves. Charge transfer is performed in this manner.

Since the transfer locks CKI to CK4 are high frequency signals of several Zoo kHz, for example 600 kHz, high-speed transfer is performed. At this time, similar transfer locks are also supplied to the storage section (15B), so the signal carrier Not used as.

In addition, as shown in FIG. 10, the transfer lock CK.

The reason for changing the level of ~CK4 is to form a predetermined potential barrier in the transfer direction, as shown in Figure 8. After the sweep transfer is completed, the original optical signal charge is vertically Readout area RO for transfer to shift register VR
G'& is opened and the signal is read out.

The potential relationship at this time is shown in FIG. 9, and this [,!
: The resulting potential relationship is shown in FIG. 6B. As a result of this transfer, optical signal charges are accumulated in the vertical shift register (2) at the same positions as in the sweep transfer, so the original signal charges are accumulated as shown in FIG. 8A.

When the charge transfer period begins, predetermined transfer locks CKl-CK4 are supplied to the first to fourth electrodes φ1 to φ4, respectively, and the optical signal charge of the light receiving section (15A) is transferred at high speed to the storage section. ('15B) is stored at the corresponding position.

In order to perform all charge transfers taking interlace into consideration, for example, the phase of transfer locks CK to CK4 during the charge transfer period in that field may be set to be in opposite phase to that in the previous field. In this case, if the potential barrier at the time of transfer is taken into account, transfer locks CKI and CK3 should be swapped, and CK2 and CK4 should be swapped.By doing this, the potential well at time t& will be as shown in Figure 8. Become. This makes it possible to obtain optical signal charges on a horizontal line that is different from the horizontal line in the previous field.

FIG. 11 (Snorter) shows an example of a method for manufacturing the light receiving section (15A) according to the present invention. Figure A-E are ■-■ in Figure 4.
In the process drawings on the line, F-H in the same diagram is a process diagram on the I-1 line, which corresponds to F in the same diagram, and E in the same diagram corresponds to G in the same diagram.
corresponds to

First, an insulating layer (7) such as 8102 and 5lNN (T) are formed on the upper surface of the P-type silicon substrate (1) (A in the same figure).
Next, an electrode α frame made of silicon or the like is placed in a predetermined position.

After the θ field is deposited, ions for the N- type region are implanted over the entire surface (FIG. B). After forming the N-type region,
A resist layer <21) is deposited on the entire surface except for the vertical shift register ■ and channel block horn 9-C8 area.
Then, ions are further implanted into the same region to form an N-type region (FIG. C). Thereafter, the resist layer eη is removed and the second and fourth electrodes φ2. φ4 f) Z is formed (same figure, F), this
Next, the first and second layers, which are also made of polysilicon, etc.
The electrode φ1. φ3 power! Selectively formed transfer electrode φl
~ φ4 manufacturing process-1) E ends (E, G in the same figure).

Next, the SiN layer of the sensor region SENS is removed, and ions are implanted to make the N'''' type region α into a P type (see H in the same figure).

Through the above steps, the desired shadow of the light receiving portion (1sA) d' is formed.

Note that the transfer locks CK1''CK4 described above may be used as four-phase clocks.

In the case of interlace, change the level during the light reception period.
For example, there is no need to invert the clock during the transfer period for each field.

In addition, in the above description, the start r-to region ROG is always in the accumulation mode during the light reception period to cause the charge of the overdrive 1 to auto-flow into the vertical shift register (2), but it is set in the accumulation mode only during the horizontal blanking period. The solid-state imaging device to which the present invention is applied is not of the type shown in FIG. 3, but may be a solid-state imaging device using a normal interline transfer method.

As described in detail, this configuration has the following features compared to the prior art.

[F] Since the sensor configuration SEMS does not have an electrical contact layer such as polysilicon, the sensitivity, especially the short wavelength sensitivity, does not deteriorate.

■ During light reception, charges due to wavelength components photoelectrically converted deep inside the substrate (1) diffuse into the bulk.

Moreover, since the charge transfer is performed at high speed, the occurrence of smear can be suppressed.

■ During the light reception period, excess charge flows to the vertical shift register VR through the squeeze dirt region ROG, so blooming can be suppressed and the vertical shift register VR can also be used as an overflow drain, making the element surface more effective. It can be used for.

(2) Compared to the sensor configuration based on PH1 combination, the charges accumulated in the N-type region α are transferred, so the transfer is complete and there is less afterimage.

Furthermore, as shown in Fig. 11 GK, the sensor area 5ENs
If we leave the N-type toilet area formed inside and make the sensor area 5ENS by (N-P), then this sensor area I
The optical signal charge photoelectrically converted by Ns can be effectively and efficiently stored in the temporary storage region ps.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of essential parts of a conventional example of a solid-state image sensor, FIG. 3 is a plan view showing an example of a solid-state image sensor to which the present invention can be applied, and FIG. 4 is a solid-state image sensor according to the present invention. FIG. 5 is a plan view showing an example of the light-receiving part of the image sensor; FIG. 5 is a sectional view taken along the line I-1 and a diagram showing the potential with respect to the substrate surface; FIG. 6 is a sectional view taken along the line ■-■ and a diagram showing the potential. , Figure 7 is a cross-sectional view of the temporary storage area and its potential, Figure 8 is a vertical cross-sectional view of the vertical shift register, Figures 9 and 10 are waveform diagrams of the clock used, and Figure 1
FIG. 1 is a process diagram showing an example of a method for manufacturing a solid-state image sensor according to the present invention. α force is a solid-state image sensor, (15A) is a light receiving part, (15B)
is the storage part, (1) is the base of negative conductivity type, (2), α force is the area of other conductivity type, JLVR is the shift register, ROG is the read/output area, 5BNS is the sensor area, and C8 is the area of the other conductivity type. Channel stopper area, PS is temporarily accumulated @ completed, φ! ~
φ4 is a transfer charge.

Claims (1)

[Claims] A plurality of light-receiving regions arranged at predetermined pitches in the horizontal and vertical directions, a plurality of vertical shift registers extending in the vertical direction, and a plurality of light-receiving regions arranged in the vertical direction, respectively formed between the light-receiving regions arranged in the vertical direction, and adjacent to each other. A solid-state image sensing device comprising a temporary storage area in which optical signal charges that have been electrically converted in a light-receiving area are accumulated, and a readout dirt area formed between the temporary storage area and a vertical shift register.