JPS5818368Y2 - solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device using a charge transfer device CTD configuration, and particularly to a solid-state imaging device using an interline transfer type.

In order to facilitate understanding of the present invention, the general configuration of a general solid-state imaging device using one type of interline transfer will be explained with reference to FIG. A plurality of light receiving parts 1 each serving as a picture element are arranged on a substrate, for example a silicon substrate, in a row (for example horizontal) direction and a column (
For example, a CTD (Charge Coupled Device:
A vertical shift register 2 having a charge-coupled device configuration is arranged, and a common horizontal shift register 3 having a CCD configuration is provided at one end of each shift register 2.

Minority carriers generated in each light receiving section 1 according to the amount of light received are transferred to an adjacent vertical shift register 2, and in this shift register 2, each charge is shifted (transferred) in the vertical direction and shifted horizontally. The charges are sequentially transferred to the register 3, and the signals are sequentially taken out from the output terminal t of the horizontal shift register 3 for each horizontal line.

Furthermore, the specific structure of the light receiving section 1 and the corresponding vertical shift register 2 of the conventional solid-state imaging device having this configuration will be explained in detail with reference to FIGS. 2 and 3.

In this example, one principal surface 1 of a P-type silicon substrate 10 is
Facing 0a, a channel stopper region 11 having the same conductivity type as the substrate 10 but having a sufficiently higher impurity concentration than the substrate 10 is formed by, for example, selective diffusion.

Although this channel stopper region 11 is provided with a portion 11a between each light receiving section 1 and the corresponding vertical shift register 2, the other portions of the light receiving section 1 are arranged so as to surround this and It is formed extending along the shift direction of the vertical shift register 2 between the corresponding light receiving section 1 and the light receiving section on the opposite side.

For example, on the main surface 10a of the semiconductor substrate 10, 5
An insulating layer 12 of i02 is applied over the entire surface.

On this insulating layer 12, on the cutout part 11a of the channel stopper region 11 between the light receiving section 1 and the vertical shift register 2 adjacent thereto, a gate is provided in common to the light receiving section 1 on each vertical line. Electrode 13 is applied.

In addition, each vertical shift register 2 has a storage gate electrode 14A and a transfer gate electrode 14B corresponding to each light receiving section 1, respectively, in a common shift direction (vertical direction) indicated by an arrow a with respect to each vertical shift register 2. The pattern is formed along the intersecting direction (that is, the horizontal direction) so as not to straddle each light receiving section 1.

In this case, the thickness of the insulating layer 12 in the shift register 2 is different between the portion located under the storage gate electrode 14A and the portion located under the transfer gate electrode 14B. When the same voltage is applied to both, the potential for minority carriers (electrons) is different under the storage gate electrode 14A and under the transfer gate electrode 14B. It is designed to create a relatively deep well of potential.

Further, each electrode 14A and 14B is covered with, for example, 5i02.
An insulating layer 15 is deposited on top of this, and a transparent electrode 16, for example, a sensor electrode 16 made of NESA, is deposited over the entire surface of the light-receiving section 1 at least.

Reference numeral 17 denotes a light shielding body, and the light shielding body 17 has a window formed above the light receiving section 1 .

Reference numeral 19 denotes an overflow drain region, which is provided adjacent to at least a portion of each light receiving section 1 and is of a conductivity type different from that of the base 10, in this example an N type region, and is a region where excessive light is generated due to the incidence of strong light. It serves to remove the carrier.

In such a configuration, an adjacent pair of storage gate electrodes 14A and transfer gate electrodes 14B corresponding to each light receiving section 1 are connected to each other to form electrodes 14.

Then, every other electrode 14 is connected alternately to lead out terminals t□ and t2, respectively.

To explain the case where signal readout is performed by interlaced scanning in a solid-state imaging device with such a configuration,
First, during the light reception period, that is, during the charge transfer in the vertical and horizontal shift registers 2 and 3,
For example, if the gate electrode 13 between the light receiving section 1 and the shift register 2 is in an Ov state in which no voltage is applied, and a predetermined positive voltage v8 is applied to the sensor electrode 16 in this state, the voltage of the base 10 changes depending on this voltage v8. Regarding the potential for minority carriers (electrons) on the surface, a potential well is generated under the light receiving section 1, as shown by the broken line 18 in FIG.

Therefore, when light enters the light receiving section 1 in this state, minority carriers generated in response to this light are accumulated in the well of the potential 18 and the potential here rises, but there is no potential below the gate electrode 13. The barrier 8a prevents this from flowing into the shift register 2.

In this state, first, in the first (odd-numbered field), a positive voltage φ1 is applied to the terminal t0, and a voltage of Ov, for example, is applied to the terminal t2.

When a predetermined positive voltage V is applied to the gate electrode 13, the barrier 8a is lowered as shown by the chain line 18' in FIG. 3, while the storage gate to which the predetermined positive voltage φ1 is applied Since a potential well is generated under the electrode 14A, iterative charges stored in the light receiving section 1 are transferred to the storage gate electrode 14A of the shift register 2.
transferred to the bottom.

In this state, two-phase clock φ1 is applied to terminals t□ and t2,
By sequentially applying φ2, the charge is transferred in a predetermined direction, the direction shown by arrow a in FIG. and its charge is transferred.

Then, in the next even-numbered field, contrary to what has been described above, by applying a positive voltage φ2 to the terminal t1 and OV1 and the terminal t2, the charges in every other light receiving section 1 are transferred to the shift register 2. Therefore, if two-phase clock voltages are applied to terminals t and t2 in shift register 2, this can be transferred in the direction of arrow a and transferred to horizontal shift register 3. .

As schematically shown in FIG. 4, the arrangement relationship between the light receiving section 1 of the solid-state imaging device using interline transfer type with such a configuration and the corresponding vertical shift register 2 is as shown schematically in FIG. On the other hand, it has a complicated configuration in which two electrodes 14A and 14B are arranged, and a gate electrode 13 is further arranged between each light receiving section 1 and the shift register 2. Therefore, in this case, the same picture element Either the area occupied by the number of pixels becomes too large, or the number of picture elements that can be accommodated in the same area is limited.

Furthermore, in the case of the above-described configuration, there is a space between adjacent electrodes 14,
Clock φ0. of different voltages, that is, two phases. φ2, but in practice, when two devices are manufactured, each storage gate electrode 14A of each electrode 14 is constituted by a common conductive layer, and each transfer gate electrode 14B is constituted by another common conductive layer. Therefore, there is a risk that a short circuit may occur between adjacent electrodes of both sets.

The present invention aims to provide a novel solid-state imaging device that can completely eliminate the above-mentioned drawbacks.

That is, in the present invention, as explained in FIG.
By specially selecting the arrangement of the electrodes of the vertical shift register 2 and the vertical shift register 2, it is possible to simplify the pattern, thereby increasing the number of picture elements per unit area or reducing the area, and further avoiding short-circuit accidents between the electrodes. This is how it was done.

First, the schematic configuration of the device of the present invention will be explained with reference to FIG. The mold configuration is such that the first, second and third electrodes 21A, 21B and 21C are arranged in sequence.

Then, a set of three-phase electrodes constituting the vertical shift register 2, that is, first, second, and 3 electrode 21A.

21B and 21C are provided so as to correspond to each other.

As a gate electrode between each light receiving section 1 (Sl and S2) and the corresponding vertical shift register 2, two electrodes constituting this vertical shift register 2, for example, the first electrode 21A and the second electrode 21B themselves are used. Corresponding light receiving section S1
, S2 by 1.

Next, an embodiment of the present invention will be explained in detail with reference to FIGS. 6 to 8. FIG. 6 shows the light receiving section 1 of the device of the present invention and the corresponding vertical shift register 2. Figures 7 and 8 are partially enlarged top views showing the relationship.
They are cross-sectional views on the line -■ and the line ■-■.

In this example as well, a P-type semiconductor substrate 20 is provided, and a high impurity concentration channel stopper region 22 having the same conductivity type as the substrate 20, e.g. P type, is formed facing the main surface 20a of the substrate 20 by selective diffusion, for example. Alternatively, the channel stopper region 22 formed by a well-known technique such as ion implantation may be formed between the light receiving section 1 on each line (for example, a vertical line) and a vertical shift register that does not correspond thereto, as usual. It is formed to extend in the shift direction, that is, in the vertical direction, and surrounds each light receiving section 1, and each light receiving section 1
A deletion portion 22 is provided between the vertical shift register 2 and the corresponding vertical shift register 2.
A is formed into a pattern.

Reference numeral 23 denotes an overflow drain region, which is a region of a conductivity type different from that of the base body 10, in this example an N type, and is formed to extend in each line of each light receiving section 1, that is, in the vertical direction, for example.

In this case, a cutout 22b is formed in the channel stopper region 22 so that the overflow drain region 23 and each light receiving section 1 can be adjacent to each other.

An insulating layer 23 made of, for example, 5i02 is deposited on the main surface 20a of the base body 20 by a well-known technique, and a first conductive layer is first deposited over the entire surface thereof.

This first conductive layer may be composed of, for example, a polycrystalline silicon layer doped with impurities.

This first conductive layer is then photo-etched to remove unnecessary portions to form a first electrode 21A in a desired pattern. 2, over the entire width of the area defined by the channel stopper regions 22 on both sides thereof, and having the required length 11 with respect to the vertical shift direction of each vertical shift register 2. A cutout part 21a having a length of 11 is formed, and the cutout part 21a is formed so as to extend over the cutout part 22a of the channel stopper area 22 provided for every other light receiving part S1 corresponding to each shift register 2. Form.

Next, the surface of the polycrystalline silicon layer forming the first electrode 21A is thermally oxidized, for example, by S102.
An insulating layer 24 is formed, and a second electrode 2 is formed on this.
1B, a polycrystalline silicon layer doped with impurities is deposited over the entire surface and photoetched to form the second electrode 21 in the desired pattern.
Form B.

The second electrode 21B is formed over the entire width of the shift register 2 at least on a portion of one end of the cutout 21a of the first electrode 21A adjacent to the first electrode 21A, and is formed over the entire width of the shift register 2. It is formed over the cutout portion 22a of the channel stopper region 22 provided for the alternate receiving portion S2.

In this second electrode 21B, a cutout 21b is formed on the other part on the cutout 21a of the first electrode 21A.

Similarly, the surface of the second electrode 21B is covered with an insulating layer 25 by thermal oxidation, for example, and a conductive layer constituting the third electrode 21C is deposited thereon.

This conductive layer can be formed from a low resistivity polycrystalline silicon layer as described above.

The third electrode 21C may be formed, for example, over the entire width of each vertical shift register 2 so as to cover at least the cutout portion 21b of the second electrode 21B of each vertical shift register 2.

Note that even when the first, second, and third electrodes 21A, 21B, and 21C are respectively formed from light-transmitting polycrystalline silicon layers, these electrodes 21A, 21B, and 21C cannot straddle the light receiving section 1. It is desirable to avoid this, and when doing so, it is possible to avoid a decrease in sensitivity on the short wavelength side when receiving light through a polycrystalline silicon layer.

Then, a sensor electrode 27 made of a transparent conductive layer, for example NESA, is formed at least on the light receiving section 1.

The sensor electrode 27 can be entirely deposited on the substrate 2o, including the electrode 21C, with an insulating layer 26 made of, for example, SiO interposed therebetween.

Then, the base body 20 is covered with a light shielding body 28.

A window 28a is bored in this light shielding body 28, and the light receiving part 1 (Sl
and S2) are exposed to the outside.

jAt tB , tc and t8 are terminals led out from the first electrode 21A, second electrode 21B1, third electrode 21C and sensor electrode 27, respectively.

According to such a configuration, the first electrode 21A or the second electrode 21B of the second electrode 21B or the third electrode 21C
Since the magnetic field of the portion formed above is blocked by these electrodes 21A or 21B and does not affect the base body 20, each shift register 2 has a magnetic field substantially in the shift direction, that is, in the corresponding direction. The arrangement direction of the light receiving sections 1 (
The electrodes 21B of the first electrodes 21A42 are sequentially and alternately placed on the surface 20a of the base 2o via the insulating layer along the vertical direction).
- The third electrode 21C is arranged, and the first, second, and third transfer regions T 1 , T 2 , and T 2 are sequentially arranged.

The first electrode 21A and the second electrode 21B extend between each shift register 2 and every other corresponding light receiving section s1 and 82 to form gate sections G1 and G2, respectively. The structure is as follows.

Next, the operation of the device according to the present invention having this configuration will be explained with reference to FIG.

9A, B, C and D are terminals 1. 1. 1
and t, that is, the first, second, and third electrodes 21A, 21B,
21C and a voltage diagram applied to the sensor electrode 27. FIG.

First, the required positive voltage is now applied to the terminal t, i.e. the sensor electrode.
For example, assuming a state in which IOV is applied, a potential well for minority carriers (electrons) is generated under the light receiving part 1, so minority carriers (electrons) corresponding to the light receiving part received through the window 28a are accumulated here. be done.

First, in odd-numbered fields, carriers, that is, signal charges, are extracted from every other light receiving section S.

Therefore, first, the signal charge of this light receiving section S1 is transferred to the corresponding vertical shift register 2 during a period r, for example, a vertical blanking period.

In this transfer, first, a required positive voltage, for example, IOV, is applied to the terminals t 1 and t 2 , that is, the first and second electrodes 21A and 21B, and the terminal t 2 , that is, the third electrode 21C is set to ov.

Then, in this state, the voltage of the sensor electrode 27 is changed to Ov.

Thus, in the gate parts G 1 and G 2 where the first and second electrodes 21A and 21B are formed, and the first and second transfer regions T 1 and T 2 of the shift register 2,
A potential valley is generated for the signal charge, and the third electrode 2
A potential barrier occurs in the third transfer region T3 where 1C is formed.

Therefore, the signal charges generated in every other light receiving section S are transferred to the gate section G0 and the first and second transfer regions T and T of the shift register 2 connected through this, but The signal charges generated in the other light receiving section S cannot be transferred to the shift register 2 because a potential barrier is generated in the third transfer region T 2 of the shift register 2 which is continuous through the gate section G2.

Next, the voltage applied to the second and third electrodes 21B, 21C and the sensor electrode 27 is maintained at that tx, and the voltage applied to the first electrode 21A is
Let Ov be the applied voltage.

Thus, the signal charge from the light receiving section S1 mentioned above is
They are collected only in the second area T2 of the shift register 2.

Thereafter, during the shift period τS□ of the shift register 2, for example, one vertical effective scanning period, as shown in FIGS. 9A, B, and C, three-phase clock voltages φ0. φ2゜φ3 first
, second and third electrodes 21A, 21B.

21C, and in each horizontal blanking period, the signal charges are sequentially transferred to the next stage transfer area, that is, shifted in the direction already shown by the arrows in FIGS. Transfer to shift register.

In this case, in the shift register 2, in addition to preventing the signal charge from flowing in the opposite direction to the shift direction, the first and second electrodes 21A and 21B are connected to the first and second gate portions G1. Since the clock voltage also serves as the gate electrode of G1 and G2, the phase and waveform of the clock voltage are selected so that the signal charge does not flow into the light receiving part 1 (Sl and S2) through the gate parts G1 and G2 during this shift. do.

That is, at least while the voltage to the first and second electrodes 21A and 21B changes from a positive voltage (for example, +10V) to Ov, the electrodes 21B, 21C, and 21A at the next stage change to a positive voltage. Let it change.

Therefore, the waveforms of the clock voltages applied to the first to third electrodes can be trapezoidal as shown by the solid lines in FIGS. 9A to 9C, or stepwise as shown by the broken lines. .

Furthermore, the clock voltage applied to the third electrode 21C can also have a rectangular shape as shown by the thin chain line.

Note that during this period τS, the sensor electrode 27 has:
Apply positive voltage.

Then, in the next even-numbered field, the minority carriers (electrons), that is, signal charges generated by the light reception by the other every other light receiving section S2 are transferred to the shift register 2 for a period τT2.
That is, the data is transferred during the next vertical blanking period.

This transfer is performed by applying a positive required voltage, for example +IOV, to the terminals tA and tc1, that is, the first and third electrodes 21A and 21C, as shown in FIGS. That is, the second electrode 21B is set to OV.

In this state, the voltage of the sensor electrode 27 is changed to Ov.

In this way, the first and third electrodes 21A and 21C are formed and the gate part G2 and the first gate part G2 of the shift register 2 are formed.
In the third transfer regions T0 and T3, a potential valley with respect to the signal charge occurs, and a potential barrier occurs in the gate tlG1 where the second electrode 21B is formed and the second transfer region T2. .

Therefore, only the signal charges generated in every other light receiving section S2 are transferred to the gate section G2 and the third and first transfer regions T3 and To of the shift register 2 connected through this. The signal charges generated in the alternate light receiving portions S0 cannot be transferred to the shift register 2 because a potential barrier is generated in the gate portion G□.

Then, the voltage applied to the first and second electrodes 21A, 21B and the sensor electrode 27 is maintained at that level, and the voltage applied to the third electrode 21
Let OV be the voltage applied to C.

Thus, the signal charge from the light receiving section S2 mentioned above is
They are collected only in the first area T1 of the shift register 2.

Thereafter, during the shift period τs2 of the shift register 2, for example, during one vertical effective scanning period, FIG. 9A.

As shown in B and C, the three-phase clock voltage φ1゜φ2
．． φ3 is the first, second, and third electrodes 21A, 21B.

21C, and in each horizontal blanking period, the signal charges are sequentially transferred to the next transfer region, that is, shifted in the direction already shown by the arrows in FIGS. 6 and 8, although not shown. In this way, for example, in the odd-numbered field, the signals obtained from every other light receiving section S□ are read out, and in the even-numbered field, the signals obtained from every other light receiving section S2 are read out. The obtained signal can be read out, and a television video signal can be obtained by so-called interlaced scanning.

As described above, according to the device of the present invention, the electrodes arranged in the shift direction of the shift register (in other words, the transfer area) are arranged in one set of three for the two light receiving parts S1 and S2 (i.e., two picture elements). Moreover, since the gate electrode provided between each light receiving part and the shift register is also used by two electrodes of the shift register, the pattern is simplified and the number of picture elements per unit area is reduced. It is possible to increase the area or reduce the area.

Moreover, since each of the first to third electrodes 21A to 21C to which independent voltages are applied is formed of an independent conductive layer, it is possible to avoid short-circuit accidents.

In the above example, the positive applied voltage value to the first to third electrodes is the same, but in reality, each transfer region T
If the insulating layer under each of the electrodes 21A to 21C in □ to T3 is composed of a single layer, two layers, or three layers, and the substantial thicknesses thereof are different, the voltage values can be different from each other.

Further, in the above-mentioned example, the base body 20 and the channel stopper region 22 are of P type, and the overflow drain region 23 is of N type.
However, when selecting these to be of opposite conductivity type, the voltage applied to each electrode may be selected to have a polarity opposite to that described above.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional solid-state imaging device using an interline transfer method, FIGS. 2 and 3 are enlarged top views and cross-sectional views of the main parts thereof, and FIG. 4 is a schematic configuration diagram for explaining the same. FIG. 5 is a diagram showing a schematic configuration of a solid-state imaging device according to the present invention, FIG. 6 is an enlarged top view of essential parts of an example of the device according to the present invention, and FIGS. 7 and 8 are on the line ■-■ in FIG. 6. and ■−
(2) An enlarged sectional view along the line, and FIG. 9 is a waveform diagram for explaining the operation of the device of the present invention. 1 is a light receiving section, 2 is a vertical shift register, 3 is a horizontal shift register, t is an output terminal, 20 is a semiconductor substrate, 22 is a channel stopper region, 23 is an overflow drain region, 24, 25 and 26 are insulating layers, 21A, 21B
and 21C are first, second, and third electrodes, 27 is a sensor electrode, and 28 is a light shield.

Claims (1)

[Scope of utility model registration request] A plurality of light receiving sections are arranged on the semiconductor substrate, and a shift register is arranged along the arrangement line of the light receiving sections, and the shift register has first and second light receiving sections for two adjacent light receiving sections on the arrangement line. and a third conductive layer;
Second and third electrodes are arranged on the semiconductor substrate via an insulating layer and insulated from each other and alternately in the shift direction, and are arranged on the semiconductor substrate between each of the light receiving sections and the shift register. A gate portion is formed by extending one or two corresponding electrodes of the three electrodes of the shift register corresponding to each of the light receiving portions, and three electrodes are formed on the first, second and third electrodes. A solid-state imaging device in which charge transfer is performed by applying a layer clock voltage.