JPS5946155B2 - solid state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device, particularly to a solid-state imaging device using an interline shift method.

As shown in FIG. 1, the basic structure of a solid-state imaging device using an interline shift method is such that a plurality of light receiving sections 1, each serving as a picture element, are arranged on a common semiconductor substrate in a row (horizontal) direction and a column (vertical) direction. A CCD (charge coupled device) is arranged on one side of the light receiving section 1 of each row.
A vertical shift register 2 having a structure is arranged, and one end of each shift register 2 is provided with a common horizontal shift register 3 having a CCD structure as well.

The vertical shift register 2 has a transfer section provided corresponding to each adjacent light receiving section 1, and transfers minority carriers generated in each light receiving section 1 according to the amount of light received for each vertical line. , to the corresponding transfer section of the corresponding vertical shift register 2, and in each of these shift registers 2, shift the charge in each transfer section to the horizontal shift register 3,
The signals are sequentially taken out from the output terminal of the shift register 3 for each horizontal line. The specific structure of a conventional imaging device with such a configuration, in particular the structure of the light receiving section 1 and the portion that transfers the charge of the light receiving section 1 to the vertical shift register 2, will be described with reference to FIG. A semiconductor substrate 10 is provided with a light receiving section 1 and a shift register 2 adjacent thereto.

The light receiving section 1 is made of an insulating layer, that is, SiO2, formed on the base 10.
A sensor 12 made of a transparent electrode is attached via a layer 11, and transfer sections of the vertical shift register 2 are provided adjacent to the light receiving sections 1, and these transfer sections are connected to the base 10.
The storage gate electrode 13 is connected to the storage gate electrode 13 via the insulating layer 11 provided above, and this storage gate electrode 13 is connected to the storage gate electrode 13 through the insulating layer 11 provided above.
A transfer gate electrode is formed by depositing the lower insulating layer 11 and insulating layers having different thicknesses. Similarly, a gate electrode 14 is provided between the light receiving section 1 and the shift register 2 with an insulating layer 11 interposed therebetween. Reference numeral 15 indicates a channel stopper region formed of a region having the same conductivity type as the basic body 10 but with a higher concentration than the basic body 10, and 16 indicates a light shielding layer formed in a portion other than the light receiving portion 12.

In an imaging device having such a configuration, carriers corresponding to light incident on the light receiving section 1 are transferred to each transfer section of the shift register 2 by a gate voltage applied to the gate electrode 14, and are transferred in the vertical direction. To explain the operation in this case, the storage gate electrode 1
3 is applied with a predetermined negative voltage φ, and a predetermined negative voltage Vs is applied to the transparent electrode of the light receiving section 1, that is, the optical information storage electrode 12, but when no voltage is applied to the gate electrode 14, , the potential on the surface of the substrate 10 is as shown by the broken line 17.

In this state, when light enters the light receiving section 1, charges are accumulated in the well of the potential 17, and the potential here rises, but this is prevented because a potential barrier 17a is formed under the gate electrode 14. It does not flow to the transfer section of the shift register 2. From this hypocrisy, next
When a predetermined negative voltage Vt is applied to the gate electrode 14, the barrier 17a is lowered as shown by the chain line 17' in the figure, and the charge stored in the light receiving section 1 is transferred to the transfer section of the shift register 2. be done. The charges transferred under the storage gate electrode 13 of the shift register 2 are transferred to a two-phase or three-phase vertical shift register (not shown).
By applying phase clock pulses, this charge is shifted in the vertical direction, that is, in the direction perpendicular to the plane of the paper in FIG. 2, and transferred to the horizontal shift register 3 explained in FIG. be. By the way, in this type of conventional solid-state imaging device, due to the presence of the optical information storage electrode 12 made of a transparent electrode or the like over the entire surface of the light receiving section 1,
The light is received through the electrode 12, which has the disadvantage of reducing the light receiving sensitivity.

Further, in addition to forming the electrode 12 on the light receiving section 1, the light shielding layer 16 must be formed on the entire surface of the area other than the light receiving section 1, which has the disadvantage that the manufacturing process becomes extremely complicated. The present invention aims to provide a novel solid-state imaging device using the interline shift method, which eliminates the above-mentioned drawbacks.

An example of the solid-state imaging device according to the present invention will be described with reference to FIGS. 3 to 7. FIG. 3 is a top view of the main parts of the device of the present invention, and FIGS. Figures 3 and 7 are respectively
It is an enlarged sectional view on the line AA, the line BB, the line CC, and the line DD in the figure. In the present invention, as explained with reference to FIG. 1, the common semiconductor substrate is provided with a light receiving section and vertical and horizontal shift registers. For example, only the connection between the two and a vertical shift register is illustrated,
And this will be explained.

In the present invention, conductivity type 1, for example N? A plurality of light receiving sections 1 are formed on a silicon semiconductor substrate 10 having a plurality of rows and columns, and a transfer section is formed adjacent to each light receiving section 1 on each vertical line (column direction). A shift register section 2 is formed.

The vertical shift register section 2 is composed of these shift register sections 2.
Transfer gate electrodes 20 and storage gate electrodes 13 are arranged alternately with respect to the charge shift direction (vertical direction) in common with respect to the transfer sections on the respective common horizontal lines. The storage gate electrode 13 has a thickness of T,
For example, a transfer gate electrode 20 is deposited through an insulating layer 11 having a thickness T2 between adjacent storage gate electrodes 13.
is coated with. Here, the thickness T of the insulating layer 11 and T
2 is selected as T,<T2. On the surface of the base 10,
A channel stopper region 15 having the same conductivity type as the substrate 10 and having a sufficiently higher impurity concentration than the substrate is provided between each of the light receiving sections 1 and between the light receiving section 1 and the shift register section 2 which do not correspond to each other. Form. In this example, a channel stopper region 15A in the column direction extending between the light receiving section 1 and the shift register section 2, which do not correspond to each other, and a channel stopper region 15B between each light receiving section 1 are formed continuously. Further, an extension part 21 of the channel stopper region 15 is formed under the storage gate electrode 13 extending between the light receiving part 1 and the corresponding transfer part of the shift register part 2.
A channel stopper region 1 is provided under the transfer gate electrode of each transfer section of the shift register section 2 corresponding thereto.
A charge transfer path 22 is formed which transfers the charge from the light receiving section 1 to the shift register section 2 sandwiched by the extension section 21 of the light receiving section 5 .

In this case, the width WO of the charge transfer path 22 is selected to be a width that can be influenced by the potential of the channel stopper region 15. In the present invention, the light receiving section 1 is formed in a portion corresponding to the cutout window 23 of the storage gate electrode 13 and the transfer gate electrode 20, but in this case, in particular, An insulating layer, e.g., a SiO2 layer 11, is deposited on the substrate 10 corresponding to the window 23, and the window 23 is formed by leaving a half of the window 23 far from the charge transfer path 22, that is, a window portion 23s on the side where the storage gate electrode is removed. The other half near the passage 22, that is, the transfer gate electrode 20
A metal layer 25 that can serve as a light-shielding layer is deposited on the entire surface including the window portion 23t and the shift register portion 2 on the side of the cutout through an insulating layer.

Then, the window 23s to which only the transparent insulating layer 11 without the metal layer 25 is deposited becomes the substantial light-receiving part 1, that is, the carrier generating part, and the window 23t adjacent thereto is made to be the substantive light receiving part 1, that is, the carrier generating part The metal layer 25A is configured as a carrier storage section with a so-called optical information storage electrode, that is, a carrier storage electrode. Next, in order to facilitate understanding of the structure of the solid-state imaging device according to the present invention described above, an example of its manufacturing method will be explained with reference to FIG. The figure corresponds to the AA cross section in FIG. First, as shown in FIG. 8A, a silicon semiconductor substrate 10 of conductivity type 1 is
The SiO2 film 24 on the surface is selectively etched into a predetermined pattern, and impurities of the same conductivity type as the substrate are diffused through the removed window holes to form the channel stopper region 15 and its extension 21 (not shown). ) to form (8th
Next, the channel stopper area 15 and the extension part 2 are shown.
After forming a SiO2 film 11 of a predetermined thickness by thermal oxidation on a substrate 10 containing 1, a polycrystalline silicon layer doped with a high concentration of P-type or N-type impurities is formed on this SiO2 film 11. A resistivity silicon layer 26 is formed (FIG. 8C' and D).

As shown in FIG. 8E, this polycrystalline silicon layer 26 is photoetched to remove unnecessary portions, and the storage gate electrode 13 is formed using this layer 26.

At this time, the storage gate electrode 13 simultaneously forms a window 23s due to the cutout shown in FIG. Next, as shown in FIG. 8F, SiO is grown by chemical vapor deposition or thermal oxidation.
2 film 11 is formed on the entire surface.

Next, as shown in FIG. 8G, a polycrystalline silicon layer 27 doped with P-type or N-type impurities at a high concentration is deposited on this SiO2 film 11, and this polycrystalline silicon layer 27 is photoetched. Transfer gate electrode 20 is formed by removing unnecessary portions. At this time, the transfer electrode 20 has a window portion 2 due to the cutout shown in FIG.
3t is formed at the same time (FIG. 8H). Next, after forming the SiO2 film 11 on the entire surface by chemical vapor deposition or thermal oxidation (FIG. 8 1), the SiO2 film 11 is formed on the window 23tf where the optical information storage electrode 25A is to be formed. is selectively removed, and a new SiO2 film 11 of a predetermined thickness is formed here (FIG. 8J).

Thereafter, a light-blocking metal layer 25 such as At is deposited on the entire surface except for the window portion 23s which is to become the light-receiving portion 1.

Next, the operation of the apparatus of the present invention having the above-described configuration will be explained.

The metal layer 25 which also serves as the optical information storage electrode 25A has a structure shown in FIG. 9A.
A voltage having a waveform as shown by reference numeral 30 is applied to. This is because in the light receiving section τ8, that is, the period in which vertical shifting is performed in the shift register section 2, a negative predetermined voltage Vs, for example, -10V is applied, and the signal charge is transferred from the light receiving section 1 to the shift register section 2. In the interval τt, a smaller transfer voltage s', for example, -8 to -5V is applied. Further, the electrodes on each transfer section of the shift register section, that is, the mutually adjacent transfer gate electrodes 20 and storage gate electrodes 13, are connected to each other to form every other transfer section, that is, every other set of gates. Electrode 20, 13VC. 2 each
The clock pulse voltages φ, , φ2 of the set are shown in FIG. 9B and C.
In the middle, the numbers 31 and 32 are given as shown. Now, in the light receiving period τ8, the voltage 8 applied to the optical information storage electrode 25A is
is applied with a negative voltage of, for example, -10V, and a clock pulse φ, for example, with a negative voltage of -10V, is applied to the transfer gate electrode 20 and storage gate electrode 13 of the transfer section of the shift register section 2. The potential on the surface of the base 10 in each part of the optical information storage electrode 2 is as shown by the broken line 33 in FIGS. 4, 5, and 6.
A potential well 33a is formed directly below the channel stopper region 15, and a potential peak 33b is formed in the area where the channel stopper region 15 is present. One area 1
5 in the charge transfer path 22, the portion 33cVC.5 shown by the broken line 33 in FIG. As shown, a potential mountain (barrier) is formed. In FIGS. 5 and 6, portions 33f and 33g are potential wells generated by applying the clock pulse voltage φ1 or φ2, respectively. Now in this prone position, light receiving section 1
That is, when light enters the window portion 23s, minority carriers (holes) are generated according to the amount of received light, and these minority carriers -
A voltage of 10 V is applied, and the light is diffused and accumulated under the optical information storage electrode 25A where a potential well 33a is formed, and this potential well 33a rises. The carriers thus accumulated according to the amount of received light are transferred to the shift register section 2 in the next section τt. That is, in this interval τt, as explained in FIG. 9A, the optical information storage electrode 25A has a voltage of -8V to
A small transfer voltage of -5V is applied, but at this time, if a clock pulse voltage φ of -10V is applied to every other transfer section, that is, every other set of electrodes 20 and 13. As shown in FIGS. 5 and 6, potential wells are generated in the transfer section of the shift register section 2 to which this clock pulse voltage .phi.1 is applied, as shown in sections 33f and 33g, respectively. Therefore, if the voltage applied to the optical information storage electrode 25A is made small here, the electrode 25A
The surface potential under A rises as shown by the broken line 34 in FIG.
It is transferred to the potential well 33g below and further to the potential well 33f below the storage gate electrode 13.
will be accumulated here. Note that the width W8 of the pulse applied to the optical information storage electrode 25A in the interval τt is the width W of the clock φ,
Select less than 1. After the charge generated in the light receiving section 1 is transferred to the shift register section 2, a large negative voltage, for example -10V, is applied to the optical information storage electrode 25A again.
is applied to the light receiving state, and a two-phase clock pulse voltage φ1 is applied to adjacent sets of electrodes of the shift register.
and φ2 are given, whereby the charges are sequentially transferred in the vertical direction and transferred to the horizontal shift register 3 as explained in FIG.

Then, in the next interval τt, the clock pulse voltage φ2 is applied to the electrodes 20 and 13 of every other transfer section of the shift register section 2, and the -8
By applying a transfer voltage Vs/ of V to -5V,
Carriers are transferred from the light receiving unit for every other horizontal line, and in the next section τ8, the carriers are shifted in the vertical direction to sequentially read out the signals of every other horizontal line.

According to the above-described configuration of the present invention, since there is no optical information storage electrode such as a conventional transparent electrode in the window portion 23s that substantially receives light, this electrode reduces or impairs the light receiving sensitivity. Never.

Furthermore, since the electrode of the carrier accumulation section generated in the light receiving section 1, that is, the optical information storage electrode 25A and the light shielding layer 25B can be formed simultaneously using the common metal layer 25, the manufacturing process of this type of solid-state imaging device can be simplified. can be simplified. Furthermore, the structure is simplified because the charge transfer from the light receiving section 1 is carried out without the need to provide a special electrode between the light receiving section 1 and the corresponding shift register section 2. ,
Moreover, in that case, the optical information storage electrode 25A is formed nearer to the charge transfer path 22, and the substantial light receiving section 1 is formed further away, so that the shift register can be connected from the receiving section 1. Charge transfer to portion 2 can be performed satisfactorily. still,
In the above example, a two-phase clock type configuration has been described, but a three-phase clock type configuration is also possible.

Further, although the above example is applied to a two-dimensional solid-state imaging device, it can also be applied to a so-called one-dimensional solid-state imaging device with one vertical line.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of an interline shift type solid-state imaging device, FIG. 2 is a sectional view of the main parts thereof, FIG. 3 is a top view of the main parts of the solid-state imaging device according to the present invention, and FIG. Figures 5, 6, and T are an enlarged cross-sectional view taken along the line A-A, an enlarged cross-sectional view taken along the line B-B, an enlarged cross-sectional view taken along the line C-C, and an enlarged view taken along the line D-D in Figure 3, respectively. 8 is a cross-sectional view showing an example of the manufacturing method of the device of the present invention in the order of steps, and FIG. 9 is a diagram for explaining the operation of the device of the present invention. 1 is a light receiving part, 2 is a shift register part, 3 is a horizontal shift register part, 11 is an insulating layer, 13 is a storage gate electrode, 15 is a channel stopper region, 20 is a transfer gate electrode, 23 is a window, and 25 is a 25A is a metal layer, an optical information storage electrode, and 25B is a light shielding layer.

Claims (1)

[Claims] 1. A carrier storage device having a shift register section in which transfer gate electrodes and storage electrodes are arranged alternately, and a light receiving section, a carrier generation section in a part of the light receiving section and a carrier storage electrode in the other part of the light receiving section. Each department is composed of
A light-shielding layer is disposed on the entire area other than the light-receiving part, including the shift register part, with an insulating layer interposed therebetween, and the carrier storage electrode and the light-shielding layer are integrally formed of a common metal layer. Imaging device.