JPS59205631A - Data processing circuit - Google Patents

Abstract

PURPOSE:To obtain a data processing circuit which receives no limit of the upper limit working frequency by providing an output circuit which reads in the output of the 1st delay circuit following an input circuit with the output of the 2nd delay circuit following a logical circuit which decides the data contents. CONSTITUTION:The n-bit series data is read into the 1st and 2nd input circuits 8a and 8b of an input circuit 8 from a data input terminal 2. A condition deciding circuit 9 delivers a deciding signal 9a when the read-in data satisfies the conditions. The 2nd delay circuit 10 delivers a synchronizing signal 10a with a delay of a clock by the input of the signal 9a. While the data read into circuits 8a and 8b are read into the circuit 8b and the circuit 8c with the input of a clock. Therefore an output circuit 11 can read out the n-bit data of circuits 8b and 8c with the input of the signal 10a. Thus the data can be processed regardless of the delay of the circuit 9, that is, without receiving no limit of the upper limit working frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing circuit that reads data in synchronization with continuous clock pulses and performs processing according to the content of the data.

Generally, in this type of data processing circuit, it is necessary to determine within one clock cycle whether data read into an input circuit satisfies a certain condition for data processing. This is because the clock pulses are continuous, and different data is sent in the next clock pulse.

FIG. 1 is a block diagram showing a conventional data processing circuit. In the figure, (1) is a clock pulse input terminal to which clock pulses are input, (2) is a data input terminal to which serial data is input, (3) is an n-bit input circuit, and (4) is a data input terminal to which serial data is input.
(5) is an input circuit (3) that outputs a first judgment signal (4a) when the read n-bit data satisfies condition A; A second condition determination circuit outputs a second determination signal (5a) when the n-bit data satisfies condition B, and (6) outputs a second determination signal (5a) when the first determination signal (4a) is input.
The first one outputs the n-bit data read in in parallel.
The output circuit (7) is a second output circuit that outputs n-bit data read into the input circuit (3) in parallel when the second determination signal (5a) is input.

Next, the operation of the data processing circuit with the above configuration will be explained. ``First, serial data is read into an n-bit input circuit (3) from a data input terminal (2). The first condition determination circuit (4) and the second condition determination circuit (5) are each 11. It is determined whether the read n-bit data satisfies conditions A and B. Now, if the condition is satisfied, the first condition determination circuit (4) outputs the first short signal (4a). (7) Therefore, the first output circuit (6) is set to the input circuit (3) by the input of Jin's first format short signal (4a), and outputs n bits of data in parallel. , if condition B is satisfied, the second condition determination circuit (5) outputs the second judgment short signal (
5a) is output. L7 Therefore, the second output circuit (7
) In response to the input of the pigeon silk 2-size short signal (5a), the n-bit digits set in the input circuit (3) are output in parallel.

However, in conventional data processing circuits, when clock pulses are required for condition determination, (a) a two-phase clock with a phase different from that of the clock pulse used to read data is used, and (b) the rising edge of the clock pulse Since both the rising and falling edges are used, if the condition judgment becomes complicated, the logic circuit size for the condition judgment increases and the delay time also increases.

Furthermore, this has the drawback of limiting the upper limit operating frequency of the data processing circuit.

(7) Therefore, an object of the present invention is to provide a data processing circuit whose upper limit operating frequency is not limited by the operating speed of a logic circuit for determining conditions.

To achieve such an object, the present invention includes an input circuit for reading data, a first delay circuit connected to the output of the input circuit, and at least one delay circuit for determining the content of the data read into the input circuit. a logic circuit, a second delay circuit connected to the output of the logic circuit, and an output circuit for reading and outputting the output data of the first delay circuit using the output pulse of the second delay circuit, The number of delay clocks of one delay circuit is made equal to the sum of the number of delay clocks of the logic circuit and the second delay circuit, and will be explained in detail below using an embodiment.

FIG. 2 is a block diagram showing an embodiment of a data processing circuit according to the present invention. In the figure, (8) indicates a 1-bit first input circuit (8a), an (n, -1)-bit second input circuit (8b), and a 1-bit first delay circuit (8b).
(9) is an (n+1)-bit input circuit consisting of (8c), when n-bit data read into the first input circuit (8a) and the second input circuit (8b) satisfies condition A,
A condition judgment circuit (10) outputs a judgment signal (9a), a D-type flip-flop (10B) and an AND circuit (1
0b), a second delay circuit that synchronizes this judgment signal (9a) with a clock pulse and outputs a synchronized output signal (10e); This is an output circuit in which the n-bit data read into the circuit (8c) is read in by inputting the synchronous output signal (10c).

The number of delay clocks of the first delay circuit (8C) is 1, the number of delay clocks of the condition determination circuit (9) is 0, and the number of delay clocks of the second delay circuit (10) is 1.

Next, the operation of the data processing circuit with the above configuration will be explained. First, n-bit serial data is read into the input circuit (8a) and the second input circuit (8b) of the input circuit (8) through the data input terminal (2). Then, the condition determination circuit (9) determines whether or not the read n-bit data satisfies condition A. If condition A is now satisfied, a determination signal (9a) is output from the condition determination circuit (9).

Then, the second delay circuit (8C) receives the determination signal (9a).
1 clock delay due to input of synchronous output signal Qoa)
AC output. - Buba first input circuit (8a) and second
The n-bit data read into the input circuit (8b) is 1
The signal is read into the second input circuit (8b) and the first delay circuit (8C) by the clock input. Therefore, the output 1 shipping line (11) is connected to the 2nd output by the input of the synchronous output signal (10a).
It is possible to read n-bit data from the input circuit (8b) and the first delay circuit (8C). Therefore, data can be processed without being affected by the delay of the condition determination circuit, that is, without being limited by the upper limit operating frequency.

FIG. 3 is a block diagram showing another embodiment of the data processing circuit according to the present invention. In the figure, (12) is an input terminal into which n-bit parallel data is input, (13) is an input circuit into which this n-bit parallel data is read, and (14) is an input terminal into which n-bit parallel data is input.
) is a first delay circuit that delays this n-bit parallel data by a predetermined number of delay clocks l, and (15) delays this first judgment multiplier (4a) by a predetermined number of delay clocks n, and a second delay circuit that outputs a determination signal (15!L);
(16) is a third delay circuit that delays this second judgment multiple (5 &) by a predetermined number of delay clocks m and outputs a second delay judgment signal (16a), and (17) refers to a first delay judgment signal ( 1
5a), the first delay circuit (14) outputs the read n-bit parallel data in parallel.
The output circuit (1B) is a second output circuit that outputs n-bit parallel data read into the first delay circuit (14) in parallel when the second delay determination signal (16m) is input.

Note that the number of delay clocks of the first condition determination circuit (4) is p,
Letting the number of delayed clocks of the second condition determination circuit (5) be q, it is equal to the sum of the number of delayed clocks of the first delay circuit (14) and the number of delayed clocks n of the second delay circuit (15) (C1=p+n). Similarly, the number of delayed clocks of the first delay circuit (14) is determined by the number of delayed clocks q of the second condition determination circuit (5) and the third
The sum of the number m of delay clocks of the delay circuit (16) (At=q+
m). Regarding the operation, the condition judgment circuit,
Although two delay circuits and two output circuits are provided, it goes without saying that they operate in the same manner as in FIG.

As described in detail above, the data processing circuit according to the present invention has the advantage that it does not depend on the delay of the condition determination circuit, that is, it does not depend on the limitation of the upper limit operating frequency.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional data processing circuit.
, FIG. 2 shows -1 of the data processing circuit according to the present invention.
- Block diagram showing an embodiment. FIG. 3 is a block diagram showing another embodiment of the data processing circuit according to the present invention. (1)...Clock pulse input terminal, (2)...
・Data input terminal, (3)...input circuit, (4)・
...first condition judgment circuit, (5) ...second condition judgment circuit, (6) ...first output circuit, (7) ...second output circuit, (8). ...Input circuit, (8a)...
・First input circuit, (8b)...Second input circuit, (8
c)...First delay circuit, (9)...Condition judgment circuit, (9B)...Judgment signal, (10)...°・°Second
Delay circuit, (10a)...D-type 7 lip-flop,
(10b)...AND circuit, (10C)...Synchronized output signal, (11)...Output circuit, (12)...
...Input terminal, (13)...Input circuit, (14)...
...First delay 1 circuit, (15)...Second delay circuit-
(16)...Third delay circuit, (17)...First
Output circuit, (18)...second output circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1. / Figure 2 Procedural Amendment (Voluntary) 1. Indication of the incident Patent application No. 58-81916 2,
Name of the invention Data processing circuit 3 Person making the amendment Representative Hitoshi Katayama Department 4 Agent 6 Details of the amendment On page 5, line 19, after "condition judgment circuit (9)", "is one clock cycle" A finite delay time less than or equal to the finite delay time is added. that's all

Claims (1)

[Claims] Reads data in synchronization with continuous clock pulses,
A data processing circuit that performs processing according to the content of data, including an input circuit that reads data, a first delay circuit that is connected to the output of the input circuit, and determines the content of the data read into the input circuit. a second delay circuit connected to the output of the logic circuit; and an output circuit that reads and outputs the output data of the first delay circuit using the output pulse of the second delay circuit. Equipped with
A data processing circuit characterized in that the number of delay clocks of the first delay circuit is equal to the sum of the number of delay clocks of the logic circuit and the second delay circuit.