JPS59203289A - アドレス変換バツフア制御方式 - Google Patents

アドレス変換バツフア制御方式

Info

Publication number
JPS59203289A
JPS59203289A JP58076511A JP7651183A JPS59203289A JP S59203289 A JPS59203289 A JP S59203289A JP 58076511 A JP58076511 A JP 58076511A JP 7651183 A JP7651183 A JP 7651183A JP S59203289 A JPS59203289 A JP S59203289A
Authority
JP
Japan
Prior art keywords
address translation
address
translation buffer
virtual memory
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58076511A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6141022B2 (enrdf_load_stackoverflow
Inventor
Masahiro Kuriyama
栗山 正裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58076511A priority Critical patent/JPS59203289A/ja
Publication of JPS59203289A publication Critical patent/JPS59203289A/ja
Publication of JPS6141022B2 publication Critical patent/JPS6141022B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58076511A 1983-04-30 1983-04-30 アドレス変換バツフア制御方式 Granted JPS59203289A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58076511A JPS59203289A (ja) 1983-04-30 1983-04-30 アドレス変換バツフア制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58076511A JPS59203289A (ja) 1983-04-30 1983-04-30 アドレス変換バツフア制御方式

Publications (2)

Publication Number Publication Date
JPS59203289A true JPS59203289A (ja) 1984-11-17
JPS6141022B2 JPS6141022B2 (enrdf_load_stackoverflow) 1986-09-12

Family

ID=13607282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58076511A Granted JPS59203289A (ja) 1983-04-30 1983-04-30 アドレス変換バツフア制御方式

Country Status (1)

Country Link
JP (1) JPS59203289A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0484025U (enrdf_load_stackoverflow) * 1990-11-30 1992-07-22

Also Published As

Publication number Publication date
JPS6141022B2 (enrdf_load_stackoverflow) 1986-09-12

Similar Documents

Publication Publication Date Title
US4495575A (en) Information processing apparatus for virtual storage control system
US3611315A (en) Memory control system for controlling a buffer memory
US8930672B2 (en) Multiprocessor using a shared virtual memory and method of generating a translation table
JPS59203289A (ja) アドレス変換バツフア制御方式
JPH02308349A (ja) バッファ記憶制御装置
US5960456A (en) Method and apparatus for providing a readable and writable cache tag memory
JP3471657B2 (ja) アドレス変換装置および方法
JPH0567001A (ja) キヤツシユメモリ回路
JPH05143445A (ja) 仮想記憶コンピユータのメモリ高速化機構
JP2564377B2 (ja) キャッシュメモリを備えた情報処理装置
JPH04353949A (ja) キャッシュメモリ制御方式
JPS59198586A (ja) アドレス変換バツフア制御方式
JPH041373B2 (enrdf_load_stackoverflow)
JPS5897184A (ja) アドレス変換方式
JPS62197846A (ja) アドレス変換装置
JPH0251755A (ja) キャッシュ・メモリーアクセス用仮想/実アドレス変換装置
JPS60238954A (ja) テ−ブルバツフアのパ−ジ方式
JPS6049449A (ja) アドレス変換バッファ制御方式
JPS6218064B2 (enrdf_load_stackoverflow)
JPH04232550A (ja) 一致処理制御装置
JPS6148049A (ja) メモリ・アクセスのチエツク装置
JPH0573424A (ja) 高速アドレス変換方式
JPS61246853A (ja) 仮想記憶方式の計算機システムにおけるチエンジ・ビツトの更新制御方式
JPS62242254A (ja) デ−タ処理装置
JPH0210448A (ja) キャッシュメモリシステム