JPS59202543A - Os firmware system - Google Patents

Abstract

PURPOSE:To speed up the OS firmware by providing a copy of an OS control table on a main memory in a high speed memory exclusively used for a microprogram. CONSTITUTION:The information of the OS control table 14 on a main memory MM1 modified dynamically and required for the processing of an FI1 is copied to an OS control table 23 of a high speed memory LM2 exclusively used for microprogram by a processing block 311. Then, the control table having a list structure is checked one by one case by a processing block 312, and when the OS control table satisfying a specified condition exists, this table is cleared. Further an interruption control circuit 53 is checked by the processing block 313 so as to check the presence of the interruption request. When the interruption request exists, the information required for the interruption of the processing of the FI1 is saved by a processing block 317 and the information required for the restart of the interruption microprogram is extracted from the OS control table 21 on the LM2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a high-speed, large-scale microprogram system in a microprogram system electronic computer, and particularly to an O
Regarding the 8th firmware conversion method.

[Background of the invention]

In the conventional microprogram method, even if an interrupt factor occurs during the execution of a microprogram that processes an arbitrary machine instruction, the interrupt has to wait until the microprogram processing related to the machine instruction is completed. In order to interrupt and restart the microprogram processing, there is a lot of information that must be temporarily saved, and this information must be saved in the main memory, which requires more access time than the microinstruction processing time. This was due to an unexpected situation. Furthermore, in cases where a series of processing ends in several microsteps or tens of microsteps, such as in the case of conventional microprograms that process machine instructions, the time that the interrupt has to wait can be tolerated. .

However, when trying to implement highly functional and complex machine language instructions or OS firmware that implements O8 functions with microprograms, it would take more than 100 microsteps, and the interrupts described above would not be possible. The amount of time they have to wait far exceeds their tolerance. This becomes an unavoidable problem, especially in systems that require real-time responsiveness. For this reason, the above-mentioned functions had to be divided into smaller functions and created by dividing them into a plurality of machine instructions, making it impossible to achieve the desired high-speed performance.

On the other hand, when attempting to implement OS firmware, the main function of the O8 is to process the O8 control table on the main memory, so information is frequently exchanged with the main memory. For this reason, the effect of OS firmware implementation is limited by the access time of the main memory, and the effect may not be as great as expected.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to improve the access frequency of main memory in microprogram processing in order to solve the above-mentioned problems.
Another object of the present invention is to provide an OS firmware system that reduces access time, enables interrupt processing during microprogram execution, and thereby enables high-speed, large-scale microprogram processing.

[Summary of the invention]

In order to achieve the above object, the present invention is characterized in that a high-speed memory dedicated to the microprogram is installed, a copy of the O8 control table on the main memory is stored in the memory, and the memory is used during the execution of the microprogram in the OS firmware. By using the copy information of the O8 control table above,
The aim is to process S firmware at high speed. Furthermore, if there is an interrupt processing request during execution of the OS firmware, the present invention saves information necessary for resuming the processing after interruption to the memory, moves to execution of the interrupt processing, and executes the interrupt processing. After execution, in order to resume execution of the OS firmware, necessary information is retrieved from the dedicated high-speed memory, and execution is quickly resumed from the point where the OS firmware was interrupted.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows the configuration of a processing device for an electronic computer according to the present invention. The processing device includes a main memory (MM) 1 and a high-speed memory (LM) 2 dedicated to microprograms according to the present invention.
, control memory (CM) 3, and arithmetic control unit (PU)
Consists of 4.

The MMI has an OS program15 written in machine instructions.
-17 and O8 control tables 11-14, user programs, user data, etc. are stored. LM2 has a copy of the O8 control table 21.23. A microprogram work area 22, an information saving area 24 during interrupt processing, and the like are arranged. 0M3 stores microprograms corresponding to various machine instructions, a microprogram 31 corresponding to OS firmware instructions related to the present invention, and the like. PU4 is a processing unit consisting of an interface control circuit with MMl, various registers, an arithmetic circuit, a control circuit of LM2, a control circuit of 0M3, etc. The execution of machine instructions that realize the functions of each program is generally as follows. It is processed as follows.

First, the storage address on the MMI of the machine instruction to be executed is set in the program counter (PC) 47, and by setting the contents in the MM address register (MAR) 46 and issuing a read request to the MMI, The machine command is read out via the MM read data signal line 56;
Instruction buffer register (stored in IB151. IB
The machine instructions stored in R51 are decoded by decoder 50.

Based on the decoding result of the decoder 50, a CM address in which a microprogram corresponding to the machine instruction is stored is generated and passed to 0M3 via the CM address signal line 62.

0M3 reads a microinstruction from the CM address indicated by the signal line 62 and sends the microinstruction to the signal line 63.
is set in the microinstruction register (MIR) 52 via the .

The PU 4 operates various control signals 66 and the like in accordance with the microinstructions set in the MIR 52 to execute various calculations and controls. For example, arithmetic processing is performed using general-purpose registers (
GR,)42. Work register file (WK) 43.
The MMI information read out to the signal line 56 and the MI
Among the values on the signal line 65 that are directly given by the microinstruction stored in R52, the three specified by the microinstruction are selected, and the arithmetic unit (ALU) 44 is used to apply the values to the microinstruction. 2 performs the specified operation and puts the result on the data bus 61. The information carried on the data bus 61 is GR42, WK43°MMl, or LM2.
etc., and stored.

Information can be written to the MMI by setting the MM address of the write area in the MAR 46, setting the information to be written in the M, M write data register (MWR) 45, and issuing a write request to the MMI. be exposed.

Further, writing and reading information to LM2 is performed as follows. Set the LM address of the write or read area in the LM address register (RAR) 41,
By issuing a write or read request to LM2, an operation of writing information such as WK43 to LM2 or reading information of LM2 to WK43 etc. is performed.

By the way, the CM address when reading the microinstruction to be executed next after the execution of a certain microinstruction is finished is given by the following method. Generally, the adder 48 generates a CM address that is the storage address of the microinstruction currently being executed plus one, and sends it to the signal line 62. Also, when branching a microprogram,
The CM address directly specified by the microinstruction is signal line 63.
Sent via . At this time, the return address from the branch light which is increased by 1 to the storage address of the microinstruction currently being executed is stored in the return 0M address stack (STACK) 49. Then, when a return υ from the branch destination is specified by 2 in the microinstruction, the return CM address is extracted from the 5TACK 49 and sent to the signal line 62.

When a series of microprogram processing is completed by fetching and executing a microinstruction according to the CM address obtained as described above, the last microinstruction instructs the fetching and execution of the next machine instruction. The MM address for fetching the next machine instruction is determined during the previous microprogram processing and is set in the PC 47. This PC47
The method for extracting the next machine command to be executed using the value of is as described above.

Here, before executing the next machine instruction, the presence or absence of an interrupt request is normally checked, and if there is an interrupt request, the interrupt acceptance process is executed immediately, and if not, the execution of the next machine instruction is started as described above. Start like this.

Interrupt requests are sent to the interrupt control circuit 5 by various interrupt signals 68.
3, and whether there is an interrupt request or not is stored there. When moving to execution of the next machine instruction, the presence or absence of an interrupt request stored in this interrupt control circuit 53 is checked, and if there is an interrupt request, it is generated by the circuit and sent to the signal line 64. Control is transferred to the interrupt reception microprogram using the CM address. Since the function of this interrupt acceptance microprogram is not important in this embodiment, its explanation will be omitted.

FIG. 2 shows means for enabling interrupt processing during execution of the O87 arm ra air in the above-mentioned processing apparatus.

Program 15 shows an example of an OS program, program 16 shows an interrupt processing program, and program 17 shows an example of an OS program.
indicates the LM initialization program, and these are all MMI
Microprogram 31 also represents an example of OS firmware instructions, which are stored within CMa. Here, the OS firmware command is a microprogram that implements the functions of the O8, and is retrieved from the main memory and processed in the same way as conventional machine commands.

In this embodiment, an OS firmware instruction FIL that performs a function of searching an O8 control table having a list structure and clearing an O8 control table that satisfies a specific condition will be explained as an example. This OS firmware instruction FIL
Because it searches and processes many O8 control tables, it is expected that the execution time will be long. It also has an FI2 interface.

The procedure for processing the OS firmware instruction F1 will be described below.

First, the LM initialization program 17 is processed as part of the bootstrap program executed when initially starting up the computer. This LM initialization program 17 executes p, o by executing machine instructions 171 to 172.
sThe contents of the OS IIJ control table 12 on the MMI, which consists of constants used when executing firmware instructions, are
O8 city 1 on M2] Copy to table 21. This copied 08 control table 21 contains the MM storage address RT of the OS firmware instruction FI2 for restarting the interrupted microprogram in the OS program 15.
N information 211 is included.

Now, suppose that the processing of the OS program 15 is started after the above-mentioned initialization. After executing the machine instructions 151 in the OS program 15, as described in the explanation of FIG.
The firmware instruction FIL 152 is taken out, and the processing of the corresponding microprogram 31 is started.

The microprogram 31 that executes the OS firmware instruction FIL is processed as follows.

It is assumed that the processing blocks in the description are executed by a plurality of microinstructions.

First, in processing block 311, information in the O8 control table 14 on the MMI, which is necessary for Fll processing and is dynamically changed, is copied to the O8 control table 23 on the LM2. Thereafter, in processing block 312, the control table having a list structure is checked case by case, and if there is an O8 control table that satisfies a specific condition, the table is cleared. Then, in processing block 313, the presence or absence of an interrupt request is determined by checking the interrupt control circuit 53 shown in FIG. If there is no interrupt request, processing continues at processing block 314 where it is determined whether the entire list of O8 control tables has been processed and, if any, the list of O8 control tables is processed in order to process the next O8 control table. , the process moves to processing block 312 . When all the lists have been processed, in processing block 315, the information 23 that has been rewritten in the information in the O8 control table 23 of LM2
1,232 is rewritten to the corresponding location in the OS control table 14 on the MMI, and finally the next machine command is fetched and executed. As a result, machine instructions 153 of the OS program will be executed next.

By the way, when it is detected in processing block 313 that there is an interrupt request, processing block 317 detects that there is an interrupt request.
The information necessary for interrupting the processing, such as the start address of the list of processing targets, the address of the O8 control table that has been processed up to that point, and the information of the WK 43 is saved in the information save area 24 on the LMZ. Then, in processing block 318, the MM address information 211 storing the firmware instruction FI2 for restarting the interrupted microprogram is extracted from the O8 control table 21 on the LMz, and the MM address information 211 is transferred to the PC.
47, and then proceeds to fetch and execute the next machine command.

As a result, an attempt is made to retrieve the FI2 instruction 154 of the MM address RTN based on the MM address information newly set in the PC 47, but as described in the explanation of FIG.
Before fetching and executing the next machine instruction, the presence or absence of an interrupt request is checked.

In this case, since there is an interrupt request, control is transferred to the interrupt reception microprogram mentioned earlier, and the necessary information there, such as information on the PC47 and GR42, is transferred to the L M
After saving to the information saving area 24 on Z, execution of the interrupt processing program 16 is started.

The interrupt processing program 16 performs its processing by executing machine instructions 161 to 162, but the last machine instruction LDPSW 162 executes the GR 42 and P'C that have been saved in the information save area 24 by the interrupt acceptance microprogram.
Recover information such as 47.

This reproduces the situation when the FI2 instruction 154 at the MM address RTN is attempted to be executed. As a result, the FI2 instruction 154 is then fetched,
The FI2 instruction microprogram is executed.

The microprogram for the FI'2 instruction is processing block 3.
In step 16, the information in the information save area 24 saved in the above-mentioned FIL instruction processing block 317 is restored, and then the process branches to the F11 instruction processing block 314. This makes it possible to reproduce the situation when the FIL instruction was interrupted and continue processing the subsequent FIL instruction.

After completing the execution of processing block 315, the next machine instruction 155 is retrieved and executed. Here, the machine instruction 155 is a branch instruction to the machine instruction 153, and in order to execute this instruction, the machine instruction 153 is retrieved and executed. Because of this, 9. This means that the same processing as if no interrupt processing was performed during execution of the FIL instruction.

As explained above, according to this embodiment, while the OS firmware command is being executed, the necessary information is transferred to LM2. GR42,
Information in WK43 can be used, and faster processing is possible than in the case of using information in MMl.

Furthermore, according to this embodiment, interrupt processing is possible even during the execution of OS firmware instructions, and there is an effect that large-scale OS firmware can be realized.

Further, other embodiments of the present invention are shown in FIGS. 3, 4, and 5.
This will be explained with the help of a diagram.

FIG. 3 shows the processing configuration of the electronic computer according to the present invention. The difference from the configuration shown in FIG. 1 is that 0M address information is placed on the data bus 61 and G11'L42. W
K43. A signal line 70 was provided to enable storing the address information in LM2 and MMI, and GR, WK.

The address information extracted from LM and MM is set to 0M.
The reason is that the signal line 71 is provided in order to enable the signal to be supplied to the signal line 3. The operation of the 0M address using these signal lines is performed under the control of the microprogram as described in the explanation of FIG.

4 and 5 show that in the processing apparatus of FIG.
A microprogram 31, which may indicate means for enabling interrupt processing during execution of S firmware, indicates FIX, which is an example of an OS firmware instruction, and a microprogram 32 indicates a means for enabling interrupt processing during execution of the OS firmware.
Interrupt reception, which accepts interrupts during firmware execution, indicates microprogram INTM, and microprogram 3
3 indicates the return machine command LDP8W.

Let us now consider a situation in which the OS program 15 is being processed, the OS firmware instruction F11152 has been extracted, and the corresponding microprogram 31 has started processing.

Processing block 311 of OS firmware instruction FIL.
312, 313, 314. The functions performed by 315 and 315 are as shown in the explanation of FIG.

If it is detected in processing block 313 that there is an interrupt request, the following processing is performed.

In processing block 317, information necessary for interrupting FIl processing is saved to the information save area 24 on the LMZ. Then, in processing block 318, the interrupt reception regarding the interrupt during execution of the microprogram is performed by the microprogram INTM.
At the same time as 32 hejyump, return 0M address information,
In this case, the address of processing block 319 is 5TAC
Store in K49.

In INTM32, in processing block 321, 5TAC
The returned CM address information in K49 is saved to area 242 of information save area 24 on LMZ. Then, in processing block 322, a flag indicating that the save information in area 242 is valid is set in area 241 of the save area 24, and then an interrupt is generated immediately before the execution of the machine instruction described in the explanation of FIG. Processing of the microprogram processing block 323 that accepts the data is performed.

In processing block 323, after saving information on the PC 47, GR 42, etc. to the saving area 24, execution of the interrupt processing program 16 is started. PO27 evacuated at this time
The contents of MM of machine instruction 153 of OS program 15
Indicates M delivery address.

Last machine instruction LDPSW of interrupt processing program 16
162 is processed by the corresponding microprogram 33. In the processing block 331 of the microprogram 33, information on the GR 42, PC 47, etc. that has been saved in the information save area 24 is recovered. Next, in processing block 332, area 241 of the information save area 24 is checked to determine whether the information in area 242 is valid or not, that is, whether an interruption occurred during execution of the microprogram. If the 7 lag in area 241 indicates invalid, the next instruction is extracted from the MM address pointed to by the recovered PC 47 in processing block 333.

If processing block 332 detects that the flag in area 241 is valid, processing block 33
In the block that jumps to 4, the CM return address saved in area 242 is restored to 5TACK 49. Next, in a processing block 335, the flag of the area 241 is reset, and in a processing block 336, the sT8 to 49, 9CM return address is extracted and a jump is made to the address.

As a result, control of the microprogram is returned to the microprogram processing block 319 of the OS firmware FIZ that was interrupted by the previous interrupt.

In the processing block 319, the information in the area 24 saved in the previously described processing block 317 is restored, and the process branches to the processing block 314. This makes it possible to reproduce the situation when the FIL instruction was interrupted and continue processing the subsequent FIL instruction.

After execution of processing block 315, the next machine instruction 1
53 is taken out and executed.

As described above, according to this embodiment, the same effects as the first embodiment can be achieved without providing any special procedures to the OS program that uses OS firmware instructions.

Furthermore, another embodiment of the present invention will be explained with reference to FIG.

FIG. 6 shows the O
3 shows part of another means for enabling interrupt processing during execution of S firmware.

A microprogram 31 indicates FIL, which is an example of an OS firmware instruction, and a microprogram 32 indicates an OS firmware instruction.
The microprogram 33 indicates the return machine command LDPSW, and the area 212 in the O8 control table 21 on LM2 indicates the MM to be saved when interrupting the execution of the OS firmware. Indicates an area for storing information or addresses of LM information.

It is now assumed that an interrupt request is detected in processing block 313 while the microprogram 31 of the OS firmware instruction FIL is being executed.

If an interrupt request is detected, in processing block 300, a jump is made to the interrupt acceptance microprogram INTM32 with identification information that it is a branch from the F engineering 1 instruction, and at the same time, the CM return comb address information is The address of the processing block 301 is stored in 8TACK49.

In INTM32, first, in processing block 305, using the identification information passed from the microprogram of the interrupted OS firmware, information necessary at the time of interruption of the OS firmware is obtained from the information indicated by the factory 212 of LM2. Then, in processing block 306, the information on the corresponding MM or LM is saved to the information save area 24 of LM2.

Next, in processing blocks 321, 322, and 323, processing similar to that described in the second embodiment is performed, and as a result, necessary information is saved and execution of the interrupt program 16 is started.

Last machine instruction LDPSW of interrupt processing program 16
The microprogram 33 that executes 162 performs the following processing, and processing blocks 331 to 335 perform the same processing as described in the second embodiment.

After processing block 335 is executed, processing block 33 is executed.
At step 7, the information to be recovered is determined from the information indicated in the area 212 of LM2, and further, at processing block 338, the corresponding MM or LM information is recovered from the information save area 24 of LM2.

Then, in processing block 336, the 5TACK 49 returns the CM address, and jumps to the corresponding CM child address.

As a result, the control of the microprogram is controlled by the processing block 3 of the OS firmware FIL that was interrupted by the interrupt.
It is returned to 01.

Processing block 301 immediately branches to processing block 314 to continue processing subsequent FIL instructions.

As explained below, according to this embodiment, the first embodiment or the second embodiment can be implemented without providing special procedures in either the OS program that uses OS firmware instructions or the microprogram that implements the OS firmware instructions. Effects similar to those of the embodiment can be obtained.

〔Effect of the invention〕

According to the present invention, by providing a high-speed memory dedicated to the microprogram, it is possible to reduce the frequency of main memory references during the execution of the microprogram, resulting in the effect of speeding up the microprogram. In addition, by providing a high-speed memory dedicated to microprograms and using it to process interrupt requests while the microprogram is running, it is possible to eliminate the need to wait for a response to an interrupt request, making it possible to microprogram, such as an OS
This has the effect of making it possible to implement firmware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a processing device according to the present invention, FIG. 2 is a diagram showing the structure of a microprogram system that enables interrupts according to the present invention, and FIG. 3 is a diagram of another processing device according to the present invention. The configuration diagrams, FIGS. 4 and 5 are diagrams showing another structure of the microprogram system that enables interrupts according to the present invention, and FIG. 6 shows the structure of the microprogram system that enables interrupts according to the present invention. It is a figure which shows yet another structure. DESCRIPTION OF SYMBOLS 1...Main memory, 2...High-speed memory dedicated to microprogram, 3...Control memory, 4...Arithmetic control mechanism, 31...Microprogram for executing OS firmware, 32...OS firmware Microprogram that accepts interrupts during execution, 33...Return 1
Figure 2 Figure 31211 4th (2) Figure 5 Closed Figure 6

Claims (1)

[Scope of Claims] 1. In a microprogram type electronic computer comprising an arithmetic control mechanism having a main memory, a control memory, and an interrupt detection circuit, the method is mainly used for executing a microprogram stored in the control memory, An OS firmware system characterized by the provision of a high-speed memory dedicated to microprograms that can be read and written at higher speeds than main memory. 2. In the method of claim 10, means for writing information in main memory necessary for executing a microprogram into a high-speed memory dedicated to the microprogram, and means for determining whether or not an interrupt occurs during execution of the microprogram; means for saving all information necessary for interrupting and resuming processing in the high-speed memory dedicated to the micro program when an interrupt occurs; and means for resuming the interrupted processing of the micro program after processing the interrupt; A micro program having means for recovering information necessary for restarting from a high speed memory dedicated to the micro program, and means for writing main memory related information on the dedicated high speed memory that had to be rewritten during execution of the micro program to the main memory again.・The 087 firmware system is characterized by the provision of a program. 3. In the method of Scope 2, a means is provided for copying a part of the information in the main memory to the micro program dedicated high speed memory and initializing the dedicated high speed memory when the electronic computer is initialized. The 087 firmware system is characterized by: