JPS5846444A - Register group storage device - Google Patents

Abstract

PURPOSE:To shorten the switching processing time of a process and to obtain a high-speed system, by performing the stand-by processing of a register in parallel to the execution of instruction after the switching processing of the process. CONSTITUTION:A stand-by address register 637 is set by the output of an AND circuit 636. Every time a machine clock is supplied, +1 addition is performed through a +1 circuit 638. Namely, read data 78 which corresponds to a process before execution in the 2nd register stack 62 is outputted. The output of the AND circuit 636, on the other hand, is passed through an OR circuit 640 to obtain a set signal to a memory address register 642. The stand-by area starting address set in the register 642 is increased by four at every time by a +4 circuit 643 and outptted as a main storage address 79. Therefore, the contents which correspond to the procees before execution stored in the 2nd register stack 62 are enqueued in a corresponding stand-by area in a main storage device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a group of registers used for calculations in a central processing unit of a computer system is defined for each process, which is a processing unit of a program, and is stored in a main memory for each process. It is possible to save and store in the l/register save area provided corresponding to 5. In particular, the present invention relates to a register group storage device that stores a register group corresponding to a running process in a computer system that executes one process at a time among a plurality of processes in an executable state.
The present invention relates to saving from a register group storage device to a main memory device at the time of process switching and recovery (writing) control from the main memory device to the register group storage device.

Conventionally, this type of system has been configured as shown in FIG. That is, one main memory stores instructions, operands, and save data for each content of a plurality of register groups. The contents of the above set of registers correspond to one process. The central processing unit 2 includes an instruction fetch device 3, an instruction execution device 4, a register group storage device 5, and the like. The register group storage device 5 is composed of a register stack 51 that stores a set of register groups corresponding to a process that is being executed, and an address register 52 that supplies an address for continuation and writing of the register stack 51. ing. The register stack 51d1 has 16 base registers (BRO to BRI5) that hold the base address of the normal main memory address.
and 16 general-purpose registers (GRO~
QR15).

The instruction fetch device shifts M3 instructions from the main memory 1, decodes them, and prepares memory operands and register operands. Preparation of the memory operand means reading the contents of the pace register and general-purpose register specified by the instruction from the register stack 51 via the address register 52, and storing three pieces of data: these contents and the contents of the displacement field in the instruction. The main memory address is determined by calculation, and a load access request to main memory #1 is generated. Furthermore, preparing a register operand means reading the contents of a general-purpose register specified by an instruction from the register stack 51 via the address register 52, and receiving this read data by the instruction execution device 4.

The operation result in the instruction execution device 4 is stored in the address position of the register stack 51 given from the instruction fetch device 3 via the address register 52.

In the instruction fetch device 3, if it is necessary to switch the process due to an interrupt from another processor such as an input/output control device, an interrupt due to exception detection during instruction execution, or instruction decoding, etc., the process is first executed. The contents of the register stack 51, which is a register group corresponding to the process that was inside, are saved to an area predetermined for each process in the main memory 1, and then the contents of the register stack 51, which is a register group corresponding to the process to be newly executed, are saved. It is necessary to move (that is, restore) the contents from the corresponding save area in the main memory 1 to the register stack 51. The operation of saving and restoring this register group will be explained with reference to the time chart shown in FIG. First, the contents of 16 pace registers (BRO to Bl'L15) and 16 general-purpose registers (GRO to GR15) of the register stack 51, a total of 32 registers, are sequentially written and saved in the main storage device 1. Next, 32 registers (BRO to BRI5, GRO to qR15) of the register stack 51 from the main memory 1
The main memory storage area corresponding to the new process is sequentially read and recovered. In other words, for backup processing and recovery processing, 32 writes to the main memory and 32
This requires multiple read operations from the main memory. That is, the conventional register group storage device 5 as shown in FIG.
A computer system using the ``process'' has the disadvantage that it takes a lot of time to switch processes. The time required for this process switching is 1
This requires approximately 0 to 100 times the processing time, which causes a significant deterioration in system performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a register group storage device that solves the above-mentioned conventional drawbacks and can substantially reduce the time required to save registers (contents) when switching processes. It is in.

The storage device of the present invention incorporates an instruction storage device, an instruction execution device, and a register group storage device, and fetches and decodes instructions from the main memory, executes instructions, decodes and assigns instructions. It performs switching processing between processes that are started up, and the contents of a set of registers used for calculations for each process, which is a processing unit of a program, are set corresponding to each process in the main memory. reading from the register save area and storing it in the register group storage device, and saving the contents of a set of register groups for the previously executing process stored in the register group storage device in the corresponding register of the main storage device; In a register group storage device of a central processing unit that executes one process at a time among a plurality of processes in an executable state by saving the process to an area, a set of the register groups corresponding to the currently executing process is provided. A first register stack that stores the contents of the program, and two areas that can store the contents of a set of registers corresponding to the program being executed and the contents of a register group that was previously being executed. A second register stack having a second register stack, address information for successive writing to these first and second register stacks, save destination area start address information 9, a recovery start instruction signal, etc. are received from the instruction fetch device and these are processed. and a register group control circuit for controlling operations, wherein register operands used for instruction execution are read from the first register stack to the instruction execution device according to register address information given from the instruction fetch device. , the operation results are simultaneously stored in corresponding positions in one area of the first register stack and the second register stack according to the I-saving register address information given from the instruction fetch device, and the process switching is performed from the instruction fetch device. When a recovery start instruction signal for processing is given, the contents of a corresponding set of register groups read from the corresponding save area of the main memory are different from those of the first register stack and the second register stack. At the same time, in response to a process switching end signal given from the instruction fetch device, one area corresponding to the previously executing process in the second register stack is stored in another area in parallel with the execution of the instruction for the new process. The present invention is characterized in that the contents of a set of registers stored in one area are sequentially sent out and saved to the corresponding save area of the main storage device.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

That is, the register group storage device 6 of this embodiment includes a first register stack 61 having 32 registers;
It consists of a second register stack 62 having four registers, and a register group control circuit 63 that controls the saving and restoring of the contents of these registers. The first register stack 61 has 16 base registers and 16 general-purpose registers that store the contents of a set of registers corresponding to the running process, and stores 32 words x 4 bytes of data. Can be stored.

In addition, the second register stack 6211, 64' can store data of 7-de x 4 bytes, and includes one set of registers corresponding to the above-mentioned executing process and one set of registers corresponding to the immediately previous executing process. It has two areas for storing the contents of the set of registers. The register group control circuit 63 is configured to perform these register statuses in parallel with the instruction execution after the process switching process (recovery of registers) is completed, so that the time required for the process switching process is significantly shortened. It is possible to speed up system performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a computer system using a conventional register group storage device, FIG. 2 is a time chart showing register saving and restoring operations in the conventional system, and FIG. 3 is a block diagram showing an example of a computer system using a conventional register group storage device. A block diagram showing an embodiment,
FIG. 4 is a detailed block diagram showing the register group storage device of the above embodiment, and FIG. 5 is a time chart showing the register recovery and saving operations of the computing system using all of the above embodiments. In the figure, 1... Main memory device, 2... Central processing unit, 3... Instruction fetch device, 4... Instruction execution device, 5.6... Register group storage device, 51... Register stack, 52...Address register, 61...
First register stutter, 62... Second register stack, 63... Register group control circuit, 631...
Address register, 632.634.641... Selection circuit, 633... Area specification register, 635...
Register write register, 637... Save address register, 639... ALL'"1" detection circuit, 642
. . . Memory address register, 644 . . . Save display register. Agent Patent Attorney Sumi 1) Shun Youngest brother 1 Figure 2 Figure 2 Figure 3 Time Figure 3 Group of registers corresponding to the previously executing process, that is, contents stored in one area of the second register stack 62 is saved to the main storage device 1 (see times 1 to 2 in FIG. 5). In other words, the save display register 644
By supplying the output logic "'1" of The outputs are selected and supplied as read addresses of the upper 1 bit and lower 5 bits to the second register stack 62, respectively. The save address register 637 is set by the output of the AND circuit 636, and is incremented by 1 by a +1 circuit 638 every time the machine clock is supplied. That is, data is sequentially read from one area of the second register stack 62 corresponding to the previously executed process, and read data 78 is output. On the other hand, the output of the AND circuit 636 is sent to the memory address register 6420 as a set signal via the OR circuit 640, and the first address of the save area set in the memory address register 6420 is added by 4 in the +4 circuit 643 for each machine clock to be added to the main memory. It is output as address 79. Therefore, the content i corresponding to the previously executed process, which was saved in the second register stack 62, is saved and stored in the corresponding save area in the main storage device 1. However, during the above-mentioned save operation, if it becomes necessary to write the register due to the execution of an instruction, the instruction fetch device 3
The register write signal 75 is sent to the register write register 6 from
35. The register write register 635 is
This is a flip-flop whose input signal 75 is set every machine clock, and when it is set by the write signal 75, its negative output causes one input of the AND circuit 6360 to become @0'', so the output of the AND circuit 636 The logic is 'θ'', and the selection circuits 632 and 634
selects the address information 631 and the positive output of the area designation register 633, respectively, and uses them as the write address of the second register stack 62. Therefore, data from the instruction execution device 4 is written to the first register stack 61 and the second register stack 62. During this time, the memory address register 642 and the save address register 6370 set inputs are at ``θ'' due to the output logic ``''ON of the AND circuit 636, so the save operation is temporarily interrupted. Note that during the save process, the output of the save display register 644 is sent to the instruction fetch device 3 as the save display signal 77, so even if the instruction fetch device 3 detects the next process switching instruction during this period, make you wait for execution,
Process switching is performed after the evacuation is completed. When the save process progresses and all 5-bit outputs of the save address register 637 become 11'', this is detected by the ALL61'' detection circuit 639 consisting of a 5-man AND circuit, and the save display register 644 and the save address register 637 are The contents of these registers are reset and all contents of these registers become "+".In other words, after the save processing is completed at time ■ shown in FIG. As can be understood from the above explanation, in this embodiment, the register saving process at the time of process switching process is performed in 32 steps.
Since the 1-input operation to the main memory is performed in parallel with the execution of the instruction, the extra time required for saving the register becomes zero, which has the effect of speeding up the switching process. Although the above embodiment has been described in the case where the second register stack 62 cannot be read and written simultaneously, for example, if a register file element is used, the read address and the write address can be supplied independently. , it is possible to perform both indulgence and honor at the same time. In this case, there is no need to temporarily interrupt the register saving process by the register write instruction signal 75 shown in FIG. 4, and the register saving process can be made completely independent of instruction execution. As described above, in the present invention, register saving processing is not performed during process switching processing, but is performed in parallel with instruction execution after the process switching processing (register recovery) is completed. Therefore, the time required for process switching can be significantly shortened, and system performance can be increased. 4. Brief description of the drawings FIG. 1 is a block diagram showing a computer system using a conventional register group storage device, and FIG. 2 is a time chart showing register save and restore operations in the conventional system. , FIG. 3 is a block diagram showing one embodiment of the present invention, FIG. 4 is a detailed block diagram showing the register group storage device of the above embodiment, and FIG. 5 is a register recovery of a computing system using all of the above embodiments. , is a time chart showing the evacuation operation. In the figure, 1... Main storage device, 2... Central processing unit, 3... Instruction fetch device, 4... Instruction execution device, 5.6... - Register group storage device, 51... register stack, 52... address register, 61...
First register stack, 62... Second register stack, 63... Register group control circuit, 631...
Address register, 632.634.641... Selection circuit, 633... Area specification register, 635...
Register write register, 637... Save address register, 639... A L L "1" detection circuit,
642... Memory address register, 644... Save display register. Agent Patent Attorney Sumi 1) Shun Youngest brother 1 Figure 2 - GLT addition) Figure 3

Claims (1)

[Claims] It has a built-in instruction retrieval device, an instruction execution device, and a register group storage device, and is capable of retrieving instructions from the main memory.
The main memory stores the contents of a set of registers used for calculations for each process, which is the processing unit of the program, and executes instructions and switches the processes activated (by decoding instructions or interrupts). A set of register groups is read from a register save area provided corresponding to each process of the device and stored in the register group storage device, and is stored in the register group storage device for a previously executing process. In the register group storage device of a central processing unit that executes one process at a time among a plurality of processes in an executable state, the contents are saved to the corresponding register save area of the main storage device. a first register stack for storing the contents of a set of registers corresponding to the process; and a first register stack storing the contents of a set of registers corresponding to the program being executed and a set of registers previously being executed. a second register stack having two areas in which the contents of the group can be stored;
and a register group control circuit that receives address information for reading and writing to the second register stack, save destination area start address information 9, a recovery start instruction signal, etc. from the instruction fetch device f, and controls these operations. hand,
Register operands used to execute an instruction are read from the first register stack to the instruction execution device according to register address information given from the instruction fetch device, and operation results are read out from the instruction execution device by register address information given from the instruction fetch device. ) are simultaneously stored in corresponding positions in one area of the first register stack and the second register stack, and when a recovery start instruction signal for process switching processing is given from the instruction fetch device, the main memory The contents of a corresponding set of register groups read from the corresponding save area of the device are simultaneously stored in another area different from the above of the first register stack and the second register stack, and the contents are provided from the instruction fetch device. In response to a process switching end signal, the contents of a set of registers stored in one area of the second register stack corresponding to the previously executing process are sequentially executed in parallel with the execution of instructions for the new process. A register group storage device, characterized in that the register group storage device is configured to send the registers and save them to a corresponding save area of the main storage device.