JPS5920199B2 - Memory check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory check method that can reduce the amount of hardware required for memory check and can always guarantee the contents of memory.

FIG. 1 shows a conventional memory check system, in which 1 indicates a program ROM, 2 a parity ROM, and 3 a parity check circuit.

Parity R0M2 stores a plurality of parity bits each corresponding to each byte or word of program ROMI. When an address is supplied to the program ROM and data is read from the program ROMI, a parity register corresponding to the read data is simultaneously supplied.
Bits are also read. The read data and parity bits are input to the parity check circuit 3, and the parity bits generated by the read data are compared with the parity bits read from the parity R0M2. If they do not match, the processor is notified that a memory error has occurred. A disadvantage of the conventional memory checking scheme as shown in FIG. 1 is that it requires a relatively large parity ROM 2, with one parity bit for each byte or word.
Ru. Therefore, if the memory check method as shown in FIG. 1 is adopted, the product cost will increase. FIG. 2 shows a conventional memory check method that eliminates the drawbacks of the memory check method shown in FIG. 1, and 4 indicates a ROM. The program and check code are written in ROM4. The check code is, for example, a vertical parity bit for the program. That is, the first bit of the check code is the EOR of the first bit of each address in the program area. The opening in FIG. 2 shows memory check processing. A program consisting of an operation program and a memory check program is written in the ROM 4. A memory check is performed as follows. That is, when power is turned on, all data in the program area is read and vertical parity bits are generated. Then, this generated vertical parity bit is compared with the check code written in advance, and the comparison result is 0.
If it is K, the operation program is executed. If NG, the processor is notified of the occurrence of a memory error.
The disadvantage of the conventional memory check method shown in FIG. 2 is that the memory check is performed only when the power is turned on.
The problem is that subsequent memory errors cannot be detected. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory check method which eliminates the above-mentioned drawbacks and has features such as being able to reduce the amount of hardware and always guaranteeing the contents of the memory. Therefore, the memory check method of the present invention includes a memory Z having a data area including an operating program and a check code storage area in which a check code generated in advance for the entire data of the data area is stored; In a system equipped with a check data designation counter and a generated check code storage means, the above operation program is executed n times (however, n
is a natural number) Each time the check is executed, the data specified by the check data specification counter is sent to the above method. "Read from the data area of the memory, calculate the read data and the check code of the generated check code storage means to generate a new check code, and store the newly generated check code in the generated check code."・Store again in the code storage means. Together with j, the count value of the check data designation counter is increased by a unit amount, and when the count value of the check data designation counter reaches a predetermined value, the check code storage area is checked.・Compare the code with the check code of the generated check code storage means,
If the two match, the generated check code storage means is cleared, and the check data designation counter is reset to its initial value, and the operation program is executed. If the two do not match, memory error processing is performed. This is a characteristic feature. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 3 is a diagram showing an embodiment of the memory check of the present invention, and FIG. 4 is a diagram showing an example of a computer system.

In FIG. 4, numeral 5 represents a ROM 16, a CPU 17 represents a control circuit, 8 represents an arithmetic circuit, 9 represents a program counter, and 10 represents a working RAM 11 a counter.

The computer system shown in FIG. 4 is built into, for example, a terminal device. An operating program, a memory check program, and a check code are written in the ROM 5. The first bit of the check code is, for example, the result of EORing the first bits of the data from address 0 to address n. Of course, other check codes, such as CRCl group counting, can also be used. The memory check program is provided in the path that the operational program passes under any circumstances. In the illustrated example, a memory check program is provided at the end of the operational program. Next, the memory check method of the present invention will be explained with reference to FIGS. 3 and 4.

When the execution of the operational program is completed, the data at address 0 is read and stored in the working RAMIO.
The contents of the counter 11 are incremented by 1 and become 1.

When the execution of the first operation program is completed, the data at the first address is read out according to the contents of the counter 11, and the data at the zero address stored in the working RAMIO and }COR in the arithmetic circuit 8 are read out. is removed and a check code is generated, and the generated check code is again used as a working R.
Stored in AMIO. After the above check code has been stored, the contents of counter 11 are incremented by 1 and become 312.
It becomes 1. When the execution of the second operation program is completed, the data at the second address is read based on the contents of the counter 11, the EOR is performed between the data at the second address and the check code in the working RAMIO, and the data is read out based on the contents of the counter 11. After the result is stored in the working RAM again, the contents of the counter 11 are incremented by 1 and become 1f3ew. The above operation is repeated and when the NH content of the counter 11 reaches n+1, the check code in the working RAMIO and the check code written in advance at the n+1 address are EOR'd, and then the constant "111...11'', and if they match, I: If there is no level 1 bit in the output after the logical product, the check in the working RAMIO is - When the code is cleared, the counter 11 is also cleared, and the above operation is repeated again.

If the two do not match, memory error processing such as alarm output is performed. In the above explanation, it is assumed that the contents of the counter 11 are incremented by 1, but the addition amount can take any value. For example, if +2 is specified, data at two consecutive addresses will be read, and this and the working R
Check stored in AMIO. Needless to say, the EOR of the code is taken. Note that even when there is no processing request, the idle loop routine of the operational program is executed to detect a processing request. As is clear from the above description, according to the present invention, a memory check is always performed and if an error is detected, it is reported, so that the contents of the memory can always be guaranteed.

Further, according to the present invention, the ROM in which data is stored
Alternatively, since it is sufficient to provide one check code for vertical parity, CRC, group counting, etc. in the RAM, the amount of hardware required for memory checks can be reduced.

[Brief explanation of the drawing]

1 and 2 are diagrams showing a conventional memory check method, FIG. 3 is a diagram showing an embodiment of the memory check of the present invention, and FIG. 4 is a diagram showing an example of a computer system. . 5...ROM, 6...CPU, 7...
...Control circuit, 8...Arithmetic circuit, 9...
...Program counter, 10...Work RAM, 11...Counter.

Claims (1)

[Claims] 1. A memory having a data area including an operational program and a check code storage area in which check codes generated in advance for all data in the data area are stored, a check data designation counter, and generated check code storage means. In the system, the data specified by the check data specification counter is read from the data area of the memory every time the operation program is executed n times (n is a natural number), and the read data and the generation check are・Generate a new check code by calculating the check code in the code storage means, store the newly generated check code in the generated check code storage means again, and store the check data designation counter When the count value of the check data designation counter reaches a predetermined value, the check code in the check code storage area and the check code in the generated check code storage means are incremented by a unit amount. Compare the two, and if they match, clear the generation check code storage means and return the check data specification counter to its initial value and run the operation program; if they do not match, perform memory error handling. A memory check method that is characterized by: