JPS59201426A - Processing of semiconductor substrate - Google Patents
Processing of semiconductor substrateInfo
- Publication number
- JPS59201426A JPS59201426A JP7570983A JP7570983A JPS59201426A JP S59201426 A JPS59201426 A JP S59201426A JP 7570983 A JP7570983 A JP 7570983A JP 7570983 A JP7570983 A JP 7570983A JP S59201426 A JPS59201426 A JP S59201426A
- Authority
- JP
- Japan
- Prior art keywords
- annealing
- etching
- diffused layer
- contamination
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000001312 dry etching Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 20
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 238000000137 annealing Methods 0.000 abstract description 24
- 238000011109 contamination Methods 0.000 abstract description 15
- 238000005530 etching Methods 0.000 abstract description 10
- 238000001020 plasma etching Methods 0.000 abstract description 9
- 229910052736 halogen Inorganic materials 0.000 abstract description 5
- 229910052721 tungsten Inorganic materials 0.000 abstract description 5
- 239000010937 tungsten Substances 0.000 abstract description 5
- -1 tungsten halogen Chemical class 0.000 abstract description 3
- 150000002367 halogens Chemical class 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000005224 laser annealing Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 238000003672 processing method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 241000218645 Cedrus Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 210000001099 axilla Anatomy 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000002940 repellent Effects 0.000 description 1
- 239000005871 repellent Substances 0.000 description 1
- 238000005001 rutherford backscattering spectroscopy Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体基体の処理方法特にドライエツチング
の除虫じた基体の損傷、汚染の回復及び除去方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for treating semiconductor substrates, and in particular to a method for recovering and removing damage and contamination from dry etching repellent substrates.
背景技術とその問題点
LSI (大規模集積回路)等の半導体装置を製造する
際のエツチング処理の1つとしてドライエツチングがあ
る。一般にこのドライエツチングにおいては、エツチン
グガス成分やエツチング容器の構成物質によってエツチ
ングされる#!−導体導体基体跡面染されたり、物に反
応性イオンミリング(RIM)又は反応性イオンエツチ
ング(I’tIE)ヲ使用した場合には、入射イオンや
電子の加速エネルギーが大きいために半導体基体に結晶
欠陥等の放射損傷が生じることがよく知られている。こ
のため、従来法のような方法を使用してこのような問題
の解決を図っている。即ち、例えば(1)汚染、損傷が
少(なるような条件を選んでドライエラチングラ行う方
法、(2)エツチングの途中でドライエツチングを中止
し、その後汚染、損傷のより少ない例えばウェットエツ
チングを使用してエツチングを続行し、電気的に活性な
領域への汚染、損傷を防ぐ方法、(3)ドライエツチン
グを最後まで行った後、汚染、損傷のより少ない他の手
段によって電気的に活性な領域に生じた汚染、損傷を除
去する方法である。これらの方法の中、(1)及び(2
)は比較的容易に実施することができるが、加工寸法の
細小化と高密度化に伴い、精度の高い微細な加工条件が
要求されるLSI等の半導体装置の製造においては応用
性に欠けるため、実際の利用範囲は非常に狭くなるとい
う欠点がある。これに対して(31の方法は(Ll及び
(21の方法と較べて非常に汎用性のある方法である。BACKGROUND ART AND PROBLEMS Dry etching is one of the etching processes used in manufacturing semiconductor devices such as LSIs (Large Scale Integrated Circuits). Generally, in this dry etching, #! is etched by the etching gas components and the constituent materials of the etching container. - If the surface of a conductor substrate is stained, or if reactive ion milling (RIM) or reactive ion etching (I'tIE) is used, the acceleration energy of the incident ions and electrons is large, so the semiconductor substrate may be damaged. It is well known that radiation damage such as crystal defects occurs. Therefore, conventional methods are used to solve these problems. That is, for example, (1) dry etching is performed by selecting conditions that cause less contamination and damage; (2) dry etching is stopped midway through etching, and then wet etching is performed with less contamination and damage. (3) After dry etching has been completed, the electrically active area can be removed by other means that cause less contamination and damage. This is a method of removing contamination and damage caused to the area. Among these methods, (1) and (2)
) can be carried out relatively easily, but it lacks applicability in the manufacture of semiconductor devices such as LSIs, which require highly accurate micro-processing conditions as processing dimensions become smaller and higher density. However, the disadvantage is that the actual scope of use is very narrow. On the other hand, the method of (31) is a very versatile method compared to the methods of (Ll and (21).
発明の目的
本発明は、上述の点に鑑み、上記(3)の方法の1つと
して#r規な短時間アニールを用いてドライエツチング
侯の半導体基体に生じた汚染、放射+1偽を眩去、回偵
できるようにした半導体基体の処理方法を提供するもの
である。Purpose of the Invention In view of the above-mentioned points, the present invention uses #r order short-time annealing as one of the methods described in (3) above to eliminate contamination and radiation +1 falseness generated on a semiconductor substrate during dry etching. The present invention provides a method for processing a semiconductor substrate that enables recovery.
発明の概要
本発明は、半導体基体の一生面をドライエツチングする
工程と、この主口にランプ九銖ン照射する工程とを有す
る半導体基体の処理方法である。SUMMARY OF THE INVENTION The present invention is a method for processing a semiconductor substrate, which includes the steps of dry etching the whole surface of the semiconductor substrate and irradiating the main opening with a lamp.
このような処理方法を法用することにより、ドライエツ
チングによって半導体基体に生シた汚染、放射損傷が短
時間で除去される。By using such a treatment method, contamination and radiation damage caused to the semiconductor substrate by dry etching can be removed in a short time.
実施例
本来hl!1例は、化1凶A及びBに示すように第1尋
′屯形のシリコン半導体基体(Itの一生面に第2醇i
Hj杉の拡散層(2)が形成され、この拡散層(2)上
の”02rg ta+に例えは反応性イオンエツチング
(RIE)によって拡散層(2)が臨むコンタクト用窓
孔(4)を形成した場合である。本発明に3いては、こ
のように反応性イオンエツチングによってコンタクト用
窓孔(4)を形成した後、タングステン・ハロゲンラン
プにより0.4〜4.0μmの波長のランプ光線をコン
タクト用窓孔(4)に臨む拡散層(2)の面に照射して
短時間のアニールを施す。ここで、拡散層(2)がAs
の拡散層の場合には酸素雰囲気中で上記のアニールを施
し、As以外の不純物の拡散層の場合には真空中で上記
のアニールを施すを可とする。Example originally hl! One example is as shown in Figure 1 A and B.
A diffusion layer (2) of Hj cedar is formed, and a contact window hole (4) facing the diffusion layer (2) is formed on the diffusion layer (2) by reactive ion etching (RIE). In the third aspect of the present invention, after forming the contact window hole (4) by reactive ion etching, a lamp beam with a wavelength of 0.4 to 4.0 μm is emitted from a tungsten halogen lamp. The surface of the diffusion layer (2) facing the contact window hole (4) is irradiated and annealed for a short time.Here, the diffusion layer (2) is made of As.
In the case of a diffusion layer, the above annealing can be performed in an oxygen atmosphere, and in the case of a diffusion layer of an impurity other than As, the above annealing can be performed in a vacuum.
この様な処理方法によれば、アニール時間が数秒から士
数秒と短いため、既に形成された拡散層(2)の不純物
の分布(表面濃度、接合深さ等)に影響を与えずに、ド
ライエツチングで生じた損傷を除去することができる。According to such a processing method, the annealing time is short, ranging from several seconds to several seconds, so dry processing can be performed without affecting the impurity distribution (surface concentration, junction depth, etc.) of the already formed diffusion layer (2). Damage caused by etching can be removed.
また、通常の炉を使用したアニールでは、5I02膜(
3)に窓開けされて露出した拡散層(2)の面に炉の管
からの2次汚染が起り得るが、この発明によればアニー
ル用の管が低温に保たれているために汚染が極めて少(
なる。アニール雰囲気として通常水素が用いられるが、
酸素を使用した場合には、不純物の再分布を生じさせな
いで81基体中の結晶欠陥をアニールすることができ、
しかも短時間アニールで基体表面に形成された薄い5i
02膜により極表面の汚染除去と不純物の外部拡散の防
止にオU用することができる。In addition, in annealing using a normal furnace, the 5I02 film (
3) Secondary contamination from the furnace tube may occur on the surface of the diffusion layer (2) exposed by opening the window, but according to this invention, the contamination is prevented because the annealing tube is kept at a low temperature. Very few (
Become. Hydrogen is usually used as the annealing atmosphere, but
When oxygen is used, crystal defects in the 81 substrate can be annealed without causing redistribution of impurities;
Moreover, the thin 5i formed on the substrate surface by short-time annealing
The 02 membrane can be used to remove contamination from the extreme surface and prevent impurities from diffusing to the outside.
またアニール雰囲気を真壁にした場合には、極表面の汚
染が気化して除去され、同時に基体の内部もアニールさ
れる。しかし、具全中でアニールする場合、基体自身の
高温によるエツチング現象、不純物の外部拡散や気化に
よる抜けが生じないように充分注意する必要がある。Further, when the annealing atmosphere is set to a solid wall, contamination on the extreme surface is vaporized and removed, and at the same time, the inside of the substrate is also annealed. However, when annealing is performed in the entire material, sufficient care must be taken to avoid etching of the substrate itself due to the high temperature, external diffusion of impurities, and omissions due to vaporization.
第2図は本発明の処理方法を用いたときのシリコン基体
の結晶欠陥の回復度をヘリウム(Hりによるラザフオー
ド・パックeスキャタリング(RB S )法で測定し
た結果である。試料は四面で比抵抗8〜12Ω偏のP形
シリコン基体を用いた。このシリコン基体に反応性イオ
ンエツチング(CF4 + H2r5Pa 、 300
W )により10分間全面エツチングをして基体の表
面に汚染と放射損傷を与えた後、バレル型エツチング装
置を使用して酸素プラズマで30分間洗浄し、次に、H
2SO4とHNO3の混合溶液中で煮沸した後、緩衝H
F溶液でライトエッチした。このシリコン基体に対して
、酸素雰囲気中(これはAsが拡散された基体だからで
あり、その他の場合は真仝にする)、ヒータ電fi97
Aの条件で照射時間を変えて、タングステン・710ゲ
ンランプによるアニールを行った。曲fit (A)
、 (B) 。Figure 2 shows the results of measuring the degree of recovery of crystal defects in a silicon substrate using the Rutherford-Pack e-scattering (RBS) method using helium when using the treatment method of the present invention. A P-type silicon substrate with a specific resistance of 8 to 12 Ω was used.This silicon substrate was subjected to reactive ion etching (CF4 + H2r5Pa, 300 Ω).
The surface of the substrate was etched for 10 minutes with W) to cause contamination and radiation damage, and then cleaned with oxygen plasma for 30 minutes using a barrel-type etching device, and then etched with H
After boiling in a mixed solution of 2SO4 and HNO3, buffer H
Light etching was performed with F solution. This silicon substrate is exposed to a heater electric fi97 in an oxygen atmosphere (this is because the substrate is diffused with As, otherwise it is true).
Annealing was performed using a tungsten 710 gen lamp under conditions A while changing the irradiation time. Song fit (A)
, (B).
(C)及びCD)は、照射時間を夫々3秒、4秒、5秒
及び6秒とした場合の測定結果である。また、曲線(E
)は(111)面のシリコン基体を使用して、ドライエ
ツチングも上記アニールもしなかった場合の測定結果、
曲線(F)は(111)面のP形シリコン基体を使用し
て上記条件と同じ反応性イオンエツチングを行った後、
上記アニールをしなかった場合の測定結果である。第2
図において、横軸は値が小さい程基体の奥の方を示し、
縦軸は1ぽが大きい程結晶欠陥が多いことを示す。但し
、(111)面と四面との結晶面の相違による)LB’
Sの分析差はほとんどないことが確かめられた。この測
定結果から、シリコン基体に本アニールを6秒間行った
場合(曲線(D))に結晶欠陥が腋も良く回復している
ことがわかる。(C) and CD) are the measurement results when the irradiation time was 3 seconds, 4 seconds, 5 seconds, and 6 seconds, respectively. Also, the curve (E
) is the measurement result when using a (111) plane silicon substrate without dry etching or the above annealing,
Curve (F) is obtained after performing reactive ion etching under the same conditions as above using a P-type silicon substrate with a (111) plane.
These are the measurement results when the above-mentioned annealing was not performed. Second
In the figure, the smaller the value of the horizontal axis, the deeper the base,
The vertical axis indicates that the larger the value of 1 po, the more crystal defects there are. However, due to the difference in crystal plane between the (111) plane and the four planes) LB'
It was confirmed that there was almost no difference in the analysis of S. From this measurement result, it can be seen that when the main annealing was performed on the silicon substrate for 6 seconds (curve (D)), the crystal defects were well recovered even in the axilla.
ナオ、短時間アニール技術としてレーザ・アニールが知
られているが、コヒーレント光を使用するレーザ・アニ
ールの場合にば5i02膜の干渉効果のため、コンタク
ト用窓孔(4)の端部でアニール族が不連縫になる。し
かし、本発明のタングステン書ハロゲイランプによるア
ニールでは、インコヒーレント光(λ−0,4〜40μ
m)を使用するので、レーザ・アニールのような現象は
避けられる。Laser annealing is known as a short-time annealing technique, but in the case of laser annealing using coherent light, the annealing process occurs at the end of the contact window hole (4) due to the interference effect of the 5i02 film. becomes discontinuous stitches. However, in the annealing using the tungsten halogen lamp of the present invention, incoherent light (λ-0, 4 to 40μ
m), phenomena such as laser annealing are avoided.
尚、本発明の処理方法では、ドライエツチングとして例
えばスパッタ、ミリング、反応性イオンエツチング、反
応性イオンミリング等を使用した場合には物理的な損傷
が除去され、プラスマエッチングを使用した場合にはエ
ツチング付加−物が昇華除去される。In addition, in the processing method of the present invention, physical damage is removed when sputtering, milling, reactive ion etching, reactive ion milling, etc. are used as dry etching, and etching is removed when plasma etching is used. The adduct is removed by sublimation.
発明の効果
本発明によれば、短時間で半導体を処理することができ
るために、既に形成された不純物の分布に影4vを与え
ないで、ドライエツチングで生じた放JAJ損鎖、汚染
を除去することができる。また、ドライエツチング後の
アニールではインコヒーレント光を利用するので、レー
ザ・アニールの場合のよづな窓孔の店M部でアニール族
が不連続になる睨奴が避けられる。Effects of the Invention According to the present invention, since the semiconductor can be processed in a short time, it is possible to remove the released JAJ loss chains and contamination caused by dry etching without affecting the distribution of impurities that have already been formed. can do. Furthermore, since incoherent light is used in the annealing after dry etching, it is possible to avoid the problem of laser annealing where the annealing group becomes discontinuous in the M part of the window hole.
図面の↑115単な簡明
第1図A及びBは本発明の処理方法の1実施例の説明に
供する断面図、第2図は、ドライエツチングした後タン
グステン中ハロゲンランプによるアニールを行った半導
体基体をラザフオード・バック・スキャタリング法で測
定した+’t (9+図である。↑ 115 of the drawings. Figures 1A and B are cross-sectional views for explaining one embodiment of the processing method of the present invention. Figure 2 shows a semiconductor substrate that has been dry etched and then annealed using a halogen lamp in tungsten. +'t (9+) was measured by the Rutherford back scattering method.
第1図
第2図
ナヤン辛ル軟
手続補正書
1.事件の表示
昭和58年特許願第 75709 号2、発明ノ名称
半導体基体の処理方法3、補正をする者
事件との関係 特許出願人
住所 東京部品用区北品用6丁目7番35号名称(2]
81 ソニー株式会社
代表取締役 大 賀 典 雄
5、補正命令の日付 昭和 年 月 日6、
補正により増加する発明の数Figure 1 Figure 2 Nayanshinru Soft Procedure Amendment 1. Display of the case 1982 Patent Application No. 75709 2, Title of the invention Method for processing semiconductor substrates 3, Person making the amendment Relationship to the case Patent applicant address 6-7-35, Kitashinyo, Tokyo Parts Ward Name ( 2]
81 Sony Corporation Representative Director Norio Ohga 5, date of amendment order: 6, 1939,
Number of inventions increased by amendment
Claims (1)
主面にランプ光線を照射する工程とを有する半導体基体
の処理方法。A method for processing a semiconductor substrate, comprising the steps of dry etching the entire surface of the semiconductor substrate, and irradiating the main surface with a lamp beam.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58075709A JPH0656846B2 (en) | 1983-04-29 | 1983-04-29 | Method for treating semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58075709A JPH0656846B2 (en) | 1983-04-29 | 1983-04-29 | Method for treating semiconductor substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59201426A true JPS59201426A (en) | 1984-11-15 |
JPH0656846B2 JPH0656846B2 (en) | 1994-07-27 |
Family
ID=13584021
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58075709A Expired - Lifetime JPH0656846B2 (en) | 1983-04-29 | 1983-04-29 | Method for treating semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0656846B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6333829A (en) * | 1986-07-03 | 1988-02-13 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Method of restoring semiconductor wafer |
US4743564A (en) * | 1984-12-28 | 1988-05-10 | Kabushiki Kaisha Toshiba | Method for manufacturing a complementary MOS type semiconductor device |
JPH01206620A (en) * | 1988-02-15 | 1989-08-18 | Toshiba Corp | Manufacture of semiconductor device |
US5024955A (en) * | 1989-01-19 | 1991-06-18 | Toko, Inc. | Variable-capacitance diode element having wide capacitance variation range |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5651580A (en) * | 1979-10-01 | 1981-05-09 | Toshiba Corp | Plasma etching method |
JPS5776846A (en) * | 1980-10-31 | 1982-05-14 | Fujitsu Ltd | Surface treating method for semiconductor |
-
1983
- 1983-04-29 JP JP58075709A patent/JPH0656846B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5651580A (en) * | 1979-10-01 | 1981-05-09 | Toshiba Corp | Plasma etching method |
JPS5776846A (en) * | 1980-10-31 | 1982-05-14 | Fujitsu Ltd | Surface treating method for semiconductor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4743564A (en) * | 1984-12-28 | 1988-05-10 | Kabushiki Kaisha Toshiba | Method for manufacturing a complementary MOS type semiconductor device |
JPS6333829A (en) * | 1986-07-03 | 1988-02-13 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Method of restoring semiconductor wafer |
JPH01206620A (en) * | 1988-02-15 | 1989-08-18 | Toshiba Corp | Manufacture of semiconductor device |
US5024955A (en) * | 1989-01-19 | 1991-06-18 | Toko, Inc. | Variable-capacitance diode element having wide capacitance variation range |
Also Published As
Publication number | Publication date |
---|---|
JPH0656846B2 (en) | 1994-07-27 |
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