JPS59198753A - Mos type dynamic memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the integration degree by reducing the element area by a method wherein the gate layer of an MOS transistor constituting a transfer region is provided by overlapping a capacitor constituting the memory cell part. CONSTITUTION:An oxide film and a nitride film are formed on a P<-> type Si substrate 1 and locally oxidized, thus forming a butterfly shape surrounded by an element isolation insulation film 9. It is removed by leaving only a side wall 24 on the side surface of the oxide film 21 by performing RIE of anisotropic etching. Next, boron is diffused with said film 21 having the side wall 24 as a mask. The oxide films 21 and 26 and the side wall 24 are removed, and a poly Si layer is formed after gate oxidation and treated with phosphorus. A poly Si layer 6 as the capacitor electrode is formed by removing only the part to be made as the contact region by photo resist process and etching. Finally, after forming a PSG film over the entire film, the contact part is window-opened by photo resist process and etching, and Al is vapor-deposited and processed by photo resist and etching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a MOS transistor comprising a memory cell section consisting of a capacitor and a transfer region consisting of a MOS transistor.
This relates to type 8 dynamic memory.

[Background of the invention]

FIG. 1 shows an example of this type of MO8 type dynamic memory (D/RAM) conventionally used.

The figure shows two elements arranged side by side, with figure (a) being a sectional view and figure (b) being a plan view. In the figure, two circular memory cell portions MC are connected to a transfer region MO8TR consisting of a MOS transistor. 1 is P
type silicon substrate, 2 is an N layer, 3BN+7-strain layer, 4 is a gate layer consisting of a polysilicon layer, 5 is 8i0
6 is a polysilicon layer as a capacitor electrode, 7 is a passivation film made of PSG, 8 is an Al signal line, and 9 is an isolation insulating film between elements. The gate layer 4 crossing between the two memory cell parts constitutes a word line, and the central part of both forms a contact part 1o, and A77 pieces a8 serve as data lines common to both.

As is clear from the figure, since the transfer region has source/drain regions in addition to the gate layer 4, it occupies an area equal to or larger than that of the memory cell portion.

However, in order to increase the degree of integration, memory capacity,
It is necessary to reduce the element area as much as possible without impairing MO8 characteristics and the like.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide a MOS dynamic memory that can reduce the element area and improve the degree of integration, and a method for manufacturing the same. .

[Summary of the invention]

In order to achieve such an object, the gate layer of the MOS transistor constituting the &:L transfer region of the present invention is provided so as to overlap a part of the capacitor constituting the memory cell section. In addition, in order to form such a structure, a semiconductor layer of a second conductivity type, which is to constitute a part of the gate formation region of a semiconductor substrate of a first conductivity type, is formed using a first mask layer. After forming, a side wall is formed on the side surface of the first mask layer facing the MOS transistor formation region using a second mask layer processed using anisotropic etching, and using this as a mask, the second conductivity type is etched. After forming a semiconductor layer of the first conductivity type and a gate layer on the center body layer, this gate layer portion is removed (a second layer forming a capacitor and a source/drain region is formed in the MOS transistor forming region and the memory cell region). A semiconductor layer having a conductivity type is formed.Hereinafter, the present invention will be explained in detail using examples.

[Embodiments of the invention]

FIG. 2 shows an embodiment of the invention. Similar to FIG. 1, two elements are shown side by side, with FIG. 1(a) being a sectional view and FIG. 1(b) being a plan view. As is clear from the figure, the gate layer 4 made of the polysilicon layer of the MOS transistor constituting the transfer region MO8T is connected to the memory cell portion RJ.
By incorporating it into the inside of C, the element area is significantly reduced. Furthermore, the decrease in memory capacitance caused by such a structure is caused by the N1m2' provided below the gate layer 4.
This is compensated for by the PN junction capacitance formed in the multilayer structure.

Note that the gate capacitance increases as the gate width increases from Wl in the conventional example shown in Fig. 1 to W2, but the characteristic parameter expressed as the ratio to the gate length increases from Wl/L to W2/L. This disadvantage can be compensated for by the improvement in the rm value obtained.

FIG. 3 shows another embodiment of the invention. In this figure, each element is arranged in pairs of two as in FIG. 2, and four elements are shown. Figure (a) is a cross-sectional view, and figure (b) is a plan view. In the first embodiment, the memory cell portion MC is formed in a circular shape in the embodiment shown in FIG. The reason why the transfer region that connects the two memory cell sections is shaped like an array or butterfly is that, as mentioned above, if it is made wider, the gate capacitance increases and the operation speed is slowed down. This is to reduce the gate width W. In FIG. 3, the MOS transistor MO8FET corresponding to each memory cell section is An N layer 12 is provided, and one end thereof is connected to an N layer 13 provided in the memory cell section.The two MOS transistors MO8FET are connected by a common 8 layer 14 and a contact section 10 and connected to the i signal line 8. are doing.

Moreover, the polysilicon layer 6 as a capacitor electrode is made of MO
It is formed so as to ride on the gate layer 4 of the S transistor. Further, the gate layers 4 are arranged close to each other in parallel with the central contact part 10 in between, and are made of aluminum.
It runs perpendicular to signal line 8.

Next, one method for forming such a structure will be explained using FIG. 4.

First, an oxide film (SiOz) and a nitride film (8ia
N+) is formed and local oxidation is performed to form an inter-element isolation insulating film 9.
Create a butterfly-shaped shape surrounded by. Next, the entire surface is oxidized to form a relatively thick (~5000A) oxide film 21, and photoresist processing and etching are performed to form areas ABCD and EFG symmetrically with respect to the center line of the butterfly shape.
Eight layers 22 are formed by opening a window in H and diffusing phosphorus relatively deeply. The widths of AB and EF are set to be wider than the gate length of the MOS transistor, and the width BE is set to a width that allows photoresist processing of the contact hole (FIG. 4(a)).

Next, after removing the oxide film 21 in the BEDG region, CVD
As shown by the broken line, the oxide film 23 is formed to a thickness of about 5000 Å or less, and is removed by RIE of anisotropic etching, leaving only the sidewall 24 on the side surface of the oxide film 21 (FIG. 2(b)). ).

Next, by diffusing boron using the bulge 21 having the side wall 24 as a mask, two layers 25 are formed at a distance dl (~0.5 μm) inside the AC and FH lines.
can be formed (area A'BEF'H'GDC'). In this case, the N layer 22 is a single P layer, and the P'' layer directly under the oxide film 21 is a P layer. 26 is an oxide film formed in the diffusion process (FIG. 4(C)). The distance d1 is the sidewall 24ON layer. This dimension is determined by the dimension in contact with the oxide film 22, but this dimension can be controlled by the thickness of the oxide film 23.

Next, the oxide films 21 and 26 and the sidewalls 24 are removed, a polysilicon layer is formed after gate oxidation, and a phosphorus treatment is performed, so that the etched edges of the polysilicon are located within A'B and F'B. Then, photoresist processing and etching are performed to form the gate layer 4 of the MOS transistor MO8FET on the gate oxide film 27. Next, after depositing phosphorus over the entire surface of the substrate, diffusion is performed to form eight layers 13 and 14 in the region excluding the gate layer 4 made of polysilicon, and phosphorus is also deposited sufficiently into the gate layer 4. (Figure 4(d)).

Next, a silicon oxide film 28 is formed by performing gate oxidation in wet 02, but the oxide film on the gate layer 4 made of polysilicon containing phosphorus is formed sufficiently thicker than other parts. be done. Thereafter, after forming a nitride film 29 on the entire surface, a polysilicon layer is again formed on the entire surface, and a portion to be used as a contact region (indicated by a dashed line in FIG. 3(b)) is formed by photoresist processing and etching. The polysilicon layer 6 is removed as a capacitor electrode (FIG. 4(e)).

Finally, after forming the PSO film on the entire surface, photoresist processing and etching are performed to form the contact portion i.

A window is opened, Al is deposited, photoresist processed and etched, and an Al window running perpendicular to the gate layer 4 is formed.
By forming the signal line 8, a structure as shown in FIG. 3 is obtained. That is, the 8th layer 22 covers the 8th layer 12 below the gate layer 4, the 2nd layer 25 covers the 2nd layer 11, and the oxide film 27.2
8 and the nitride film 29 form the absolute R film 5, respectively.

In this way, by self-alignment using RIE, N)? 'N layer 12 connected to j13
(22) can be formed.

〔Effect of the invention〕

As explained above, according to the present invention, the device area is It became possible to reduce the Further, according to the manufacturing method of the present invention, after forming the semiconductor layer of the second conductivity type constituting the capacitance below the gate layer, the semiconductor layer is The first layer leaving a slight side edge of the layer.
A semiconductor layer of a second conductivity type that is connected to a semiconductor layer of a second conductivity type below the gate layer at the side end portion by forming a semiconductor layer having a quadriconductivity type and further introducing impurities using the gate layer as a mask. By adopting the method of forming the M
This is useful for improving the degree of integration of O8 type dynamic memory.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a cross-sectional view and a plan view showing a configuration example of a conventional MO8 type dynamic memory, and FIG.
a) and (b) are a cross-sectional view and a plan view of an MO8 type dynamic memory showing one embodiment of the present invention; FIG. 3(a)
and ('b) are a sectional view and a plan view of an MO8 type dynamic memory showing another embodiment of the present invention, and FIG. 4(a)
-(e) are cross-sectional views showing an example of the manufacturing method. DESCRIPTION OF SYMBOLS 1...P-type silicon substrate, 2...N layer constituting the PN junction capacitance of the fist/memory cell portion, 3...@N source/drain layer, 4...gate layer, 5... ... Absolute R film, 6. Polysilicon layer as capacitor electrode,
11-...Pi, 12...N layer under the gate layer, 1
3... N layer, 14... N layer constituting the source/drain layer, 21... oxide film (first mask layer),
22...N layer (semiconductor layer having second conductivity type), 2
3...Oxide film (second mask layer), 24...Side wall, 25...P) Semiconductor layer having 4-type conductor type), 27...・Gate oxidation jjj+. Agent Patent Attorney Akio Takahashi

Claims (1)

[Claims] 1. MO8 constituted by a memory cell section consisting of a capacitor and a transfer region consisting of a MOS transistor
In type dynamic memory, part of the capacity is MOS
An MO8 type dynamic memory comprising a PN junction capacitor formed by providing a semiconductor layer of an opposite conductivity type in a semiconductor substrate below a gate layer of a transistor. 2. Impurities are introduced into a semiconductor substrate having a first conductivity type using a first mask layer covering the MOS transistor except for the gate formation region as a mask, and a second conductivity opposite to the first conductivity type is introduced into the gate formation region. a step of forming a semiconductor layer having a shape, a step of removing the first mask layer leaving only the outer periphery of the MOS transistor formation region, and a step of removing the first mask layer leaving only the outer periphery of the transistor formation region; The mask layer is subjected to anisotropic etching to reduce the MQ8 of the first mask layer.
A step of forming a sidewall covering the side surface facing the transistor formation region, and introducing an impurity using the first mask layer provided with the sidewall as a mask to form a first conductivity type on the semiconductor layer having the second conductivity type. A step of forming a semiconductor layer with a gate electrode formed thereon, and a step of forming a semiconductor layer with a gate MOS transistor formed thereon via an insulating film on the MOS transistor formation region.
forming a semiconductor layer having a second conductivity type on the semiconductor layer having the first conductivity type by introducing impurities into the gate layer portion (MOS) transistor formation region and the memory cell portion; M characterized by including the process
A method for manufacturing O8 type dynamic memory.