JPS59198052A - Phase locked circuit - Google Patents

Abstract

PURPOSE:To attain quickly the initial phase locking by using a complex conjugation value of two signals in a base band as the correction of the initial phase difference, and feeding back the product of two output signals of a complex multiplier as the input of a phase locked loop. CONSTITUTION:An AM-PM-VSB signal is branched into two, and applied to multipliers 11, 12, where the products f1, f2 between the signals and two orthogonal carrier waves having the same frequency as the carrier frequency are obtained respectively. The signals are converted into two orthogonal base band signals via a low pass filter 13. The signals are doubled by multipliers 14, 15 into signals g1(t) and g2(t) and added to a complex multiplier 17. An output of the 1st integration device 19 is applied to a correction vector forming section 20. This output is added to a vector correcting section 21 and the internal phase of this time is decided by multiplying a correction vector to the preceding value of the 2nd integration device 23 in terms of complex number. A vector AGC section 22 controls the gain so that the internal phase vector is traced on the unit circle.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a phase synchronization circuit that fully demodulates a vestigial sideband amplitude/phase modulated signal used in data transmission such as facsimile.

(2) Technical background The residual sideband amplitude/phase modulation (AM) target of this circuit is
-PM-VSB) signal will be explained using FIG. Figure 1 (1) shows 2
A value data signal is shown. In the data signal, for example, "0" represents white and "1" represents black. The data signal is subjected to binary-to-ternary conversion (amplitude modulation (AM)) to become a ternary data signal (x (t)), as shown in FIG. 1(2). Carrier wave is phase modulated (PM) by ternary data signal
Then, the AM-PM multiplied signal shown in FIG. 1(3) is obtained. The carrier wave phase of the portion corresponding to "+1" of the AM-PM multiplied signal ternary data signal is O phase, and the portion corresponding to "-1" is π phase. The AM-PM-VSB signal is a signal obtained by further filtering the AM @PM signal with a VSB filter.

AM-PM-VSB signal f obtained in this way
(t) is expressed in the following form. fc is the frequency of the carrier wave.

t (t) = x(t) cos 2πf Ct +
0(t) sin 2πfct where (t) = 2πfc
The term t is a term of an orthogonal component caused by Δ due to the characteristics of the VSB filter, and X(t) is a signal whose phase is rotated by 90 degrees with respect to (1).

(3) Prior art and problems Conventionally, a circuit for demodulating an AM-PM-VSB signal as described above first demodulates the signal to baseband using two orthogonal carrier waves (2πfct and 5ln2πfct) equal to the carrier frequency, and then The two signals thus obtained are added to one input of a complex multiplier, and the output of the complex multiplier is appropriately weighted, and the output is then outputted to a first integrator, a correction vector generation section, a vector correction section, and a vector AGC section.

In addition to the other input of the complex multiplier, synchronous detection is performed via a phase-locked loop composed of a second integrator and a second integrator. This circuit has the problem that the initial phase synchronization takes time and its accuracy is not always satisfactory, and it is difficult to correctly correct the phase error especially in the case of AM-PM-VSB signals where phase inversion occurs frequently. was there. Furthermore, due to the interference of orthogonal components, there is a problem that the influence of such deterioration accumulates in sections where phase synchronization is lost at a change point of the transmitted data, or where the carrier wave disappears.

(4) Object of the Invention One object of the present invention is to solve the above-mentioned problems in the conventional circuit by using the complex conjugate value of two baseband signals as a correction for the initial phase difference, and by using the complex conjugate value of the two baseband signals as the input of the phase-locked loop. Based on the idea of feeding back the product of two output signals of a complex multiplier as It is possible to extract the phase difference, correct the phase difference, and obtain a high-quality demodulated signal.

Another object of the present invention is to provide an initialization determination circuit and a loop connection determination circuit, and based on the concept of controlling initialization and feedback to the phase-locked loop, respectively, initialization and feedback to the phase-locked loop are performed only at appropriate times. The purpose is to carry out feedback so that the correct demodulation operation can continue even during the period when the carrier wave is lost without being affected by the interference of orthogonal components.

(5) Structure of the Invention In one form of the present invention, synchronous detection of a residual sideband amplitude/phase modulated signal is performed by multiplying two orthogonal carrier waves having a frequency equal to the carrier frequency and passing the signal through a low-pass filter. , generate baseband signals of in-phase and quadrature components for the original signal, add these two signals to one input of a complex multiplier, and send the output of the complex multiplier to the complex multiplier via a phase-locked loop. A phase synchronization circuit that performs feedback to the other input of the baseband signal, wherein a complex conjugate value of the baseband signal is input to the other input of the complex multiplier as correction of the initial phase difference. A circuit is provided.

In another embodiment of the present invention, the synchronous detection of the amplitude and phase modulated signal in the residual 1Ill waveband is performed by multiplying the signal by two orthogonal carrier waves having a frequency equal to the carrier frequency and passing the resultant signal through a low-pass filter. All baseband signals of in-phase and quadrature components are applied to one input of a complex multiplier, and the output of the complex multiplier is passed through a phase-locked loop to the other input of the complex multiplier. In a phase synchronization circuit that performs feedback, an initialization judgment circuit detects the absolute level and amount of variation of the baseband signal and compares it with a predetermined threshold, and the absolute level and variation of the circle of the complex multiplier. a loop connection determination circuit for detecting the amount and comparing it with the predetermined threshold; The complex conjugate value of the two signals is vectorally blunt initialized, and the product of the two output signals of the complex multiplier is fed back to the phase-locked loop according to the judgment of the loop connection judgment circuit, so that the carrier wave is There is provided a phase-locked circuit characterized in that the phase-locked loop is disconnected from the remaining section and allowed to run freely with the amount of phase fluctuation determined so far.

(6) Embodiment of the Invention A block circuit diagram of a phase locked circuit as a first embodiment of the invention is shown in FIG. This circuit is multiplier 11.12
, 14, 15, 16 and 18° low pass filter (LPF
)13. Complex multiplier 17. and a first integrator 19 that constitutes a phase-locked loop; and a correction vector creation section 20. The vector correction section 21 includes a vector AGC section 22 and a second integrator 23. The AM-PM-VSB signal is branched into two and applied to multipliers 11 and 12, where they are divided into two orthogonal transmission waves (part 2πf) having a frequency equal to the carrier frequency.
ct and 2πfct) are determined.

The two obtained signals f1 and f2 are in the resistance range 1
3, the signal is converted into two orthogonal baseband signals. The two converted baseband signals are doubled by multipliers 14 and 15, respectively, and the signal F+(t
) and =V2(t) are applied to one input of the complex multiplier 17. On the other hand, the signal L(t) remains as it is, and the signal g2(t) is multiplied by -1 by the multiplier 16 and the second
is added to the integrator 23. That is, the complex conjugate value is added to the second block divider 23 (see the broken line in FIG. 2).

The two outputs h of the complex multiplier 17! (t) and h+(
t) is multiplied by the multiplier 18 and added to the first divider 19. Moreover, h 1 (t) becomes the demodulated output as it is. The first integrator 19 integrates the phase error Δ to calculate a correction scalar amount of the internal phase between the sample and the sample.

The output of the first divider 19 is supplied to the correction vector creation section 2o. The correction vector generation unit 20 is also supplied with the output of the second divider 23, and the correction vector generation unit 20 is supplied with the output of the second divider 23.
The vector amount to be corrected this time is calculated from the output of the integrator 19 and the previous value of the second integrator 23. The output of the correction vector creation section 20 is applied to the vector correction section 21. The vector correction unit 21 complex multiplies the previous value (previous internal phase) of the second integrator 23 by a correction vector to determine the current internal phase. The output of the vector correction unit 21 is the vector AG
C (automatic gain control) section 22, vector AGC
The unit 22 performs gain control on the current internal phase vector that has been corrected for the phase error so that it rides on the unit circle, and uses signals j1(ri and ν2() as the current internal phase.
t) is supplied to the second integrator 23. 2nd net separator 23
In the initial setting, the signals fi t (t) and -92(t) k are used, and at other times than the initial setting, the signal 71 is used.
(t) and g2(t) to the other input of the complex multiplier 17.

The operation of each of the circuit components described above will be explained using mathematical formulas. The long sword signal f(1) of the circuit in Figure 2 has an initial phase of θ0.
and phase fluctuation φ(1) due to the influence of the line, then f(t)=x(t)cz(2πfct+θ0+φ(t
) ) +0(t)sin (2πfct+θ0+φ(
t)), and the input of the LPF 13 is f 1 (t) = x(t) cos (2πfct + θ
0+φ(t))・coS2πfct+'5t)sin
(2πfct+00+φ(t)) ・cos 2πfc
tf 2 (t) = x (t) cos(2πf(t
+θ0+φ(t))11sLn2πfct+”(t)s
tn (2πfat+θ0+φ(t))・5ln2πf
ct.

When fully deformed, χ(1> f2(t)=-[5ln(4πfct+θθ+φ(t)
) 5in(θI)+φ(1)))-dyed [winter (4πf
Ct+θ0+φ(←(θ0+φ(1))). LP
The double frequency component is removed from the F output, and 91(t) = x(t)
cos (θ0+φ(t) ) +4t)s+z+ (
θ. +φ(1)) −...(1),! 92(t)=
-X(t) 8 stones (θ.+φ(t) ) +”(t)α3
(θ. 1φ(t)) ・(2). This is AM
-PM - This is a baseband signal obtained by removing the carrier component from the VSB signal. Here, the relationship between the sending data signal (1) and the gold (1) is shown in FIG.

In this circuit, the initial phase difference is corrected by the signal 1 to be demodulated.
1(t) and jl 2 (t), the phases Fl(t) and ! i'z(t),
This is achieved by initializing with @1(1) and 12(t).

In the section indicated by the arrow in Figure 3, equations (1) and (2) can be expressed as follows, so 1, F, (t)2x(t)cos(θ0+φ(t))
92 (t) −x (t) sin (θ0+φ(t)
)x(t)=1, g + (
0) -g 1(0) -x(0)cos (θ0+φ
(0) ) = cos (θθ+φ(0))g2 (0
) −−g2 (0) = x(0)sin (θ0+
If the initial setting is φ(0))=s stone(θθ+φ(0)), the internal phase of the phase locked circuit will match the initial phase of the input. Processing after initial setting is performed for each function of the phase-locked loop.

The complex multiplier 17 performs processing as shown in the following equation.

h 1(t)=,F 1ft)・L(t) 92(
t)・g2(t)h 2 (t)=91(t)・,! i
'2(t)+c(1)・,9z(t) In the section indicated by the arrow in FIG. ) I
IcosΦ1”cosΦ2+ x(t)sΦI0S stoneΦ
2-x(t) μs (1 of Φ2-) h 2 (t)-x(t) -cosΦ111SIfl
Φ, -x(t)slnΦ1・瀉Φ2= x(t)si
n (Φ2 - Φ1) When Φ1 = Φ2, the data signal (1) is obtained as 1z(t) as the demodulated output, b2(t) becomes 0, and the loop feedback amount becomes 0. . When Φ2=Φl+Δ, h 1 (t) = x (t) Δ h 2 (t) = x (t)si+]Δ), the phase difference Δ is extracted.

The feedback amount for phase inversion is controlled by a complex multiplier 1702.
The product y (t
)'i and determine it as the feedback amount.

y(t)−h+(t)・h2(1)= ,(t)
2YongΔYuΔ=x(t)2−zgstone2Δ y(t) obtained in this way is y when Δ is small.
The phase error can be evaluated as (t) # x (t)2Δ, where X(t)2 corresponds to the phase reversal of the O phase and the π phase. The phase error Δ can be extracted without being affected by the sign change in (1).

FIG. 4 shows a diagram explaining the vector correction method of the phase locked circuit. In the figure, R indicates the real axis and I indicates the imaginary axis.

A block circuit diagram of a phase locked circuit as a second embodiment of the present invention is shown in FIG. This circuit differs from the first embodiment in that an initialization determination circuit 31, a loop connection determination circuit 32, and a multiplier 33 are added.

In order to initialize the complex conjugate value of the input signal to the second integrator 23 of the phase-locked circuit at the beginning of operation and correct the internal phase by the initial phase difference of the signals (initialization), there is no interference of orthogonal components, and the system It is inevitable that this is a period in which the pirates are still active. To detect such periods (A, E and J in Fig. 3, the signal v = 111
(t)2+172 (t)2= x(t)2+you(t)
``f!r: Find the level as the threshold value Th.

and Th2. For periods A, E, and J in FIG. 3, V(t) = x(t)2#1.0. In addition, in order to determine that the data change points such as B, D, F, and H in Fig. 3 are not periods where interference from orthogonal components occurs, the previous samples for gl(t) and Vz(t) are used. The difference between ΔL (t) = l, fi'+ (t)-,! i'
t (t-π)1 and ΔJ'z (t)=I fi2
(t) g2(tfs) Find I, Δg+(t)
and Δ,92(t) as thresholds Th3 and Th4
Compare each. Here, fB represents the sampling frequency. The above-mentioned operation is shown in a flowchart as shown in FIG. In the case of initialization, the signal g+(t) and ! The complex conjugate value of i'2(t) is applied to the complex multiplier 17 via the second divider 23, and in the case of steady processing, a feedback signal from the phase-locked loop is supplied.

bl(t) and b which are input to the loop connection determination circuit
z(t) is gl(t) and ! The result of complex multiplication of i'z(t) and the internal phase vector is as follows.

b+ (t) -9s (t)・cos minute (t) -,
! ? 2 (t)・Withdrawal (1) = x(t) [cos
(θ(t) '(t)))4t)(:=(('(t)
'(t)):)h 2 (t) =ha(t) ・sln
min(t) + g2(t)・J(t)−−x(t)(
sln (θ(1)-min(t)):)+'5 as Hikitei(θ
(t) - Compensation t))]Here, if the phase difference between the signal phase θ(1) and the internal phase 'Th(t) is Δ, then h 1(t)=x(t)cosΔ+0(t)sinΔ
/\hz(t)=x(S stone Δ+x(t)cosΔ. By successively correcting the phase difference metal by Δr, in the steady state, Δ=0. Therefore, h + ( t)
Mai, (1) h 2 (t) #仝(1) Therefore, this human power h 1 (t) and h
2 (t) as well, the signal level V'(t) '' h 1(t)2+ bz as in the initialization judgment.
(t)2 is compared with thresholds Thl and Th2, and Δh2(t)-1hz(t)hz(-±)IS is compared with thresholds Th3 and Th4. Judgment is made in this way, and the error amount is fed back and corrected during periods A, E, and J in Figure 3, and during other periods,
By feeding back the error amount (l), correction is continued using the previously set correction vector. A flowchart of this operation is shown in FIG.

Note that by sending the above-described determination result of the loop connection determination circuit 321-i to the multiplier 33 as a signal of "1" or "0", if it is "0", an error amount of 0 is fed back, and the error amount is "1". ”, the error amount Δ is fed back.

As described above, it is possible to realize a phase synchronization circuit which is not affected by the interference of orthogonal components and can continue correct demodulation operation even during the period when the carrier wave is lost.

In this example, loop connection was determined based on the result of complex multiplication with the internal carrier wave, but when the temporal change in θ(1) can be considered to be sufficiently small, the loop connection is determined in the part where the initialization determination is performed. Even if the determinations are made simultaneously, the effect remains the same, and in this case it is advantageous in terms of processing amount.

(7) Effects of the Invention According to the present invention, initial phase synchronization can be performed quickly, phase errors can be extracted without being affected by sign changes even in the case of signals with frequent phase inversions, and phase errors can be extracted without being affected by sign changes. Correct correction of the phase difference is possible, and as a result, a high quality demodulated signal can be obtained.

In addition, initial settings and feedback to the phase-locked loop are performed only at appropriate times, and the effects of orthogonal component interference are reduced.
i1? Correct demodulation operation can be performed even during periods when no trace of the carrier wave is received.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram for explaining the AM-PM-VSB signal applied to the present invention, FIG. 2 is a block circuit diagram of a phase synchronization circuit as the first embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining the AM-PM-VSB signal applied to the present invention. FIG. 2 is a waveform diagram for explaining the signal waveform in the circuit of FIG. 2, FIG. 4 is a vector diagram for explaining the phase relationship of the signals in the circuit of FIG. 2, and FIG. 5 is a phase diagram of the second embodiment of the present invention. A block circuit diagram of the synchronous circuit and FIGS. 6 and 7 are flowcharts explaining the operation of the circuit of FIG. 5. 11.12... Multiplier, 13... Low pass filter, 1
4.15.16... Multiplier, 17... Complex multiplier,
18... Multiplier, 19... First integrator, 20...
Correction vector creation unit, 21... Vector correction unit, 22
. . . vector correction unit, 23 . . . second integrator, 31.
. . . Initialization determination circuit, 32 . . . Loop connection determination circuit, 33 . . . Multiplier. Patent applicant Fujitsu Ltd. Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate (1) Yukio Patent attorney Akira Yamaguchi Figure 1 (3) AM-PM signal O phase Y phase O phase Figure 6 Figure 7

Claims (1)

[Claims] 1. Synchronous detection of a residual sideband amplitude/phase modulated signal is multiplied by two orthogonal carrier waves with a frequency equal to the carrier frequency, passed through a low-pass filter, and is in phase with the original signal. component and quadrature component baseband signals, apply the two signals to one input of a complex multiplier, and feed the output of the complex multiplier to the other input of the complex multiplier via a phase-locked loop. 1. A phase synchronized circuit for performing a phase synchronization circuit, characterized in that a complex conjugate value of the baseband signal is input to the other input of the complex multiplier to correct an initial phase difference. 2. Synchronous detection of the residual sideband amplitude/phase modulated signal is multiplied by two orthogonal carrier waves with a frequency equal to the carrier frequency and passed through a low-pass filter, and the base of the in-phase and quadrature components is calculated with respect to the original signal. In a phase-locked circuit that generates a band signal, applies the two signals to one input of a complex multiplier, and feeds back the output of the complex multiplier to the other input of the complex multiplier via a phase-locked loop. , an initialization determination circuit that detects the absolute level and amount of variation of the baseband signal and compares it with a predetermined threshold; and a circuit that detects the absolute level and amount of variation of the output of the complex multiplier to determine the amount of caulking. A loop connection determination circuit is provided for comparing with a predetermined threshold value, and according to the determination of the initialization determination circuit, the complex conjugate value of the two baseband signals is input to the other complex multiplier to correct the initial phase difference. is initialized in a vectorial manner, and the product of the two output signals of the complex multiplier is fed back to the phase-locked loop according to the judgment of the loop connection judgment circuit. Disconnect the phase-locked loop,
This phase-locked circuit is characterized by being able to run freely with the amount of phase fluctuation determined so far.