JPH04349739A - Coherent agc system for psk demodulation - Google Patents

Abstract

PURPOSE:To eliminate the need for the adjustment by detecting a coherent AGC level at the acquisition of a PSK signal so as to reduce the acquisition time and forming the entire system with digital circuits. CONSTITUTION:A PCM-PSK base band signal is converted into a digital signal at an A/D converter 3, demodulated by a PSK multiplier digital multiplier adder circuit 5 and the amplitude is adjusted by a coherent AGc circuit 8. A coherent AGC arithmetic operation/LOCK discrimination circuit 15 gives an AGC data to the coherent AGC circuit based on I and Q data from the coherent AGC circuit 8. A PSK demodulation phase error detection use digital multiplier adder circuit 10 detects a phase error of a subcarrier data based on the I and Q data. ROMs 6,7 generate two systems of subcarrier data orthogonal to each other by using a clock outputted from a PSK timing generating circuit 14 after the phase error is corrected and the data is fed to the PSK multiplier digital multiplier adder circuit 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coherent AGC system for PSK demodulation that demodulates PCM baseband signals.

0002

[Prior Art] Conventionally, in circuits used in this type of system, the PSK demodulation circuit is composed of an analog circuit.
The coherent AGC circuit uses only in-phase (INPHASE) data as information for determining the AGC level, regardless of whether the PSK signal is captured or synchronized.

0003

[Problem to be solved by the invention] The above-mentioned conventional PSK
Since the coherent AGC method for demodulation is composed of analog circuits, there is a factor of instability, and it takes a lot of time to adjust and test the performance of each PSK demodulation circuit. Furthermore, when a PSK signal is captured, the coherent AGC level is uncertain, resulting in unstable operation, and there is a drawback that the time required for PSK signal synchronization becomes longer.

0004

[Means for Solving the Problems] The coherent AGC method for PSK demodulation of the present invention provides two-phase PSK modulated PCM
-Digital demodulation means for orthogonally detecting the PSK baseband signal, and digital AGC for correcting the amplitude of two systems of data output from this digital demodulation means based on AGC data.
coherent AGC data calculation means for generating the AGC data based on the two systems of data outputted by the digital AGC means; and subcarrier generation means for generating two systems of subcarrier data orthogonal to each other and supplying the generated subcarrier data to the digital demodulation means.

[0005] The subcarrier generating means generates the two signals based on the two systems of data outputted by the digital AGC means.
a digital synthesizer that generates a sampling clock based on the phase error data from the phase error detection means and subcarrier frequency data given from the outside; The digital synthesizer may be configured to include a ROM that outputs the two systems of subcarrier data at the timing of the sampling clock from a digital synthesizer.

[0006] The digital demodulation means includes an A-D converter that samples the PCM-PSK baseband signal at the timing of the sampling clock;
It may be configured to include two systems of multipliers that multiply data from the D converter by the two systems of subcarrier data from the ROM.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 1 is a low-pass filter (L
PF), 2 is incoherent AGC circuit, 3 is A-D
converter, 4 is an incoherent AGC calculation circuit, 5 is P
SK multiplication digital multiplication and addition circuit, 6 is a ROM circuit for SIN waveform generation, 7 is a ROM circuit for COS waveform generation, 8 is a coherent AGC circuit, 10 is a digital multiplication and addition circuit for PSK demodulation phase error detection, 11 is a PSK demodulation loop 12 is a numerical calculation circuit for PSK demodulation (A
LU), 13 is a subcarrier clock generation synthesizer, 14 is a PSK timing generation circuit, and 15 is a coherent AGC calculation/LOCK determination circuit.

[0010] The PCM-PSK baseband signal subjected to two-phase PSK modulation is passed through the LPF 1 whose cutoff frequency is set by the PSK subcarrier frequency, and the S/N of the input signal is
After the ratio is improved and the signal level (including noise) is made constant by the incoherent AGC circuit 2, the analog signal is converted into a digital signal by the AD converter 3. The sampling clock at that time is supplied from the PSK timing generation circuit 14 whose source oscillator is the subcarrier clock generation synthesizer 13, and the sampling rate is P
It is an integer (2 to the N power) times the SK subcarrier frequency. In addition, the subcarrier clock generation synthesizer 13 and the PSK timing generation circuit 14 generate the synchronization clock and data dump clock in addition to the above-mentioned sampling clock based on externally set PSK subcarrier frequency and bit rate information. It is occurring.

PCM-P output from the A-D converter 3
The SK sampling data is phase-detected by the PSK multiplication digital multiplication/addition circuit 5 using parallel data corresponding to the SIN wave (0 degree phase component) of the SIN waveform generation ROM circuit 6, and the detection output signal is phase-detected by the PSK demodulation in-phase (INPHAS).
E) It becomes data (I data) and is output. PCM-P
SK sampling data is also used as RO for COS waveform generation.
Parallel data corresponding to the COS wave (90 degree phase component) of the M circuit 7 is phase-detected by the digital multiplication/addition circuit 5 for PSK multiplication, and output as PSK demodulated quadrature (QUAD) data (Q data). The phase detection described above is PCM
- A digital multiplication/addition circuit for PSK multiplication (
A digital circuit that combines a multiplier, an adder, and a latch circuit) is multiplied by 5, integrated for the number of samplings determined by the PSK subcarrier frequency/bit rate ratio, and then integrated for an integer number (2 to the N power) of the PSK sampling clock. This is done by dumping with one data dump clock.

The I data and Q data dumped by the digital multiplication/addition circuit 5 for PSK multiplication are each multiplied and added by the coherent AGC circuit 8 with the coherent AGC control data calculated by the coherent AGC calculation/LOCK judgment circuit 15. and output as level-adjusted I data and Q data. Coherent AGC operation/
The LOCK determination circuit 15 uses the magnitude of the composite vector value of the respective vector values of the I data and Q data detected by the digital multiplication/addition circuit 5 for PSK multiplication as coherent AGC control data for the coherent AGC circuit 8.
Output to. The levels of I data and Q data are controlled in the coherent AGC circuit 8 according to the size of the coherent AGC control data.

The PSK demodulation phase error detection digital multiplication/addition circuit 10 converts the phase error data detected by the I data and Q data from the coherent AGC circuit 8 into PSK.
Output to digital filter 11 for K demodulation loop, PSK
A demodulation loop digital filter 11 and an ALU 12 control a subcarrier clock generation synthesizer 13. In the digital filter 11 for the PSK demodulation loop, processing equivalent to a conventional analog loop filter is performed digitally, averaging processing of Q data is performed, and the ALU 1
2, phase error data of the subcarrier frequency is output.

The coherent AGC operation/LOCK determination circuit 15 calculates the I data and Q data by taking the arctangent of the ratio of the respective vector values of the I data and Q data detected by the digital multiplication/addition circuit 5 for PSK multiplication. The relative angle is detected, and the value is passed through a comparator with a threshold value to perform PSK demodulation synchronization (LOCK).
A determination is made. These combined vector and arctangent calculations are performed in the ROM.

[0015] The ALU 12 and the subcarrier clock generation synthesizer 13 are circuits corresponding to a voltage controlled oscillator (VCO) of a conventional analog circuit. Data (integrated by a digital multiplication/addition circuit) is added, and the frequency and phase components of the subcarrier and bit rate sampling clock can be varied digitally. PS that receives the output of the synthesizer 13 for subcarrier clock generation
The sampling clock from the K timing generation circuit 14 is used to generate parallel data corresponding to the SIN wave and the COS wave in the SIN waveform generation ROM circuit 6 and the COS waveform generation ROM circuit 7, and then to the digital multiplication/addition circuit 5 for PSK multiplication. Output to . Dumping of the digital multiplication/addition circuit 5 for PSK multiplication is performed at the timing of a data dump clock having a frequency that is one integer (2 to the N power) of the subcarrier sampling clock frequency.

[0016]

[Effects of the Invention] As explained above, the present invention eliminates the need to adjust the complicated Costas loop of the PSK demodulation circuit by configuring the main part of the PSK demodulation circuit, which is conventionally configured with an analog circuit, with a digital circuit. In addition, there is an effect that the acquisition time can be shortened by detecting the coherent AGC level at the time of signal acquisition of the PSK demodulation circuit and performing stable signal acquisition.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

1 Low-pass filter 2 Incoherent AGC circuit 3 A-
D converter 4 In-coherent AGC calculation circuit 5
PSK multiplication digital multiplication/addition circuit 6 SIN waveform generation ROM circuit 7 COS waveform generation ROM
Circuit 8 Coherent AGC circuit 10 Digital multiplication and addition circuit for PSK demodulation phase error detection

Claims (3)

[Claims] [Claim 1] Two-phase PSK modulated PCM-PSK
digital demodulation means for orthogonally detecting the baseband signal;
The two systems of data output by this digital demodulation means are
digital AGC means for amplitude correction based on the C data;
coherent AGC data calculation means that generates the AGC data based on two systems of data outputted by the digital AGC means;
A coherent AGC for PSK demodulation, comprising subcarrier generation means that generates subcarrier data of two mutually orthogonal systems of the PCM-PSK baseband signal based on system data and supplies it to the digital demodulation means. method. 2. The subcarrier generation means includes a phase error detection means for generating phase error data of the two systems of subcarrier data based on the two systems of data output by the digital AGC means, and this phase error detection means. a digital synthesizer that generates a sampling clock based on the phase error data from the digital synthesizer and subcarrier frequency data given from the outside;
The coherent AGC method for PSK demodulation according to claim 1, further comprising a ROM for outputting system subcarrier data. 3. The digital demodulation means includes an A-D converter that samples the PCM-PSK baseband signal at the timing of the sampling clock, and an A-D converter that samples the PCM-PSK baseband signal at the timing of the sampling clock, and an A-D converter that samples the PCM-PSK baseband signal at the timing of the sampling clock; 3. The coherent AGC method for PSK demodulation according to claim 2, further comprising two systems of multipliers for multiplying subcarrier data of the systems.