JP3578650B2 - Carrier synchronization circuit, quadrature demodulation circuit and interference wave canceller - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a carrier synchronization circuit, a quadrature demodulation circuit, and an interference wave removing device used in a television receiver and a relay broadcasting device, and in particular, generates a stable and high-accuracy reproduced carrier signal and accurately removes an interference wave. The present invention relates to a carrier synchronization circuit, a quadrature demodulation circuit, and an interference wave removing device that can be used.
[0002]
[Prior art]
In Japan, television broadcast signals are transmitted at 90 MHz to 108 MHz and 170 MHz to 222 MHz in the very high frequency band (VHF).
On the other hand, as an ionosphere suddenly appearing at about the same altitude as the ionosphere (E layer) generated at an altitude of about 100 km, there is a so-called sporadic E layer (hereinafter abbreviated as “Espo”). It is known that it frequently occurs from April to August and causes abnormal propagation of VHF waves, which causes interference with foreign FM audio broadcast waves in domestic TV broadcast signals.
[0003]
Therefore, various devices (interference wave removing devices) are conventionally incorporated in some television broadcast relay devices in order to eliminate the influence of interference waves caused by the ESPO. In recent years, in particular, with the development of digital signal processing technology, for example, it is described in “Digitalized E-spot interference interference elimination circuit” in JP-A-10-294888, “Digital processing method of television signal” in JP-A-10-294901, and the like. An interference wave elimination device that can be built in a television receiver by converting a circuit into an LSI using such digital processing has been devised.
[0004]
A quadrature demodulation circuit used in a conventional interference wave removing apparatus using digital processing for removing the interference wave caused by the ESPO will be described with reference to FIG. FIG. 3 is a configuration block diagram illustrating an example of a conventional orthogonal demodulation circuit.
[0005]
As shown in FIG. 3, a conventional quadrature demodulation circuit generally converts a received television broadcast signal into an intermediate frequency signal (IF signal) having a frequency １ ／ of a sampling frequency in a digital circuit at a subsequent stage by an analog circuit. IF signal conversion means 1, A / D conversion means 2 for directly A / D converting the IF signal, and local oscillation signal generation as means for generating a local oscillation signal (hereinafter abbreviated as "local oscillation signal") Means 3, quasi-synchronous detection means 4 for quasi-synchronous detection of an A / D-converted signal using a local oscillation signal, and a complex baseband signal, and a complex limiter and a narrow-band low-pass filter (LPF) from the complex baseband signal. ), A complex carrier signal extracting means 5 for extracting a complex carrier signal, and using the complex carrier signal, correcting the frequency and phase of the complex baseband signal, and And a correcting means 6 for outputting a period detection complex baseband signal.
[0006]
In addition, the local oscillation signal generating means 3 generates a common-mode local oscillation which is a data sequence that changes like “1, 0, −1, 0, 1,...” At regular time intervals according to the sign of the cosine of each π / 2 radian. A COS signal generating means for outputting a signal (hereinafter referred to as a “COS signal”) and “0, −1, 0, 1, 0” at regular time intervals in accordance with a signal obtained by inverting the sign of a sine every π / 2 radians ,... ”And a -SIN signal generating means for outputting a quadrature local oscillation signal (hereinafter, referred to as a" -SIN signal ") which is a data sequence that changes.
[0007]
Next, the operation of the quadrature demodulation circuit of the conventional interference wave removing apparatus shown in FIG. 3 will be described. First, the IF signal converting means 1 converts the received signal into an IF signal having a frequency of 1/4 of the sampling frequency. A / D converter 2 A / D converts the IF signal and outputs it.
[0008]
On the other hand, the COS signal generation means and the -SIN signal generation means of the local oscillation signal generation means 3 output the COS signal and the -SIN signal as local oscillation signals, respectively, and the quasi-synchronous detection means 4 outputs the local oscillation signal. To perform quasi-synchronous detection on the signal output from the A / D conversion means 2 to generate and output a complex baseband signal.
[0009]
Then, the complex carrier signal extracting means 5 extracts and outputs a complex carrier signal using the complex limiter and the narrow band LPF, and the correcting means 6 uses the complex carrier signal input from the complex carrier signal extracting means 5. The frequency and phase of the complex baseband signal input from the quasi-synchronous detection means 4 are corrected, and a complex baseband signal subjected to perfect orthogonal synchronous detection is output.
[0010]
[Problems to be solved by the invention]
However, in the above-described conventional quadrature demodulation circuit, the IF signal conversion means is an analog circuit, and the frequency of the IF signal may fluctuate or the frequency of the IF signal may be shifted due to interference waves.
Therefore, when trying to narrow the bandwidth of the narrow band LPF in order to increase the accuracy of the complex carrier signal extracting means, the signal of the frequency to be passed is shifted from the original position due to fluctuations or the like, so that the image to be passed is Since the carrier signal is attenuated without passing through, and the demodulated video signal is distorted, the bandwidth of the narrow band LPF cannot be narrowed.
If an LPF having an extremely narrow pass band width is used, the scale of the hardware of the narrow band LPF becomes large, and it becomes impossible to reduce the circuit scale, which is an advantage of the interference wave removing apparatus by digital processing. Anyway, it is difficult to extremely narrow the bandwidth of the narrow-band LPF.
[0011]
Therefore, when an interference wave having a frequency close to the video carrier frequency arrives, the interference wave is mixed into the reproduced carrier signal, and there has been a problem that a highly accurate carrier signal cannot be reproduced.
[0012]
Further, when a modulated wave modulated by a video signal of a picture including a white portion having a large area is received, due to overmodulation or multipath distortion, the carrier component disappears, or the intensity of the carrier component decreases, There is a problem that the accuracy of the reproduced carrier signal is deteriorated.
[0013]
As described above, the conventional interference wave removing apparatus using the quadrature demodulation circuit cannot improve the accuracy of the reproduced carrier signal, and detects the interference wave from the perfect synchronous detection signal generated based on the deteriorated reproduced carrier signal. Therefore, interference waves cannot be accurately removed, and at the same time, the output video signal is distorted.
[0014]
The present invention has been made in view of the above circumstances, and provides a carrier synchronization circuit and a quadrature demodulation circuit capable of obtaining a reproduced carrier signal with high accuracy even in a poor interference environment. With the goal.
[0016]
[Means for Solving the Problems]
Claims for solving the problems of the conventional example1The described invention is a carrier synchronization circuit, which receives a complex baseband signal, receives a complex baseband signal, and makes the amplitude of the complex baseband signal constant, and a carrier signal from the complex baseband signal output by the complex limiter circuit. A narrow-band low-pass filter circuit that extracts the signal, and locks the phase of the carrier signal output from the narrow-band low-pass filter circuit, and continuously reproduces the carrier signal with the locked phase.As a carrier signal to correct the frequency phase error of the complex baseband signal obtained by quasi-synchronous detectionAnd a digital PLL circuit for outputting the signal, and can generate a stable and accurate reproduced carrier signal.
[0017]
Claims for solving the problems of the conventional example2In the carrier synchronization circuit, a second LPF circuit that receives a complex baseband signal and limits a band in a carrier synchronization circuit, and sets a sampling frequency of the band-limited complex baseband signal to a color subcarrier of an NTSC signal A second down-sampling circuit for converting to a frequency, a complex limiter circuit for controlling the amplitude of a signal output from the second down-sampling circuit to be constant, and a video carrier for a signal output by the complex limiter circuit A narrow-band low-pass filter circuit for extracting a component as a carrier signal; and a digital PLL for locking the phase of the carrier signal output from the narrow-band low-pass filter circuit and continuously reproducing and outputting the carrier signal with the locked phase. Circuit and a carrier signal input from the digital PLL circuit. , And a fourth LPF circuit that interpolates the carrier signal whose sampling frequency has been increased by the interpolation and outputs it as a reproduced carrier signal, A stable and high-accuracy reproduced carrier signal can be generated.
[0018]
Claims for solving the problems of the above conventional example3The invention described in the claims1Or claims2In the carrier synchronization circuit described above, the digital PLL circuit is a digital PLL circuit that outputs a frequency error signal representing a difference between a video carrier frequency of the intermediate frequency signal and twice the frequency of the color subcarrier frequency of the NTSC signal, A loop filter circuit that removes a high-frequency component from a frequency error signal output by the digital PLL circuit; and a voltage-controlled oscillator that outputs a local oscillation signal used to generate an intermediate frequency signal based on a signal output by the loop filter circuit. This makes it possible to stably generate a highly accurate reproduction carrier signal and stabilize the frequency of the IF signal.
[0019]
Claims for solving the problems of the conventional example4The invention described in the claims1Or claims2Or claims3In the carrier synchronization circuit described above, the digital PLL circuit includes a phase comparison unit, an integration unit, and an oscillation unit, and the phase comparison unit determines a phase of the input complex carrier signal and a phase of the reproduced complex carrier signal. A phase difference from the phase is output as a phase error signal, and when the amplitude of the input complex carrier signal becomes smaller than a predetermined value, the phase error signal is forced to have no phase difference. Phase comparing means for outputting as zero data representing the phase error signal, wherein the integrating means is an integrating means for generating and outputting a signal for controlling the oscillating means from the phase error signal, and wherein the oscillating means includes an output from the integrating means. The phase of the complex carrier signal is generated based on the received signal, the complex carrier signal is reproduced from the phase and output, and the reproduced complex carrier signal is generated. It is characterized by a digital PLL circuit which is an oscillating means for returning the phase of the signal to the phase comparing means and outputting it, and can generate a stable and accurate reproduced carrier signal.
[0020]
Claims for solving the problems of the conventional example5The invention described in the claims4In the carrier synchronization circuit described in the above, the phase comparison means calculates an arc tangent as a phase of the input complex carrier signal, a phase of the complex carrier signal reproduced by the oscillation means, and the calculated arc tangent. And a first ± π conversion circuit for converting the phase error signal into a value from −π to π, and a zero signal as a signal indicating that there is no phase difference. A zero data circuit that outputs data, an absolute value circuit that calculates and outputs an absolute value of an input complex carrier signal, and an absolute value output by the absolute value circuit determines whether the carrier signal has previously disappeared. Threshold circuit that determines whether or not the level of the input complex carrier signal is a sufficient level based on whether or not a threshold value set as a level for discriminating is inputted. If the first threshold circuit determines that the carrier signal is at a sufficient level, the first threshold circuit outputs a phase error signal output by the first ± π conversion circuit, and outputs the first threshold circuit. However, when it is determined that the carrier signal is not at a sufficient level, the phase comparison means has a first selector circuit that outputs a signal output by the zero data circuit, As a result, a highly accurate reproduced carrier signal can be generated.
[0021]
Claims for solving the problems of the conventional example6The invention described in the claims4Or claims5In the carrier synchronous circuit described above, the oscillation means is a numerically controlled oscillator circuit including a third adder, a second ± π conversion circuit, a second latch circuit, a COS circuit, and a SIN circuit. The third adder is a third adder that adds a control signal input from an integrating means and a signal output by the second latch circuit and outputs the result, and the second ± π The second adder circuit converts the signal output from the third adder to a value between -π and π, and the second latch circuit converts the second ± π A second latch circuit that latches and outputs a signal output by the circuit, wherein the COS circuit is a COS circuit that outputs a cosine of a signal output by the second latch circuit, and the SIN circuit is SIN circuit that outputs the sine of the signal output by the second latch circuit Are characterized, can be stably generate high reproduction carrier signal accuracy.
[0022]
Claims for solving the problems of the conventional example7The invention described in the claims4Or claims5Or claims6In the carrier synchronizing circuit described above, the integrating means includes, in a signal output by the phase comparing means, a direct term coefficient at the time of pull-in, a direct term coefficient at the time of holding, an integral term coefficient at the time of pull-in, and an integral term at the time of holding. The first to fourth fixed value multiplication circuits each multiplying by a coefficient, and the detected phase error signal output by the phase comparison means are preset as errors after the pull-in is completed and the holding operation is to be performed. A second threshold circuit for determining whether or not the pull-in is completed based on whether or not the threshold value is exceeded; and a second fixed value when the second threshold circuit determines that the pull-in is completed. A second selector for outputting a signal output from the first fixed-value multiplier when outputting a signal output from the multiplier and determining that the second threshold circuit has not completed the pull-in; When it is determined that the circuit and the second threshold circuit have completed the pulling, a signal output from the fourth fixed value multiplying circuit is output, and it is determined that the second threshold circuit has not completed the pulling. In this case, a third selector circuit that outputs a signal output by the third fixed value multiplication circuit, an integration circuit that integrates a signal output by the third selector circuit, and an output signal that is output by the second selector circuit And a second adder for adding a signal to be integrated with the signal integrated by the integration circuit and outputting the added signal as a control signal, thereby generating a stable and accurate reproduced carrier signal. it can.
[0023]
Claims for solving the problems of the conventional example8The invention described in the claims7The carrier synchronizing circuit described above, wherein the integrating means is an integrating means having a D / A conversion circuit for converting a signal output from the integrating circuit into an analog signal and outputting the analog signal as a frequency error signal. If the error signal is used as a signal for controlling a local oscillation signal used for reproducing the IF signal, the frequency of the IF signal can be stabilized.
[0024]
Claims for solving the problems of the conventional example9The invention described in the claims3Or claims8In the carrier synchronous circuit described above, a loop filter circuit for removing a high frequency component of a frequency error signal output from a digital PLL circuit, and a local oscillator for generating an IF signal based on the signal output from the loop filter circuit A voltage-controlled oscillator for generating and outputting a signal, whereby the frequency of the IF signal can be stabilized.
[0025]
Claim 1 for solving the problem of the conventional example.0The invention described in the above is a multiplier that performs frequency conversion by multiplying a local oscillation signal and an RF signal input from a TV tuner or the like in a quadrature demodulation circuit, and an unnecessary component such as an image signal generated by the frequency conversion in the multiplier. , A band-pass filter circuit that outputs the analog IF signal as an analog IF signal, an A / D conversion circuit that converts the analog IF signal output by the band-pass filter circuit into a digital IF signal, and the A / D converter A step Nyquist filter circuit for attenuating signal components in a double sideband region in an NTSC modulated wave of a signal output from the circuit, and a quasi-synchronous detection for quasi-synchronous detection of a signal output from the step Nyquist filter circuit and outputting a complex baseband signal A detection circuit for removing an image component generated by the quasi-synchronous detection from the complex baseband signal 1 low-pass filter circuit, a first down-sampling circuit for converting a sampling frequency of a signal output from the first low-pass filter circuit, and a delay for delaying a signal output from the first down-sampling circuit for a predetermined time. A circuit for reproducing a carrier signal from the complex baseband signal and outputting the reproduced carrier signal.9And a phase rotation circuit that corrects a frequency phase error of a signal output from the delay circuit based on a reproduced carrier signal output from the carrier synchronization circuit, and outputs a signal that is completely synchronously detected. And a stable complex baseband signal can be output.
[0026]
Claim 1 for solving the problem of the conventional example.1According to the invention described above, an interference wave removing apparatus is provided.0The method is characterized in that interference waves are detected and removed based on the signals output by the described quadrature demodulation circuit, and the interference waves can be accurately removed.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
The carrier synchronization circuit according to the embodiment of the present invention reproduces a complex carrier signal having an in-phase component and a quadrature component (hereinafter, abbreviated as a “carrier signal”). The amplitude of the carrier signal is made constant by a complex limiter circuit, the component of the carrier signal is extracted by a narrow band low-pass filter circuit, and the carrier signal locked to the phase of the carrier signal is reproduced by a digital PLL circuit. The accuracy is improved, and even if the level of the extracted carrier signal is attenuated or lost, the carrier signal can be output stably and stably due to the characteristics of the PLL circuit.
[0028]
Further, the quadrature demodulation circuit according to the embodiment of the present invention using such a carrier synchronization circuit corrects a frequency phase error of a complex baseband signal obtained by quasi-synchronous detection based on a stable carrier signal, and A complex baseband signal obtained by quadrature synchronous detection is obtained and output, and a stable complex baseband signal can be output.
[0029]
Further, the interference wave removing device according to the embodiment of the present invention using such a quadrature demodulation circuit detects and removes the interference wave based on the stable complex baseband signal, so that the interference wave can be accurately removed. In addition, a demodulated signal with little distortion can be obtained.
[0030]
A quadrature demodulation circuit according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of a quadrature demodulation circuit according to an embodiment of the present invention.
As shown in FIG. 1, the quadrature demodulation circuit according to the embodiment of the present invention includes a multiplier 11 as means for multiplying a local oscillation signal and an RF signal input from a TV tuner or the like to perform frequency conversion, A BPF circuit 12 as a means for removing unnecessary components such as an image signal generated by frequency conversion, an A / D conversion circuit 13 as a means for converting an analog IF signal into a digital IF signal, and a step Nyquist filter circuit 14. , A COS signal and a −SIN signal as local oscillation signals, perform quasi-synchronous detection, divide into in-phase components and quadrature components, and output a complex baseband signal. An image component generated due to quasi-synchronous detection is removed from the complex baseband signal of the corresponding component, which is provided corresponding to the in-phase component and the quadrature component of the band signal. Two first LPF circuits 16a and 16b, and a first down-sampling circuit provided corresponding to each of the first LPF circuits 16a and 16b and converting the sampling frequency of each signal. 17a and 17b, and delay circuits 18a and 18b as means for delaying each signal for a fixed time, provided corresponding to the first down-sampling circuits 17a and 17b. And a phase rotation circuit 19 as means for outputting a completely synchronously detected signal, reproduces a carrier signal, outputs the reproduced carrier signal into an in-phase component and a quadrature component, and generates an IF signal. And a carrier synchronizing circuit 20 as means for outputting a local oscillation signal for performing the operation.
[0031]
Further, as shown in FIG. 1, the carrier synchronization circuit 20 is provided corresponding to each of the in-phase component and the quadrature component when the sampling frequency is converted later, and no aliasing distortion occurs in each corresponding signal. As described above, the second LPF circuits 21a and 21b as means for performing band limitation and the second LPF circuits 21a and 21b are provided in correspondence with the second LPF circuits 21a and 21b, and serve as means for converting a sampling frequency into a color subcarrier frequency of an NTSC signal. A second down-sampling circuit 22a, 22b, a complex limiter circuit 23 as means for processing the amplitude, that is, an absolute value of the complex baseband signal output from the second down-sampling circuit 22a, 22b to be constant; It is provided corresponding to each signal of the in-phase component and the quadrature component output by the limiter circuit 23, and the signal other than the video carrier component of each corresponding signal The third LPF circuits (narrow band low-pass filter circuits) 24a and 24b as means for removing the components and the phases of the signals (complex carrier signals) output from the third LPF circuits 24a and 24b are locked, and By continuously reproducing and outputting the complex carrier signal, the accuracy of the carrier signal is improved, and even when the amplitude of the complex carrier signal is small, the stable complex carrier signal is free-running and reproduced, and is output. A digital PLL circuit 25 as a means for outputting a signal representing a difference between the video carrier frequency of the IF signal and twice the frequency of the color subcarrier frequency of the NTSC signal as a frequency error signal, and input from the digital PLL circuit 25 The up-sampling circuit 26a, which raises the sampling frequency by interpolating the signal of “0” into each of the in-phase component and the quadrature component signals, 6b, fourth LPF circuits 27a and 27b provided as means for interpolating and reproducing each signal whose sampling frequency has been increased by interpolation, and outputting the carrier signal, and a digital PLL circuit A loop filter circuit as means for removing high-frequency components from the frequency error signal output by the loop filter 25; and a local oscillation signal used by the multiplier 11 to generate an IF signal based on the signal output by the loop filter circuit. And a VCO 29 as output means.
[0032]
Hereinafter, each part will be specifically described.
The multiplier 11 multiplies a local oscillation signal input from the carrier synchronization circuit 20 by an RF signal input from a TV tuner or the like (a signal obtained by amplifying a signal containing an interference wave to a predetermined level, input from an antenna). Then, the RF signal is frequency-converted. For example, ideally, the RF signal is converted into an IF signal of 7.15809 MHz, which is a quarter of the sampling frequency of 28.63636 MHz, and output. Here, 28.63636 MHz is eight times the color subcarrier frequency of the NTSC signal, and therefore, 7.15809 MHz is twice the frequency of the color subcarrier frequency of the NTSC signal.
[0033]
The BPF circuit 12 removes an image component generated by the frequency conversion and an unnecessary band component from the IF signal input from the multiplier 11 and outputs the result.
The A / D conversion circuit 13 converts the signal input from the BPF circuit 12 into a digital signal at a clock frequency of, for example, 28.63636 MHz (eight times the color subcarrier frequency of the NTSC signal), and converts the signal into a digital IF signal. Output.
[0034]
Since the NTSC signal is a vestigial sideband signal, the step Nyquist filter circuit 14 considers that the video signal will be distorted if detected as it is, and takes into account frequencies near the video carrier frequency (± 1.25 MHz). That is, the signal in the double sideband (DSB) area is attenuated by about 6 dB as compared with the signal component in the SSB (SingleSideBand) area.
[0035]
The quasi-synchronous detection circuit 15 quasi-synchronously detects the signal output from the step Nyquist filter 14 using the COS signal and the −SIN signal as local oscillation signals, and generates a complex baseband signal having each of an in-phase component and a quadrature component. Is output.
[0036]
The first LPF circuit 16a removes an image component generated due to the quasi-synchronous detection from the in-phase component of the complex baseband signal output from the quasi-synchronous detection circuit 15, and the first LPF circuit 16b performs the quasi-synchronous detection. This is to remove an image component generated by the quasi-synchronous detection from the quadrature component of the complex baseband signal output from the synchronous detection circuit 15.
[0037]
Each of the first down-sampling circuit 17a and the first down-sampling circuit 17b has a ratio of 2: 1 between the signal input from the first LPF circuit 16a and the signal input from the first LPF circuit 16b. Then, the sampling frequency is converted from 28.63636 MHz to 14.31818 MHz (half the frequency of the NTSC signal, which is four times the color subcarrier frequency).
[0038]
The delay circuit 18a and the delay circuit 18b delay the signals input from the first down-sampler 17a and the first down-sampler 17b, respectively, by a predetermined time. Is reproduced and output to the phase rotation circuit 19 so as to coincide with the timing of output to the phase rotation circuit 19.
[0039]
The phase rotation circuit 19 is based on a complex carrier signal having an in-phase component and a quadrature component which is reproduced and output by the carrier synchronization circuit 20, and based on a complex base having the in-phase component and the quadrature component input from the delay circuits 18a and 18b. It corrects the frequency phase error of the band signal and outputs it as an in-phase component and a quadrature component of the perfect synchronous detection output.
[0040]
The second LPF circuit 21a and the second LPF circuit 21b of the carrier synchronizing circuit 20 respectively convert the video input signals from the first down-sampling circuit 17a and the first down-sampling circuit 17b into video carrier signals. Only components in the vicinity of the frequency are taken out, band-limited so that aliasing distortion does not occur in the down-sampling circuit 22, and output.
[0041]
The second down-sampling circuit 22a and the second down-sampling circuit 22b respectively thin out the signals output from the second LPF circuit 21a and the second LPF circuit 21b to, for example, 4: 1 and perform sampling. The frequency is converted to 3.57954 MHz (the color subcarrier frequency of the NTSC signal) and output.
[0042]
The complex limiter circuit 23 processes the complex signals output from the second down-sampling circuits 22a and 22b so that the amplitude, that is, the absolute value of the complex signal becomes constant, and outputs a complex baseband signal having a constant amplitude.
As a specific configuration of the complex limiter circuit 23, a configuration as shown in "Complex carrier carrier limiter circuit" in JP-A-10-303999 can be considered.
[0043]
The third LPF circuit 24a and the third LPF circuit 24b are narrow-band low-pass filter circuits, and are provided corresponding to signals of the in-phase component and the quadrature component output from the complex limiter circuit 23, respectively. The components other than the video carrier component of each signal to be removed are output.
[0044]
The digital PLL circuit 25 increases the accuracy of the signals (complex carrier signals) of the in-phase component and the quadrature component output from the third LPF circuit 24a and the third LPF circuit 24b, and the amplitude of the complex carrier signal is increased. Even if it is small, it reproduces and outputs a stable carrier signal and outputs a signal representing the difference between the video carrier frequency of the IF signal and twice the frequency of the color subcarrier frequency of the NTSC signal as a frequency error signal. is there.
[0045]
That is, instead of narrowing the pass band of the third LPF circuit 24, the digital PLL circuit 25 increases the accuracy of the complex carrier signal output from the third LPF circuit 24 due to the characteristics of the PLL circuit. As a characteristic of the circuit, the complex carrier signal disappears due to overmodulation, multipath distortion, etc., or is attenuated due to the so-called flywheel effect, which runs for a certain period of time even if there is no signal input. It reproduces a stable carrier signal even if it is lost.
The specific configuration of the digital PLL circuit 25 will be described later.
[0046]
The up-sampling circuit 26a and the up-sampling circuit 26b respectively increase the sampling frequency by interpolating a signal of “0” into each of the in-phase component and the quadrature component signals input from the digital PLL circuit 25, and increase the sampling frequency, for example, by four Is converted to a frequency of 14.31818 MHz.
The fourth LPF circuit 27a and the fourth LPF circuit 27b interpolate signals input from the up-sampling circuits 26a and 26b, respectively, and output the signals as reproduced carrier signals.
[0047]
The loop filter circuit 28 removes high frequency components from the frequency error signal output from the digital PLL circuit 25.
The VCO 29 is a voltage-controlled oscillator, and outputs a local oscillation signal used to generate an IF signal based on a signal input from the loop filter 28.
It is preferable that the control of the VCO 29 is sufficiently slower than the response speed of the digital PLL circuit 25 so that the feedback control does not compete with each other. Otherwise, the VCO 29 is controlled before the digital PLL circuit 25 responds, and accurate control cannot be performed.
[0048]
Here, the configuration of the digital PLL circuit 25 will be described with reference to FIG. FIG. 2 is a configuration block diagram illustrating an example of the digital PLL circuit 25. The PLL circuit is generally composed of a phase comparing means, an integrating means, and an oscillating means. Here, referring to FIG. 2, an NCO (Numerically Controlled Oscillator) is used as the oscillating means. A digital signal processing type secondary Tan-DPLL circuit will be described.
The digital PLL circuit 25 may have another circuit configuration.
[0049]
The digital PLL circuit shown in FIG. 2 outputs the phase error of the input complex carrier signal and the phase error of the reproduced complex carrier signal as a phase error signal, and the amplitude of the input complex carrier signal becomes smaller than a certain value. At this time, based on the input complex carrier signal, a phase comparison means 71 for forcibly outputting the phase error signal as zero, and a video carrier frequency of an IF signal and a color Integrating means 72 for generating a frequency error signal indicating a difference from a frequency twice as high as the carrier frequency, and an NCO control signal as a signal for controlling the oscillation frequency of the NCO required for reproducing the carrier signal; 72 reproduces the value of the phase of the carrier signal based on the NCO control signal output from , Together with the divided and outputs the in-phase and quadrature components, and a NCO circuit (numerically controlled oscillator circuit) 73 for outputting a phase value of the reproduced carrier signal fed back to the phase comparator 71.
[0050]
As shown in FIG. 2, the phase comparing means 71 includes an arc tangent circuit 41 as means for calculating the phase of the complex carrier signal from the input complex carrier signals of the in-phase component and the quadrature component, and an NCO A subtractor 42 as means for calculating the difference (phase error signal) between the phase of the complex carrier signal reproduced by the circuit 73 and the calculated phase, and the phase error signal θ is calculated as θ = θ0 + 2πn (where n is A first ± π conversion circuit 43 as a means for converting into a value of θ0 (−π <θ0 <π) that becomes an integer, and a means for outputting zero data as a signal representing a value of “0” A zero data circuit 44, an absolute value circuit 45 as a means for calculating and outputting the absolute value of the input complex carrier signal having an in-phase component and a quadrature component, and an absolute value output by the absolute value circuit 45, The carrier signal is turned off in advance. A first means as means for judging whether or not the level of the carrier signal has become a sufficient level by judging whether or not a threshold value set as a level for discriminating whether or not the carrier signal has been reached. When the threshold circuit 46 and the first threshold circuit 46 determine that the carrier signal is at a sufficient level, the phase error signal θ0 output from the first ± π conversion circuit 43 is integrated by the integrating means 72. , And otherwise, a first selector circuit 47 as means for selectively outputting a signal representing “0” output from the zero data circuit 44 to the integrating means 72.
[0051]
Further, the integrating means 72 adds, to the signal output by the phase comparing means 71, a direct term coefficient α1 at the time of pull-in, a direct term coefficient α2 at the time of holding, an integral term coefficient β1 at the time of pulling, and an integral term coefficient β1 at the time of holding The first to fourth fixed value multiplying circuits 48a to 48d as means for multiplying .beta.2 and the phase error signal .theta.0 output from the first. ± ..pi. A second threshold circuit 49 as means for judging whether or not a threshold value set as an error for performing the holding operation is exceeded and judging whether or not the pull-in operation is completed; 2 when it is determined that the threshold circuit 49 has completed the pull-in, the signal output from the second fixed-value multiplying circuit 48b that multiplies the direct term coefficient α2 at the time of holding is selectively output. Directly When it is determined that the second selector circuit 50a as means for selectively outputting a signal output from the first fixed value multiplication circuit 48a for multiplying the term coefficient α1 and the second threshold circuit 49 have completed the pull-in operation , A signal output from the fourth fixed value multiplying circuit 48d for multiplying by the integral term coefficient β2 at the time of holding, and otherwise, a third fixed value multiplication for multiplying by the integral term coefficient β1 at the time of pull-in. A third selector circuit 50b as means for selectively outputting a signal output from the circuit 48c, a first adder 51 and a clip circuit 52 as means for integrating the signal output from the third selector circuit 50b And a latch circuit 53 (in the claims, the first adder 51, the clip circuit 52, and the latch circuit 53 are collectively referred to as an "integrator circuit"), and a second selector circuit 50. The second adder 54 as a means for adding the signal output from the latch circuit 53 and the signal output from the latch circuit 53 and outputting the signal as a signal (NCO control signal) necessary for reproducing the carrier signal, and the latch circuit 53 The D / A converter 55 converts an output signal into an analog signal and outputs the analog signal as a frequency error signal.
[0052]
Further, the NCO circuit 73 performs integration while maintaining the signal output by the second adder 54 of the integration means 72 in the range of -π to π, and outputs a signal corresponding to the phase of the carrier signal. The third adder 56, the second ± π converting circuit 57, the second latch circuit 58, and the in-phase component of the carrier signal are reproduced from the signal output from the latch circuit 58 and corresponding to the phase of the carrier signal. Similarly, a COS circuit 59 for outputting a signal and a SIN circuit 60 for reproducing and outputting the orthogonal component of the carrier signal from a signal corresponding to the phase of the carrier signal are provided.
[0053]
The respective components will be specifically described below. The arc tangent circuit 41 of the phase comparison means 71 calculates the arc tangent of the complex carrier signal from the input complex carrier signal having the in-phase component and the quadrature component, and Is output as
The arc tangent circuit 41 can be realized by using, for example, a ROM (read-only memory) in which arc tangent values corresponding to respective components of the complex carrier signal are stored in advance.
[0054]
The subtracter 42 calculates the difference between the phase signal output from the arctangent circuit 41 and the signal representing the phase of the reproduced carrier signal input from the NCO circuit 73 and outputs the result as a phase error signal. .
[0055]
The first ± π conversion circuit 43 converts the phase error signal θ output from the subtractor 42 into θ0 (−π <θ0 <π) such that θ = θ0 + 2πn (where n is an integer). is there. For example, the tangent value is a value that periodically repeats a value corresponding to -π to π, and thus utilizes such a property.
[0056]
The zero data circuit 44 outputs a value (zero data) to be output by the first ± π conversion circuit 43 when θ0 = 0.
That is, the zero data is a phase error signal indicating that the phase error is “0”.
[0057]
The absolute value circuit 45 multiplies the amplitude absolute value of the carrier signal, that is, the carrier signal by its complex conjugate, from the signals of the in-phase component and the quadrature component of the input carrier signal, and further obtains the square root. A signal representing the result is output.
[0058]
The first threshold circuit 46 determines whether the amplitude absolute value calculated by the absolute value circuit 45 exceeds a threshold value set in advance to determine whether the carrier signal has a sufficient amplitude. And outputs a signal representing the result of the determination.
[0059]
When the first selector circuit 47 determines that the carrier signal has a sufficient amplitude according to the signal input from the first threshold circuit 46, the first ± π conversion circuit 43 outputs The signal to be output is selectively output to the integration means 72, and otherwise, the signal output from the zero data circuit 44 is selectively output to the integration means 72.
[0060]
That is, the phase comparing means 71 distributes and inputs the in-phase component and the quadrature component of the input complex carrier signal to the arctangent circuit 41 and the absolute value circuit 45, and the arctangent circuit 41 generates the phase signal. The absolute value circuit 45 outputs a signal representing the amplitude absolute value of the complex carrier signal, and the subtracter 42 outputs the phase signal output from the arctangent circuit 41 and the phase of the reproduced carrier signal output from the NCO circuit 73. The difference from the signal is calculated as a phase error signal, and the first ± π conversion circuit 43 outputs the phase error signal (referred to as “detected phase error signal” in the claims) as a value from −π to π. .
[0061]
On the other hand, the first threshold circuit 46 determines whether or not the amplitude of the input complex carrier signal is sufficient according to the signal indicating the amplitude absolute value output from the absolute value circuit 45, and determines that the amplitude is sufficient. In this case, the first selector circuit 47 selectively outputs the phase error signal input from the first ± π converting circuit 43, and the first threshold circuit 46 outputs the amplitude of the input complex carrier signal. Is not sufficient, the first selector circuit 47 outputs the zero data (the phase error signal indicating that the phase error is “0”) output from the zero data circuit 44. Become.
[0062]
When the amplitude absolute value of the input complex carrier signal becomes extremely small, the accuracy of the phase signal obtained from the complex carrier signal becomes worse, and the accuracy of the reproduced complex carrier signal is considered to deteriorate. When the input complex carrier signal disappears for a certain period of time due to overmodulation or the like, it is conceivable that a normal complex carrier signal cannot be continuously reproduced. According to such a phase comparison unit 71, When the amplitude absolute value of the input complex carrier signal becomes smaller than a preset value, the phase error signal is forcibly set to zero, the state of the digital PLL circuit is maintained, and the NCO can be continuously oscillated. is there.
[0063]
The first to fourth fixed value multiplying circuits 48a to 48d respectively add the direct term coefficient α1 at the time of pull-in to the phase error output from the selector circuit 47 of the phase comparing means 71. And the direct term coefficient α2 at the time of holding, the integral term coefficient β1 at the time of pull-in, and the integral term coefficient β2 at the time of holding.
[0064]
Thus, an NCO control required to generate a frequency error signal (a part of βΣxi) and a reproduced carrier signal by calculating a mathematical expression such as γi = αxi + βΣxi (where x is a signal output from the selector circuit 47). And a signal γ. Note that Σ is an addition for i.
[0065]
The second threshold circuit 49 is set in advance to determine whether or not the pull-in operation has been completed based on the phase error signal output from the first ± π conversion circuit 43 of the phase comparison means 71. The threshold value is compared with the phase error signal output from the first ± π conversion circuit 43, and when the phase error signal output from the first ± π conversion circuit 43 exceeds the threshold value, the pull-in is performed. It determines that the operation has not been completed and outputs a signal indicating that the pull-in operation has not been completed to the second selector circuit 50a and the third selector circuit 50b.
When the phase error signal output from the first ± π conversion circuit 43 does not exceed the threshold value, the second threshold circuit 49 determines that the pull-in operation has been completed, and completes the pull-in operation. That is, a signal indicating the fact is output to the second selector circuit 50a and the third selector circuit 50b.
[0066]
Here, the second threshold circuit 49 compares and determines a value obtained by averaging the absolute value of the input signal for a certain period in order to prevent so-called hunting, which continuously outputs electric vibration. It is preferred to do so.
[0067]
The second selector circuit 50a receives a signal indicating that the pull-in operation has been completed from the second threshold circuit 49, and selectively selects a signal output from the second fixed value multiplying circuit 48b as a second signal. This is output to the adder 54.
Further, the second selector circuit 50a selectively receives a signal indicating that the pull-in operation has not been completed from the second threshold circuit 49 and selectively outputs a signal output from the first fixed-value multiplication circuit 48a. Is output to the second adder 54.
[0068]
The third selector circuit 50b receives the signal indicating that the pull-in operation has been completed from the second threshold circuit 49, and selectively selects the signal output from the fourth fixed value multiplying circuit 48d as the first signal. This is output to the adder 51.
Further, the third selector circuit 50b receives an input of a signal indicating that the pull-in operation has not been completed from the second threshold circuit 49, and selectively selects a signal output from the third fixed-value multiplication circuit 48c. To the first adder 51.
[0069]
The first adder 51 adds the signal input from the third selector 50 b and the signal input from the latch circuit 53 by feedback, and outputs the result to the clip circuit 52.
The clip circuit 52 performs a so-called overflow process and an underflow process so that a signal input from the first adder 51 does not exceed a size that the first latch circuit 53 can hold. is there.
[0070]
The first latch circuit 53 temporarily stores (latches) the signal input from the clip circuit 52, feeds it back to the first adder 51, and outputs it to the second adder 54. , And also to the D / A conversion circuit 55.
Therefore, the first adder 51, the clipping circuit 52, and the first latch circuit 53 perform addition as a whole and perform integration.
[0071]
The second adder 54 adds the signal input from the second selector circuit 50a and the signal input from the latch circuit 53 and outputs the result to the NCO circuit 73.
Further, in a state where the digital PLL circuit is sufficiently synchronized (a state in which the pull-in is completed), the value held and output by the first latch circuit 53 is based on the base of the complex carrier signal input to the digital PLL circuit. Is proportional to the frequency error of the IF signal.
Thus, the D / A conversion circuit 55 converts the signal output from the first latch circuit 53 into an analog signal and outputs the analog signal as a frequency error signal.
[0072]
That is, the integrator 72 adds the direct term coefficient α1 at the time of pull-in to the phase error signal output from the first selector circuit 47 of the phase comparator 71 by the first to fourth fixed value multiplying circuits 48a to 48d, respectively. Multiplied by the direct term coefficient α2 at the time of holding, the integral term coefficient β1 at the time of pull-in, and the integral term coefficient β2 at the time of holding, and based on the phase error signal input from the first ± π conversion circuit 43, It is determined whether or not the second threshold circuit 49 has completed the pull-in operation, and if it is determined that the pull-in operation has been completed, the second selector circuit 50a and the third selector circuit 50b respectively perform the second and third selector circuits 50a and 50b. The signals output from the fixed value multiplication circuit 48b and the fourth fixed value multiplication circuit 48d are selectively output to the second adder 54 and the first adder 51, respectively. Pulls in When it is determined that the operation has not been completed, the second selector circuit 50a and the third selector circuit 50b output the first fixed value multiplier circuit 48a and the third fixed value multiplier circuit 48c, respectively. The signals are selectively output to the second adder 54 and the first adder 51, respectively.
[0073]
On the other hand, the first adder 51, the clip circuit 52, and the first latch circuit 53 integrate and output a signal input from the third selector circuit 50b, and the second adder 54 The signal input from the selector circuit 50a and the result of the integration are added and output to the NCO circuit 73, and the D / A conversion circuit 55 converts the signal input from the first latch circuit 53 into an analog signal. And output as a frequency error signal.
[0074]
According to such an integrating means 72, the signal output from the D / A conversion circuit 55 is used as a signal for controlling the frequency of the local oscillation signal used when converting the frequency of the RF signal into the IF signal, thereby obtaining the IF signal. The video carrier frequency of the signal can be precisely synchronized to an integer fraction of the sampling frequency, and the return of the harmonic component due to the quantization is made to match the video carrier frequency, thereby preventing the occurrence of flicker and beat. is there.
[0075]
The third adder 56 adds the signal output from the second adder 54 and the signal output from the second latch circuit 58 and outputs the result.
The second ± π converting circuit 57 converts the signal φ output from the third adder 56 into φ0 (−π <φ0 <π) such that φ = φ0 + 2πn (where n is an integer). Output.
[0076]
The second latch circuit 58 latches the signal output from the second ± π conversion circuit 57, feeds it back to the third adder 56 and outputs it, and sends it to the subtracter 42 of the phase comparison means 71. Is also output.
Further, the second latch circuit 58 outputs the latched signal as a phase value to the COS circuit 59 and the SIN circuit 60.
[0077]
The COS circuit 59 generates a signal corresponding to the cosine of the phase value input from the second latch circuit 58 and outputs the signal as an in-phase component of the reproduced carrier signal. The SIN circuit 60 generates a signal corresponding to the sine of the phase value input from the second latch circuit 58 and outputs the signal as a quadrature component of the reproduced carrier signal.
The COS circuit 59 and the SIN circuit 60 can be realized by a ROM or the like, like the arc tangent circuit 41.
[0078]
That is, the NCO circuit 73 integrates the signal output from the second adder 54 of the integrating means 72 by the third adder 56, the second ± π conversion circuit 58, and the second latch circuit 58, and The feedback operation is performed so that the phase error signal output from the comparing means 71 converges to zero.
The COS circuit 59 and the SIN circuit 60 output the in-phase component and the quadrature component of the reproduced carrier signal based on the result of the integration.
[0079]
Such a feedback operation of the NCO 73 has an effect that a reproduced carrier signal can be generated stably.
[0080]
As a whole, according to the digital PLL circuit as shown in FIG. 2, the accuracy of the carrier signal to be reproduced can be improved, and even if the amplitude of the input carrier signal is reduced or disappears, the reproduction can be performed. There is an effect that the carrier signal can be continuously output.
Therefore, according to the carrier synchronization circuit 20 having such a digital PLL circuit shown in FIG. 1, there is an effect that a highly accurate reproduced carrier signal can be continuously output.
[0081]
Next, the operation of the digital quadrature demodulation circuit shown in FIG. 1 will be described.
The received signal including the interference wave input from the antenna is amplified to an appropriate level and input to the multiplier 11 as an RF signal.
Then, the multiplier 11 multiplies the local oscillation signal input from the VCO 29 of the carrier synchronization circuit 20 by the RF signal and outputs the resulting signal. The BPF circuit 12 causes the image component generated by the frequency conversion in the multiplier 11 to generate an unnecessary component. The band component is removed and the result is output as an IF signal.
[0082]
Here, for example, if the sampling frequency of the IF signal is 28.63636 MHz (eight times the color subcarrier frequency of the NTSC signal), the video carrier frequency is 7.15809 MHz (the color of the NTSC signal is １ ／ of the sampling frequency). (2 times the sub-carrier frequency).
[0083]
The A / D conversion circuit 13 converts the analog IF signal into a digital IF signal at a clock frequency of, for example, 28.63636 MHz, and the step Nyquist filter circuit 4 corresponds to a double sideband signal of the NTSC modulated wave. The signal component in the frequency region of the video carrier frequency ± 1.25 MHz is reduced by 6 dB as compared with the signal component in the SSB region.
[0084]
Then, the quasi-synchronous detection circuit 15 quadrature-demodulates the signal input from the step Nyquist filter circuit 14 as a COS signal and the −SIN signal as a local oscillation signal, generates a complex baseband signal, and generates an in-phase component thereof. These are output separately for the orthogonal components.
Then, for each component of the complex baseband signal, the corresponding first LPF circuit 16 removes the image component generated along with the quadrature demodulation, and the corresponding first down-sampling circuit 17 sets the sampling frequency to, for example, It is converted to 14.31818 MHz (four times the color subcarrier frequency of the NTSC signal) and dropped, and further delayed by the corresponding delay circuit 18 by the delay generated when the carrier synchronization circuit 20 generates a reproduced carrier signal. Then, it is output to the phase rotation circuit 19.
[0085]
On the other hand, as for each component of the signal output from the down-sampling circuit 17, only the component near the video carrier frequency is taken out by the corresponding second LPF circuit 21, and aliasing distortion does not occur in the next down-sampling process. The complex limiter circuit 23 converts the band into a baseband signal having a constant amplitude.
[0086]
The components of the complex baseband signal, which have been converted to the constant amplitude, are further removed by the corresponding third LPF circuits 24 from the components other than the video carrier component, and are output as carrier signals.
The carrier signal is output as a continuous and stable reproduced carrier signal by the operation of the digital PLL circuit 25. The signals of the in-phase component and the quadrature component of the reproduced carrier signal are respectively converted into corresponding up-sampled signals. The signal "0" is interpolated by the circuit 26, converted to a sampling frequency of, for example, 14.31818 MHz, which is four times, and output, and further interpolated and reproduced by the corresponding fourth LPF circuit 27. The signal is output to the phase rotation circuit 19 as a carrier signal.
[0087]
Then, the phase rotation circuit 19 converts the frequency phase error of each of the in-phase component and the quadrature component of the complex baseband signal output from the delay circuit 18 by the signal of the in-phase component and the quadrature component of the reproduced carrier signal. Then, the in-phase component and the quadrature component of the complex baseband signal which has been corrected and completely synchronously detected are output.
[0088]
On the other hand, the frequency error signal (information relating to the difference between the video carrier frequency of the IF signal and 7.15809 MHz (twice the color subcarrier frequency of the NTSC signal)) output from the digital PLL circuit 25 is output by the loop filter circuit 28. After removing the high frequency, the signal is output to the VCO 29 as a control signal, and the local oscillation signal output from the VCO 29 is adjusted so that the frequency of the IF signal is exactly 7.15809 MHz (twice the color subcarrier frequency of the NTSC signal). So that
[0089]
According to the digital quadrature demodulation circuit according to the embodiment of the present invention, even if an interference signal or the like is mixed in the RF signal and the carrier signal extracted from the RF signal is deteriorated or lost, the digital PLL circuit 25 and By the operation of the carrier synchronization circuit 20 using the same, a highly accurate and stable reproduced carrier signal can be continuously obtained, and the frequency phase error of the quasi-synchronous detected signal can be corrected. There is an effect that can be output.
[0090]
Further, as shown by the broken line in FIG. 1, after the digital quadrature demodulation circuit according to the embodiment of the present invention, each component of the in-phase component and the quadrature component of the fully synchronous detection signal output by the digital quadrature demodulation circuit is provided. Is subjected to complex FFT processing, the frequency and level of the interference wave are detected, and a cancellation circuit that adaptively cancels the interference wave component by a Hilbert transform / adaptive filter circuit or the like is provided, thereby providing an interference wave removal device. You can also.
According to such an interference wave removing device, since the interference wave is detected and removed based on the perfect synchronous detection signal generated based on the reproduced carrier signal with high accuracy, the interference wave can be accurately removed and the image quality is degraded. Thus, there is an effect that an output video signal with less noise can be obtained.
[0091]
Note that, in the digital quadrature demodulation circuit according to the embodiment of the present invention, a case has been described in which a complex carrier signal having an in-phase component and a quadrature component is used as a carrier signal. can do.
[0092]
【The invention's effect】
Claim1According to the described invention, the carrier signal is continuously reproduced by locking to the phase of the extracted carrier signal.Output as a carrier signal for correcting the frequency phase error of the complex baseband signal obtained by quasi-synchronous detection.Since the carrier synchronization circuit is used, it is possible to stably generate a highly accurate reproduced carrier signal.
[0093]
Claim2According to the described invention, the input complex baseband signal is band-limited in advance and then down-sampled, the amplitude is fixed by a complex limiter circuit, and the narrow-band low-pass filter circuit extracts a carrier signal. The digital PLL circuit receives the input of the carrier signal, locks to the phase of the carrier signal, continuously reproduces and outputs the carrier signal with the locked phase, and the up-sampling circuit outputs the digital PLL signal. A carrier synchronization circuit that interpolates a preset signal into a reproduced carrier signal output from the circuit, upsamples the signal, and further interpolates and outputs the signal using an LPF, generates a stable and accurate reproduced carrier signal. There is an effect that can be done.
[0094]
Claim3According to the described invention, the digital PLL circuit outputs a frequency error signal representing an error in the frequency of the carrier signal of the IF signal, the loop filter circuit removes a high-frequency component of the frequency error signal, and A voltage controlled oscillator outputs a local oscillation signal for generating an IF signal according to the output signal.1 or 2The carrier synchronization circuit described above has an effect of stably generating a high-precision reproduced carrier signal and an effect of stabilizing the frequency of an IF signal.
[0095]
Claim4-7According to the invention described above, the phase comparison means of the digital PLL circuit generates a phase difference between the input carrier signal and the reproduced carrier signal as a phase error signal, and is used when the intensity of the input carrier signal is not sufficient. Outputs a phase error signal as a signal indicating that there is no phase error, the integrator outputs a signal for controlling the oscillator based on the phase error signal, and the oscillator outputs the signal And reproducing and outputting the carrier signal according to the above, and the phase of the reproduced carrier signal is fed back to the phase comparing means and output.1Or claims2Or claims3Since the carrier synchronization circuit described above is used, there is an effect that a reproduced carrier signal with high accuracy can be generated stably.
[0096]
Claim8According to the present invention, the D / A conversion circuit of the integration means outputs a signal generated internally as a frequency error signal.7Since the carrier synchronization circuit described above is used, controlling the oscillator that generates the IF signal based on the frequency error signal has the effect of stabilizing the frequency of the IF signal.
[0097]
Claim9According to the described invention, the loop filter circuit removes a high frequency component of the frequency error signal output from the digital PLL circuit, and the voltage controlled oscillator generates an IF signal based on the signal output from the loop filter circuit. For generating and outputting a local oscillation signal for3Or claims8The carrier synchronization circuit described above has an effect that the frequency of the IF signal can be stabilized.
[0098]
Claim 10According to the described invention, the multiplier multiplies the local oscillation signal by the RF signal input from the TV tuner or the like to perform frequency conversion, and the bandpass filter circuit removes unnecessary components such as an image signal, The digital IF signal is output as an analog IF signal, the A / D converter converts the signal into a digital IF signal, and outputs the digital IF signal. After attenuating the signal component, the quasi-synchronous detection circuit quasi-synchronously detects the signal and outputs a complex baseband signal, and the first low-pass filter circuit generates the complex baseband signal from the complex baseband signal with quasi-synchronous detection The first down-sampling circuit converts the sampling frequency of the signal, and the delay circuit outputs the signal from the first down-sampling circuit. That while signal a predetermined time delay and output, according to claim 1 to claim9The described carrier synchronization circuit reproduces the carrier signal from the complex baseband signal and outputs the reproduced carrier signal, and the phase rotation circuit is output from the delay circuit based on the reproduced carrier signal output from the carrier synchronization circuit. A quadrature demodulation circuit for correcting a frequency phase error of a signal to be output and outputting a signal which is completely synchronously detected.9The demodulation of the IF signal can be performed based on the continuous and stable carrier signal output by the described carrier synchronization circuit, and there is an effect that a stable complex baseband signal can be output.
[0099]
Claim 11According to the described invention, claim 10Since the interference wave removal device detects and removes the interference wave based on the signal output by the described quadrature demodulation circuit, the interference wave can be removed based on the stable complex baseband signal, and the interference wave can be accurately removed. There is an effect that can be done.
[Brief description of the drawings]
FIG. 1 is a configuration block diagram of a quadrature demodulation circuit according to an embodiment of the present invention.
FIG. 2 is a configuration block diagram illustrating an example of a digital PLL circuit 25.
FIG. 3 is a configuration block diagram illustrating an example of a conventional orthogonal demodulation circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... IF signal conversion means, 2 ... A / D conversion means, 3 ... Local oscillation signal generation means, 4 ... Semi-synchronous detection means, 5 ... Complex carrier signal extraction means, 6 ... Correction means, 11 ... Multiplier, 12 ... BPF circuit, 13 A / D converter circuit, 14 step Nyquist filter circuit, 15 quasi-synchronous detection circuit, 16 first LPF circuit, 17 first down-sampling circuit, 18 delay circuit, 19 phase Rotation circuit, 20: carrier synchronization circuit, 21: second LPF circuit, 22: second downsampling circuit, 23: complex limiter circuit, 24: third LPF circuit, 25: digital PLL circuit, 26: upsampling Circuit, 27: fourth LPF circuit, 28, loop filter circuit, 29, VCO circuit, 41, arctangent circuit, 42, subtractor, 43, first ± π conversion Circuit 44, zero data circuit, 45, absolute value circuit, 46, first threshold circuit, 47, first selector circuit, 48, fixed value multiplying circuit, 49, second threshold circuit, 50a, second circuit Selector circuit, 50b third selector circuit, 51 first adder, 52 clip circuit, 53 first latch circuit, 54 second adder, 55 D / A conversion circuit, 56 ... 3rd adder, 57: second ± π conversion circuit, 58: second latch circuit, 59: COS circuit, 60: SIN circuit, 71: phase comparison means, 72: integration means, 73: NCO circuit

Claims (11)

A complex limiter circuit that receives an input of a complex baseband signal and makes the amplitude of the complex baseband signal constant, a narrowband low-pass filter circuit that extracts a carrier signal from the complex baseband signal output by the complex limiter circuit, Lock the phase of the carrier signal output from the narrowband low-pass filter circuit, continuously reproduce the carrier signal with the locked phase, and calculate the frequency phase error of the complex baseband signal obtained by quasi-synchronous detection. A digital PLL circuit that outputs a carrier signal for correction . A second LPF circuit that receives a complex baseband signal and performs band limitation, and a second down-sampling circuit that converts a sampling frequency of the band-limited complex baseband signal into a color subcarrier frequency of an NTSC signal A complex limiter circuit for controlling the amplitude of a signal output from the second down-sampling circuit to be constant, and a narrow-band low-pass for extracting a video carrier component of the signal output by the complex limiter circuit as a carrier signal A filter circuit, a digital PLL circuit that locks to a phase of a carrier signal output from the narrow-band low-pass filter circuit, and continuously reproduces and outputs the carrier signal at the locked phase; Interpolate a preset signal into a carrier signal to increase the sampling frequency And Ppusanpuru circuit, said interpolation by interpolating the carrier signal elevated sampling frequency, the carrier synchronizing circuit, characterized in that it comprises a fourth LPF circuit for outputting a reproduced carrier signal. A digital PLL circuit is a digital PLL circuit that outputs a frequency error signal representing a difference between a video carrier frequency of an intermediate frequency signal and a frequency twice as high as a color subcarrier frequency of an NTSC signal, and is output by the digital PLL circuit. A loop filter circuit that removes a high-frequency component from the frequency error signal; and a voltage-controlled oscillator that outputs a local oscillation signal used for generating an intermediate frequency signal based on a signal output by the loop filter circuit. claim 1 or claim 2 carrier synchronizing circuit according. The digital PLL circuit includes phase comparing means, integrating means, and oscillating means, and the phase comparing means calculates a phase difference between a phase of the input complex carrier signal and a phase of the reproduced complex carrier signal. A phase for outputting as an error signal, and for outputting the phase error signal as zero data forcibly indicating that there is no phase difference when the amplitude of the input complex carrier signal becomes smaller than a predetermined constant value. A comparing means, wherein the integrating means is an integrating means for generating and outputting a signal for controlling the oscillating means from the phase error signal, and wherein the oscillating means is a complex carrier based on a signal output from the integrating means. A phase of the signal is generated, a complex carrier signal is reproduced from the phase and output, and a phase of the reproduced complex carrier signal is fed back to the phase comparing means. Claim 1 or claim 2 or claim 3 carrier synchronizing circuit, wherein it is a digital PLL circuit is an oscillation means for outputting Te. A phase comparing means for calculating an arc tangent as a phase of the input complex carrier signal; and a phase error signal representing a difference between the phase of the complex carrier signal reproduced by the oscillating means and the calculated arc tangent. , A first ± π conversion circuit for converting the phase error signal into a value between -π and π, and a zero data circuit for outputting zero data as a signal indicating that there is no phase difference And an absolute value circuit that calculates and outputs the absolute value of the input complex carrier signal, and the absolute value output by the absolute value circuit is set in advance as a level for distinguishing whether or not the carrier signal has disappeared. A first threshold circuit for determining whether or not the level of the input complex carrier signal is at a sufficient level depending on whether or not the threshold value exceeds a threshold value; When it is determined that the carrier signal is at a sufficient level, the phase error signal output by the first ± π conversion circuit is output, and the first threshold circuit outputs the phase error signal at a sufficient level. 5. The carrier synchronization circuit according to claim 4 , wherein the phase comparison means includes a first selector circuit that outputs a signal output by the zero data circuit when it is determined that the signal is not output. The oscillation means is a numerically controlled oscillator circuit including a third adder, a second ± π conversion circuit, a second latch circuit, a COS circuit, and a SIN circuit, wherein the third addition means Is a third adder that adds a control signal input from an integrating means and a signal output by the second latch circuit and outputs the added signal, and wherein the second ± π converting circuit is a third adder. Is a second ± π converting circuit that converts a signal output from the adder into a value from −π to π, wherein the second latch circuit latches a signal output from the second ± π converting circuit. A COS circuit that outputs a cosine of a signal output by the second latch circuit; and a SIN circuit that outputs a cosine of a signal output by the second latch circuit. claim 4 or claim 5 characterized in that it is a SIN circuit for outputting a sinusoidal signal of Mounting of the carrier synchronization circuit. The integrating means multiplies the signal output by the phase comparing means by a direct term coefficient at the time of pull-in, a direct term coefficient at the time of holding, an integral term coefficient at the time of pull-in, and an integral term coefficient at the time of holding. Whether the detected phase error signals output from the first to fourth fixed value multiplying circuits and the phase comparing means have exceeded a threshold value which is set in advance as an error for performing the holding operation after the pull-in is completed. A second threshold circuit for determining whether or not the pull-in has been completed, and a signal output by the second fixed-value multiplying circuit when the second threshold circuit has determined that the pull-in has been completed. A second selector circuit for outputting a signal output from the first fixed-value multiplying circuit when the second threshold circuit determines that the pull-in has not been completed, and When it is determined that the path has completed the pulling, a signal output from the fourth fixed value multiplying circuit is output, and when it is determined that the second threshold circuit has not completed the pulling, the third fixed value multiplying circuit is output. A third selector circuit that outputs a signal output by the value multiplication circuit, an integration circuit that integrates a signal output by the third selector circuit, and an integration circuit that integrates a signal output by the second selector circuit with the integration circuit. it is obtained by adding a signal, a second adder and claim 4 or claim 5 or claim 6 carrier synchronizing circuit according to characterized in that the integrating means having an output as a control signal. 8. The carrier synchronization circuit according to claim 7 , wherein the integration means includes an D / A conversion circuit that converts a signal output from the integration circuit into an analog signal and outputs the analog signal as a frequency error signal. A loop filter circuit for removing a high-frequency component of a frequency error signal output from a digital PLL circuit; and a local oscillation signal for generating an IF signal based on a signal output from the loop filter circuit, and output. carrier synchronization circuit according to claim 3 or claim 8, wherein the having a voltage controlled oscillator. A multiplier that performs frequency conversion by multiplying a local oscillation signal and an RF signal input from a TV tuner or the like; and removes unnecessary components such as an image signal generated by the frequency conversion in the multiplier to obtain an analog IF signal. A band-pass filter circuit for outputting, an A / D conversion circuit for converting an analog IF signal output from the band-pass filter circuit into a digital IF signal, and an NTSC modulated wave of the signal output from the A / D conversion circuit. A step Nyquist filter circuit for attenuating signal components in the double sideband region, quasi-synchronous detection of a signal output from the step Nyquist filter circuit, and a quasi-synchronous detection circuit for outputting a complex baseband signal; A first low-pass filter circuit for removing an image component generated due to the quasi-synchronous detection; A first down-sampling circuit for converting a sampling frequency output from a pass filter circuit, a delay circuit for delaying a signal output from the first down-sampling circuit for a predetermined time, and reproduction of a carrier signal from the complex baseband signal was carried out, and a carrier synchronizing circuit of claim 1 to claim 9, wherein outputting a carrier signal reproduced on the basis of the reproduced carrier signal outputted from the carrier synchronizing circuit, the signal of the frequency phase output from the delay circuit A quadrature demodulation circuit comprising: a phase rotation circuit that corrects an error and outputs a signal that is completely synchronously detected. Based on the signal quadrature demodulation circuit according to claim 1 0, wherein outputs, interference wave removal apparatus characterized by finding and eliminating the interference waves.

Images