KR101092440B1 - Carrier Recovery apparatus and digital broadcasting receiver using the same - Google Patents

Abstract

The present invention relates to an apparatus for recovering a carrier by receiving a signal modulated by a residual sideband (VSB) scheme and a digital broadcast receiver using the same. In particular, the present invention has an effect of maintaining the characteristics of the existing FPLL system by adding and using a phase error detector that does not use another pilot signal based on the existing FPLL system. In this case, by using a COSTAS loop that does not use a pilot signal as a phase error detector, even when the pilot signal is very weak, the carrier can be recovered normally, thereby improving the carrier recovery performance of the system.

Carrier Recovery, FPLL, COSTAS

Description

Carrier recovery apparatus and digital broadcasting receiver using the same

1 is a block diagram of a general digital broadcast receiver

2 is a block diagram illustrating a structure of a carrier recovery apparatus of a conventional FPLL structure.

3 is a configuration block diagram of a carrier recovery apparatus of the conventional COSTAS structure

4A to 4D show examples of a signal spectrum and a modulation process according to the present invention.

5 is a block diagram illustrating a carrier recovery apparatus according to a first embodiment of the present invention.

6 is a block diagram illustrating a configuration of a carrier recovery apparatus according to a second embodiment of the present invention.

7 is a block diagram illustrating a carrier recovery apparatus according to a third embodiment of the present invention.

8 is a block diagram illustrating a carrier recovery apparatus according to a fourth embodiment of the present invention.

9 is a detailed block diagram illustrating an embodiment of a phase error detector according to the present invention.

10 is a block diagram showing an embodiment of a digital broadcast receiver including a detailed block of a modulator and a phase error detector according to the present invention;

Explanation of symbols for main parts of the drawings

500: A / D converter 501: delay

502: Hilbert Converter 503: Complex Multiplier                 

504: resampling unit 505, 1130: modulation unit

511,512,513: multiplier 506: phase error detector

507: frequency converter 508: loop filter

509: NCO 910, 1140: upper error detection unit

920,1150: lower error detection unit 930,1160: adder

1200: timing recovery unit

The present invention relates to a digital broadcast receiver, and more particularly, to an apparatus for recovering a carrier by receiving a signal transmitted after being modulated in a residual side band (VSB) scheme.

In general, the Grand Alliance's VSB method, which is adopted as a standard for digital TV transmission in the United States and Korea, greatly increases one sideband signal of two sidebands that are generated up and down around the carrier when amplitude is modulated. It only modulates the rest of the attenuation. That is, one of the methods of efficiently using the band region by taking only one sideband spectrum of the baseband and transferring it to the passband.

Such a VSB transmission method has the advantage of completely eliminating noise generated on a transmission channel when receiving a broadcast, so that the screen can be viewed without noise at all. However, if the transmission signal cannot be completely restored, the VSB cannot be viewed at all. TV receivers should be able to receive any signal that passes through any poor transmission channel.

FIG. 1 is a block diagram illustrating a general VSB digital TV receiver. When a RF (Radio Frequency) signal modulated by a VSB method is received through an antenna 101, the tuner 102 selects only a specific channel frequency desired by a user. The VSB signal of the RF band carried on the channel frequency is lowered to the intermediate frequency band (IF (typically 44 MHz or 43.75 MHz is widely used in analog TV broadcasting) and the other channel signal is properly filtered.

The output signal of the tuner 102, which lowers the spectrum of an arbitrary channel to a fixed primary IF band, is adopted to remove the interference of adjacent channel signals and the high frequency component generated from the tuner 102 (Surface Acoustic Wave). SAW) passes through the filter 103.

At this time, the digital broadcast signal, for example, since all information is present in the band of 6 MHz from the intermediate frequency of 44 MHz, the SAW filter 103 removes all remaining sections except for the 6 MHz band in which the information exists from the output of the tuner 102. The output is then output to the intermediate frequency processor 104.

The intermediate frequency processor 104 down converts the signal filtered by the SAW filter 103 to an oscillation frequency for generating a second IF signal, converts the signal into a second IF signal, and then converts the analog / digital (A / D) signal. Output to the unit 105.

The A / D converter 105 samples the output of the intermediate frequency processor 104 at a fixed frequency (or variable frequency), digitizes it, and outputs the digitized signal to the carrier recovery unit 106.

The carrier recovery unit 106 converts the passband signal digitized by the A / D converter 105 into a baseband signal and then outputs the DC eliminator 107. In this case, the carrier signal (that is, the pilot signal) used in the carrier recovery by the carrier recovery unit 106 changes to a DC component having a frequency of 0 Hz after carrier recovery.

That is, the DC component is forcibly inserted into the transmission signal by the transmitter in order to enable the carrier recovery unit 106 to perform carrier recovery. Therefore, after carrier recovery is performed, the DC component inserted in the transmitter is not necessary. Accordingly, the DC remover 107 detects and removes a DC component from the baseband signal output from the carrier recovery unit 106.

The baseband digital signal from which the DC component is removed is output to the synchronizer 108 and the channel equalizer 109.

In general, the most notable characteristics of the VSB transmission scheme proposed by the Grand Alliance (GA) are the pilot signal, the data segment synchronization signal, and the field synchronization signal. These signals are inserted and transmitted by the transmitter to improve characteristics such as carrier recovery and timing recovery.

Accordingly, the synchronization unit 108 recovers the data segment synchronization signal and the field synchronization signals that were inserted at the time of transmission from the DC-removed signal. The synchronization signals thus obtained are output to the channel equalizer 109, the phase tracker 110, and the FEC unit 111.                         

The channel equalizer 109 removes linear distortion of amplitude causing interference between symbols included in the baseband digital signal and ghost generated by a building or a mountain by using the baseband digital signal and a synchronization signal. The output is then output to the phase tracker 110.

The phase tracker 110 removes the residual phase noise caused by the tuner 102 from the output signal of the channel equalizer 109 and outputs the residual phase noise to the FEC unit 111. The FEC unit 111 recovers a transmission symbol from a signal from which phase noise has been removed using the synchronization signals, and outputs the transmission symbol in the form of a transport stream.

At this time, all the digital processing blocks after the carrier recovery unit 106 may not operate normally unless the carrier recovery is performed in the carrier recovery unit 106.

In order to recover the carrier, a transmitter sends a pilot signal when transmitting data. For example, the bandwidth of each terrestrial channel is the center frequency of 6 MHz, and the frequency at which the carrier signal exists on the transmission signal is called a pilot frequency. In this case, the term pilot is used instead of the carrier because the size of the carrier signal is reduced so that the digital TV signal does not affect the existing analog TV signal (about 13 dB).

Therefore, the carrier recovery unit 106 in the digital TV receiver accurately restores the position of the pilot frequency existing on the frequency of the transmission signal and converts it to the baseband signal.

Currently, the most common algorithm of the carrier recovery unit 106 is FPLL (Frequency Phase Locked Loop), which is simple to implement and excellent in performance. That is, the FPLL is a frequency locked loop (FLL) process that removes a frequency difference between a carrier component of a received signal and a reference carrier component of a receiver itself, and a phase lock between the two carrier signals from which the frequency difference is removed. Locked Loop) process is executed at the same time.

FIG. 2 is a block diagram illustrating an embodiment of a carrier recovery unit having an FPLL structure, in which a loop for locking a frequency and a loop for locking a phase are combined.

In FIG. 2, a first low pass filter 204, a delay 206, a sign extractor 207, a multiplier 208, a loop filter 209, an NCO 210, and a complex multiplier 203. Loop consists of a second lowpass filter 205, a multiplier 208, a loop filter 209, an NCO 210, and a complex multiplier 203. It is a PLL loop to lock the phase. The delay unit 206 is referred to as an auto frequency control filter (AFC Filter).

That is, since the passband signal digitized by the A / D converter 105 includes only a real component, it is input to the delay unit 201 and the Hilbert transformer 202 to form an imaginary component.

The Hilbert transformer 202 inverts the digitized passband real component signal by 90 degrees, converts the signal into an imaginary component signal, and outputs the complex multiplier 203. The signal of the passband real component input by the processing time of the signal is delayed and output to the complex multiplier 203.

For convenience of description, the real component signal output from the delayer 201 is a passband I signal and the imaginary component signal output from the Hilbert transformer 202 is called a passband Q signal.

The complex multiplier 203 receives a complex carrier, that is, a sinusoidal wave and a cosine wave, through which a carrier recovery is performed through a NCO (Numerically Controlled Oscillator) 210, and then passes through the delayer 201 and the Hilbert transformer 202. Transmit the passband I, Q signal to the baseband I, Q signal by multiplying with the band I, Q signals.

The baseband I, Q signals are output to the DC remover 107 and output to the first and second low pass filters 204 and 205 for carrier recovery.

In this case, in order to recover the carrier, only a signal around a frequency where a pilot frequency exists among 6 MHz bandwidths is required. Accordingly, the first and second low pass filters 204 and 205 remove remaining frequency components in which data components exist from the I and Q signals to prevent the performance of the carrier recovery unit from being degraded by the data.

That is, in the baseband I, Q signal, the pilot signal is changed into a DC component. Strictly, it changes to the frequency component around the DC component. This is generated by the difference between the carrier frequency component of the input signal and the carrier frequency component generated by the NCO 210. Accordingly, since only the component around the DC can recover the carrier, the first and second low pass filters 204 and 205 remove the remaining data components except for the signal around the DC component.                         

The output of the first low pass filter 204 is then input to a delay 206. The delay unit 206 delays the I signal from which data components have been removed for a predetermined time and outputs it to the code extractor 207. At this time, when the I signal of the pilot component output from the first low pass filter 204 passes through the delay unit 206 and the pilot does not exactly change to the DC component, the frequency error and the phase error corresponding thereto are generated.

That is, the delay unit 206 converts the difference between the pilot frequency component of the input passband signal and the carrier frequency component of the NCO 210 into a form of frequency error and outputs the result to the code extractor 207.

The code extractor 207 extracts only the sign of the signal output from the delay unit 206 and outputs it to the multiplier 208. The multiplier 208 multiplies the sign of the I signal by the Q signal from which the data components are removed and outputs to the loop filter 209 as a frequency error. The loop filter 209 filters and integrates an input frequency error and outputs the NCO 210 to the NCO 210. The NCO 210 generates a complex carrier proportional to the output of the loop filter 209, thereby generating the complex multiplier. Output to (203). The complex carrier becomes a signal closer to a carrier frequency component of a signal input more than before. When this process is repeated, a carrier frequency signal, which is almost similar to the carrier frequency component of the input signal, is generated by the NCO 210 and output to the complex multiplier 203. Transition to a signal.

This series of processes is the FLL process of the FPLL used for carrier recovery. In addition, after the FLL process, the frequency component of the carrier no longer exists at the output of the complex multiplier 203.

When the frequency difference between the two carrier signals is removed by the above-described process, the PLL process for removing the phase difference is now performed.

At this time, in the FPLL structure, switching between the FLL and PLL processes is automatically switched without external control. This is because there is no change in the output of the code extractor 207 after the FLL process is completed. Thus, the output of the sign extractor 207 no longer affects the block. However, only the output of the second low pass filter 205 is affected. This case is called a PLL process that compensates for the phase difference.

However, the carrier recovery apparatus of the FPLL structure described above has a form in which the output frequency of the NCO is adjusted to the frequency of the pilot signal. This means that information required for carrier recovery of the FPLL structure is obtained from the pilot component. In this case, the pilot signal component is so weakened as it passes through the channel that the system performance degradation cannot be prevented if the position cannot be accurately located in the spectrum.

In other words, the FPLL structure is a modified form of the COSTAS loop, and is designed to operate as a frequency error detector (FED) by adding an AFC filter to the COSTAS loop. Therefore, the FED performance of the FPLL structure depends on the magnitude of the pilot signal, and especially when the pilot signal is weakened by the channel, the performance is greatly reduced.

3 shows a COSTAS loop structure as another embodiment of a carrier recovery apparatus. That is, the Costas loop method is a PLL structure that estimates the frequency and phase of the carrier directly from the suppressed modulated signal.                         

In FIG. 3, the sign detector 305 may optionally be employed. 3 is equivalent to FIG. 2 except for the delay unit 206 serving as a frequency error detector (FED) in FIG. 2.

In other words, the FPLL currently used is a modified form of the COSTAS loop, which removes the AFC filter (i.e., the delayer of FIG. 2) when the pilot signal is weakened while passing through the channel, thereby performing carrier recovery using the COSTAS loop. It means you can.

However, when using the existing spectrum, since the desired signal portion of the spectrum is already weakened, it is not significant to change only the shape of the loop as shown in FIG. 3. In other words, if the pilot signal component is very weak as it passes through the channel, and its position cannot be accurately located on the spectrum, the system performance degradation cannot be avoided even in the COSTAS loop shown in FIG.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a carrier recovery apparatus for recovering a carrier using both edges of the spectrum band and a digital broadcast receiver using the same.

In order to achieve the above object, the carrier recovery apparatus according to an embodiment of the present invention, the frequency shift unit for converting the digital passband signal by multiply the complex carrier to a digital baseband signal; Modulation for generating a signal of the upper edge spectrum form where the opposite edge of the edge with the pilot signal is located near DC and the lower edge spectrum form signal where the pilot signal is located near DC from the baseband signal output from the frequency shifter part; A phase error detector for detecting and outputting an upper phase error and a lower phase error from an upper edge spectrum signal and a lower edge spectrum signal output from the modulator; A loop filter for filtering and integrating the phase error output from the phase error detection unit; And an NCO generating a complex carrier in proportion to the integrated value based on a preset center frequency and outputting the complex carrier to the frequency shifting unit.

In the carrier recovery apparatus according to an embodiment of the present invention, when the pilot signal is located at 3.309441 MHz on the passband signal spectrum, the center frequency of the NCO is set to 3.309441 MHz.

를 연속 두 번 곱하여 상위 에지 스펙트럼 신호를 생성하고,

를 곱하여 하위 에지 스펙트럼 신호를 생성하는 것을 특징으로 한다.The modulator is coupled to the baseband signal output from the frequency shifter.

Multiply twice in succession to produce a higher edge spectral signal,

Multiply by to generate a lower edge spectrum signal.

In a carrier recovery apparatus according to an embodiment of the present invention, when the pilot signal is located at 3.309441 MHz on the passband signal spectrum, the center frequency of the NCO is set to 6.0 MHz.

를 곱하여 상위 에지 스펙트럼 신호를 생성하고,

를 곱하여 하위 에지 스펙트럼 신호를 생성하는 것을 특징으로 한다.The modulator is coupled to the baseband signal output from the frequency shifter.

Multiply by to generate the upper edge spectral signal,

Multiply by to generate a lower edge spectrum signal.

The phase error detection unit may include an upper error detection unit of a COSTAS loop structure that detects an upper phase error by extracting a signal near a DC where a pilot signal does not exist among the upper edge spectrum signals; An upper error detection unit of an FPLL structure for detecting a lower phase error by extracting a signal near a DC in which a pilot signal exists among the lower edge spectrum signals; It is characterized by consisting of an adder for outputting after calculating the final phase error by adding the upper, lower phase error.

According to another embodiment of the present invention, a carrier recovery apparatus multiplies a digital passband signal by a first complex carrier to output a digital baseband signal in the form of an upper edge spectrum in which an opposite edge of an edge with a pilot signal is located near DC. A first frequency shifting unit; A second frequency shifter which multiplies the digital passband signal by a second complex carrier to output a digital baseband signal in the form of a lower edge spectrum in which the pilot signal is located near DC; A phase error detector for detecting and outputting an upper phase error and a lower phase error from the upper edge spectrum signal and the lower edge spectrum signal output from the first and second frequency shifting units, respectively; A loop filter for filtering and integrating the phase error output from the phase error detection unit; The first NCO generating a first complex carrier that is proportional to the value integrated in the loop filter based on a preset first center frequency and outputting the first complex carrier to the first frequency shifter, and the second center frequency. And a second NCO generating a second complex carrier proportional to the value integrated in the loop filter and outputting the second complex carrier to the second frequency shifter.

In the carrier recovery apparatus according to another embodiment of the present invention, when the pilot signal is located at 3.309441 MHz on the passband signal spectrum, the first center frequency is set to 3.309441 MHz, and the second center frequency is set to 8.690559 MHz. It is done.

According to an embodiment of the present invention, a digital broadcast receiver includes: an A / D converter configured to sample an analog passband signal at a sampling frequency and convert the analog passband signal into a digital passband signal; A frequency shifter for converting the passband signal digitized by the A / D converter into a digital baseband signal by multiplying a complex carrier wave; A modulation for generating a signal in the form of an upper edge spectrum in which the opposite edge of the edge with a pilot signal is located near DC and a signal in the form of a lower edge spectrum in which the pilot signal is located near DC from the baseband signal output from the frequency shifter. part; A phase error detector for detecting and outputting an upper phase error and a lower phase error from an upper edge spectrum signal and a lower edge spectrum signal output from the modulator; A loop filter for filtering and integrating the phase error output from the phase error detection unit; An NCO generating a complex carrier in proportion to the value integrated in the loop filter based on a preset center frequency and outputting the complex carrier to the frequency shifter; And a timing recovery unit for detecting timing error information from the lower edge spectrum signal, generating a frequency of a newly corrected double symbol clock according to the information, and outputting the frequency as a sampling frequency to the A / D converter. It is characterized by.

In the digital broadcast receiver according to an embodiment of the present invention, when the A / D converter converts an analog passband signal into a digital passband signal using a fixed frequency generated by a fixed oscillator as a sampling frequency, the frequency shifter outputs the signal. A resampling unit for resampling and interpolating the digital baseband signal at a frequency of twice the symbol clock output from the timing recovery unit is further included between the frequency shifting unit and the modulation unit, and synchronizes the phase error to a fixed frequency. The output frequency converter is further included between the phase error detector and the loop filter.

According to another aspect of the present invention, there is provided a digital broadcast receiver comprising: an A / D converter for sampling an analog passband signal at a sampling frequency and converting the analog passband signal into a digital passband signal; A first frequency shifter for outputting a digital baseband signal in the form of an upper edge spectrum where the opposite edge of the edge with the pilot signal is located near DC by multiplying the digitized passband signal by the A / D converter; ; A second frequency shifter configured to multiply a passband signal digitized by the A / D converter by a second complex carrier to output a digital baseband signal having a lower edge spectrum in which a pilot signal is located near DC; A phase error detector for detecting and outputting an upper phase error and a lower phase error from the upper edge spectrum signal and the lower edge spectrum signal output from the first and second frequency shifting units, respectively; A loop filter for filtering and integrating the phase error output from the phase error detection unit; The first NCO generating a first complex carrier that is proportional to the value integrated in the loop filter based on a preset first center frequency and outputting the first NCO to the first frequency shifting unit; A second NCO generating a second complex carrier proportional to an integrated value at and outputting the second complex carrier to the second frequency shifter; And a timing recovery unit for detecting timing error information from the lower edge spectrum signal, generating a frequency of a newly corrected double symbol clock according to the information, and outputting the frequency as a sampling frequency to the A / D converter. It is characterized by.

In the digital broadcasting receiver according to another embodiment of the present invention, when the A / D converter converts an analog passband signal into a digital passband signal using a fixed frequency generated by a fixed oscillator as a sampling frequency, the first and second A first and second resampling unit for re-sampling the digital baseband signal output from the frequency shifting unit to a frequency of twice the symbol clock output from the timing recovery unit and interpolating the first and second frequency shifting unit and the phase error It is further included between the detection unit, characterized in that the frequency conversion unit for outputting the phase error in synchronization with a fixed frequency is further included between the phase error detection unit and the loop filter.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings will be described the configuration and operation of the embodiment of the present invention. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.                     

The same components as in the related art are denoted by the same names and the same reference numerals for convenience of description, and detailed description thereof will be omitted.

Since the COSTAS loop does not require a pilot signal to derive phase error information, the present invention is characterized by performing carrier recovery using both edges of the spectrum by further adding a COSTAS structure based on the FPLL structure.

If both edge portions of the spectrum are not weakened, the performance of the carrier recovery unit may be improved by using the COSTAS loop using the opposite edge of the spectrum.

4 shows a spectrum forming process for using the opposite edge of the existing spectrum.

4 (a) shows a spectrum of an I channel signal in a 6 MHz pass band, and when the center frequency of the I channel signal is located at 6 MHz, the pilot signal is located at 3.309441 MHz.

FIG. 4 (b) shows the spectrum of the signal transitioned to the baseband when the center frequency of the NCO in the carrier recovery unit is adjusted to 3.309441 MHz so that the pilot signal of (a) can reach DC. It is showing. 4 (b) is a spectrum of the I channel signal when the 6 MHz passband signal of (a) is shifted to the baseband by adjusting the center frequency of the NCO to 3.309441 MHz, and the pilot signal is located at DC. Able to know.

), 도 4의 (c)와 같이 된다. 다시 도 4의 (c)의 신호에

를 곱하는 변조를 수행하면 도 4의 (d)와 같이 (b)의 기저대역 신호를 기준으로 반대편 에지가 DC에 존재하는 신호가 생성된다. And modulating the signal of (b) to 2.690559 MHz to bring the opposite edge to DC based on the baseband signal of (b) (i.e., the signal of (b) *

) And (c) of FIG. 4. Again to the signal of Figure 4 (c)

When the multiplication is performed, as shown in (d) of FIG. 4, a signal having the opposite edge in DC is generated based on the baseband signal of (b).

를 곱하면 도 4의 (b)와 같이 원래의 기저대역 신호가 생성된다. And the signal of FIG.

By multiplying, the original baseband signal is generated as shown in FIG.

In the present invention, the spectrum of the form as shown in Figure 4 (b) is called the lower edge spectrum (Lower Edge spectrum), the spectrum of the form as shown in Figure 4 (d) is called the Upper Edge spectrum (Upper Edge spectrum).

The present invention performs carrier recovery using the lower and upper edge spectrum of FIG.

The following describes a carrier recovery process of the present invention through various embodiments.

First embodiment

FIG. 5 is a block diagram illustrating an apparatus for recovering a carrier according to a first embodiment of the present invention, in which an A / D converter 500 samples an analog passband signal received at a fixed frequency oscillated by a fixed oscillator to obtain a digital passband. An embodiment of the case of converting into a signal.

In this case, a resampler 504 and a frequency converter 509 are required. The reason for this is described in detail later.

A complex multiplier 503 for converting a passband signal into a baseband signal is connected to a front end of the resampling unit 504.

A modulator 505 is connected to an output terminal of the resampler 504 to control both ends of the spectrum of the resampled baseband signal to be located at DC. A phase error detector 506 is disposed between the output terminal of the modulator 505 and the frequency converter 509, and a loop filter 508 and an NCO 509 between the frequency converter 509 and the complex multiplier 503. Are arranged sequentially.

In the first embodiment of the present invention configured as described above, the A / D converter 500 samples the analog passband signal output from the intermediate frequency processor by a fixed frequency, that is, a constant clock of 25 MHz, to delay the delayer 501 and Hilbert. Output to converter 502. That is, although the transmitter transmits data sampled at 21.52 MHz, which is twice the symbol frequency fs, the data output from the A / D converter 500 is a digital passband signal sampled at 25 MHz.

The Hilbert transformer 502 inverts the digitized passband real component signal by 90 degrees, converts the signal into an imaginary component signal, and outputs the complex multiplier 503. The delay unit 501 outputs the complex multiplier 503. The signal of the passband real component inputted by the processing time of is delayed and outputted to the complex multiplier 503.

FIG. 4 (a) shows an example of the spectrum of the digital passband signal, showing an intermediate frequency of 6 MHz and a pilot frequency of 3.309441 MHz.

The complex multiplier 503 multiplies the digital passband I, Q signal by the output frequency of the NCO 509, converts the signal into a baseband I, Q signal, and outputs the result to the resampling unit 504.

At this time, the center frequency of the NCO 509 is set to 3.309441 MHz so that the pilot signal of FIG. 4A is located at DC.

Then, in the spectrum of the baseband signal output from the complex multiplier 503, the pilot signal is located at DC as shown in FIG. That is, the lower edge spectrum in which the pilot signal is present in DC is formed.

On the other hand, while the transmitter transmits data sampled at 21.52 MHz, which is twice the symbol clock frequency fs, the data output from the A / D converter 500 is digital data sampled at 25 MHz.

Therefore, the resampling unit 504 converts the digital baseband I and Q signals output from the complex multiplier 503 using the output frequency of the timing recovery unit (not shown). The interpolation is performed on a digital signal synchronized with 21.52 MHz and output to the modulator 505. This is because the A / D converter 500 samples and transmits the data sampled and transmitted at 21.52 MHz at 25 MHz, and therefore, the resampling unit 504 again samples at twice the symbol clock frequency, that is, 21.52 MHz. Will print.

The modulator 505 modulates both ends of the spectrum of the resampled baseband signal to be located at DC in order to perform carrier recovery using both ends of the baseband signal.

To this end, the modulator 505 includes first to third multipliers 511 to 513.

를 곱하여 도 4의 (c)와 같은 스펙트럼을 형성하고, 제 2 곱셈기(512)는 도 4의 (c)와 같은 스펙트럼 신호에

를 다시 곱하여 도 4의 (d)와 같은 상위 에지 스펙트럼을 형성한다. That is, the first multiplier 511 applies to the lower edge spectrum signal as shown in FIG.

Multiplying to form a spectrum as shown in (c) of FIG. 4, and the second multiplier 512 is applied to the spectral signal as shown in (c) of FIG.

Multiply again to form the upper edge spectrum as shown in FIG.

를 곱하여 도 4의 (b)와 같은 하위 에지 스펙트럼을 형성한다. And the third multiplier 513 is applied to the spectral signal as shown in (c) of FIG.

Multiply by to form a lower edge spectrum as shown in FIG.

The upper edge spectrum signal formed by the second multiplier 512 and the lower edge spectrum signal formed by the third multiplier 513 are output to the phase error detector 506.

In this case, instead of using the third multiplier 513, the lower edge spectrum signal output from the resampling unit 504 may be directly input to the phase error detector 506. This may vary by system designer.

The phase error detector 506 detects the phase error from the upper edge spectrum signal and the lower edge spectrum signal, respectively, and adds the phase error to the frequency converter 507.

9 is a detailed block diagram of the phase error detector 506. Since the pilot signal does not exist in DC for the upper edge signal, a COSTAS loop structure except the AFC filter is used. Since the pilot signal exists in the DC for the lower edge signal, the conventional FPLL structure in which a frequency error detector (FED) is added is used. This is because the COSTAS loop structure does not use a pilot signal, and the FPLL structure uses a pilot signal.

That is, the phase error detector adds an upper error detector 910 for detecting an upper phase error from an upper edge spectrum signal, a lower error detector 920 for detecting a lower phase error from a lower edge spectrum signal, and adds the upper and lower phase errors to a final phase. The adder 930 outputs an error.

The upper error detector 910 includes a first low pass filter 911, a second low pass filter 912, and a multiplier 914. Here, the code extractor 903 which is an AFC filter can be selectively adopted.

The lower error detector 920 includes a third low pass filter 921, a fourth low pass filter 922, a delay 923, a code extractor 924, and a multiplier 925.

That is, the first and second low pass filters 911 and 912 of the upper error detection unit 910 remove the remaining data except the signals around the DC component among the upper edge spectrum I and Q signals, respectively, and then, multiply the data components to the multiplier 914. Output In this case, the upper edge spectrum I, Q signal does not have a pilot signal in the DC component as shown in (d) of FIG. The multiplier 914 multiplies the I and Q signals passing through the first and second low pass filters 911 and 912 and outputs the result to the adder 930 as a higher phase error.                     

The third and fourth low pass filters 921 and 922 of the lower error detector 920 perform filtering to remove the remaining components except for the signals around the DC components among the lower edge spectrum I and Q signals. At this time, the pilot signal is present in the DC component of the lower edge spectrum I and Q signals as shown in FIG. If a difference between the carrier frequency component of the input signal and the frequency component generated by the NCO 509 occurs, the pilot signal changes to a frequency component around the DC component.

The output of the third low pass filter 921 is input to the delayer 923 serving as an AFC, and the output of the fourth low pass filter 922 is input to the multiplier 925. The delay unit 923 delays the I signal from which the data components are removed and outputs the delayed signal to the code extractor 924 for a predetermined time. In this case, when the I signal of the pilot component output from the third low pass filter 921 does not change to the DC component while passing through the delay unit 923, it means that a frequency error and a phase error corresponding to the same are generated.

That is, the delay unit 923 converts the difference between the pilot frequency component of the input passband signal and the frequency component of the NCO 509 into a form of frequency error and outputs the result to the code extractor 924.

The code extractor 924 extracts only the sign of the signal output from the delay unit 923 and outputs it to the multiplier 925. The multiplier 925 multiplies the sign of the I signal by the Q signal from which the data component is removed and outputs the result to the adder 930 as a lower phase error.

The adder 930 adds an upper phase error and a lower phase error to output the final phase error to the frequency converter 507.

The frequency converter 507 is a block added together with the resampling unit 504 because the A / D converter 500 samples at a fixed frequency (that is, 25 MHz), and synchronizes a phase error to 25 MHz again. To the loop filter 508.

That is, since the complex multiplier 503 converts the passband signal into a baseband signal in synchronization with 25 MHz, the loop filter 508 and the NCO 509 must also operate at 25 MHz. However, since the phase error output from the phase error detector 506 is a signal synchronized to 21 MHz by the resampling unit 504, the frequency converter 507 is required.

The loop filter 508 filters and integrates an input phase error and outputs the result to the NCO 509. The NCO 509 has a center frequency of 3.309441 MHz and is a complex carrier wave proportional to the output of the loop filter 508. Is generated and output to the complex multiplier 503. A complex carrier (cos, sin) for compensating the phase error value becomes a signal closer to a carrier frequency component of a signal input more than before. When this process is repeated, a frequency signal that is almost similar to the carrier frequency component of the input signal is generated by the NCO 509 and output to the complex multiplier 503. The complex multiplier 503 receives the baseband signal for which the signal of the pass band is desired. Transition to

Second embodiment

6 is a block diagram illustrating a carrier recovery apparatus according to a second embodiment of the present invention, in which the A / D converter 600 samples an analog passband signal received at a variable frequency and converts the received signal into a digital passband signal. Example for the case.

In this case, the resampling unit 504 and the frequency converter 509 of FIG. 5 are not necessary. Instead, twice the symbol clock frequency 2fs generated from the timing error information of the timing recovery unit (not shown) is input to the A / D converter 600 and used for sampling.

That is, the configuration and operation of FIG. 6 are the same as those of FIG. 5 described above. 6 has a difference that the frequency of the clock input to the A / D converter 600 is twice the symbol clock frequency 2fs instead of the fixed frequency. Therefore, since the configuration and operation of FIG. 6 may be referred to FIG. 5, detailed descriptions thereof will be omitted.

In the case of FIG. 6, the A / D converter 600 samples the analog passband signal at twice the symbol clock frequency 2fs and converts the analog passband signal into a digital passband signal. Thus, the resampling unit 504 and the frequency converter 507 ), Which reduces the hardware burden.

Third Embodiment

FIG. 7 is a block diagram illustrating a carrier recovery apparatus according to a third embodiment of the present invention. The A / D converter 700 samples an analog passband signal at a fixed frequency. Different from the second embodiment.

That is, in FIG. 7, the passband signal digitized by the A / D converter 700 is input to the delay unit 701 and the Hilbert transformer 702. The digital passband I and Q signals output from the delay unit 701 and the Hilbert transformer 702 are input to the first and second complex multipliers 703 and 705. In addition, the output of the first NCO 710 is input to the first complex multiplier 703, and the output of the second NCO 711 is input to the second complex multiplier 705.

The lower edge spectrum signal output from the first complex multiplier 703 is input to the phase error detector 707 via the first resampling unit 704 and the upper edge spectrum signal output from the second complex multiplier 705. Is input to the phase error detector 707 via the second resampling unit 706.

The phase error output from the phase error detector 707 sequentially passes through the frequency converter 708 and the loop filter 709 and is then input to the first and second NCOs 710 and 711.

Referring to the operation of the third embodiment according to the present invention configured as described above is as follows.

That is, when the pilot frequency is located at 3.309441 MHz as shown in FIG. 4A, the center frequency of the first NCO 710 is set to 3.309441 MHz, and the center frequency of the second NCO 711 is set to 8.690559 MHz.

When the first complex multiplier 703 multiplies the digital passband I, Q signal by the output frequency of the first NCO 710 to convert the baseband I, Q signal, the pilot signal is shown in FIG. The lower edge spectrum located at DC is formed.

In addition, when the second complex multiplier 705 multiplies the digital passband I, Q signal by the output frequency of the second NCO 711 and converts the signal into a baseband I, Q signal, a pilot signal is obtained as shown in FIG. An upper edge spectrum is formed in which the opposite edge of the existing edge is at DC.                     

The first resampling unit 704 interpolates the lower edge spectral signal output from the first complex multiplier 703 to a double symbol clock frequency 2fs, that is, a lower edge spectral signal synchronized to 21.52 MHz. Output to the detection unit 707.

The second resampling unit 706 interpolates the upper edge spectral signal output from the second complex multiplier 705 to a double symbol clock frequency (2fs), that is, an upper edge spectral signal synchronized to 21.52 MHz. Output to the detection unit 707.

The detailed configuration and operation of the phase error detector 707 are the same as the phase error detector described in the first embodiment of the present invention.

That is, the phase error detector 707 detects the upper phase error from the upper edge spectrum signal in the upper error detector 910 having the COSTAS structure as shown in FIG. 9, and the lower edge spectrum signal in the lower error detector 920 having the FPLL structure. After detecting the lower phase error from the adder 930, two phase errors are added to the frequency converter 708. For further details refer to the first embodiment described above.

The frequency converter 708 outputs the phase error synchronized with 21 MHz to the loop filter 709 by synchronizing again with 25 MHz. The loop filter 709 filters and integrates an input phase error and outputs the first and second NCOs 710 and 711. The first NCO 710 generates a complex carrier in proportion to the output of the loop filter 709 using 3.309441 MHz as a center frequency and outputs the complex carrier to the first complex multiplier 703. The second NCO 711 generates a complex carrier in proportion to the output of the loop filter 709 using 8.690559 MHz as a center frequency and outputs the complex carrier to the second complex multiplier 705.

Fourth embodiment

8 is a block diagram illustrating a carrier recovery apparatus according to a fourth embodiment of the present invention. The basic configuration of FIG. 8 is the same as the first embodiment described above. However, in the fourth embodiment of the present invention, the configuration of the center frequency of the NCO and the modulator is different from that of the first embodiment.

를 다시 곱하여 상위 에지 스펙트럼을 형성하는 곱셈기(811)와 재샘플링부(804)의 출력에

를 곱하여 하위 에지 스펙트럼을 형성하는 곱셈기(812)로 구성된다. The center frequency of the NCO 809 is set to 6.0 MHz, and the modulator 805 is connected to the output of the resampling unit 804.

To the output of the multiplier 811 and the resampling unit 804, which multiply again to form the upper edge spectrum.

Multiplier 812 to form a lower edge spectrum.

Then, the signal passing through the complex multiplier 803 is in the form of the center of the spectrum is located in DC, as shown in (c) of FIG.

를 곱하면 도 4의 (d)와 같은 상위 에지 스펙트럼이 형성된다. 그리고 곱셈기(812)에서 상기 재샘플링부(804)의 출력에

를 곱하면 도 4의 (b)와 같은 하위 에지 스펙트럼이 형성된다. The output of the complex multiplier 803 is input to the modulator 805 via the resampling unit 804. At this time, the multiplier 811 of the modulator 805 is connected to the output of the resampling unit 804.

Multiplying results in an upper edge spectrum as shown in FIG. The multiplier 812 outputs the resampling unit 804.

Multiplying results in a lower edge spectrum as shown in FIG.

The upper and lower edge spectrum signals are input to the phase error detector 806.

The phase error detector 806 detects the upper phase error from the upper edge spectrum signal in the upper error detector 910 having the COSTAS structure as shown in FIG. 9, and the lower edge spectrum signal in the lower error detector 920 having the FPLL structure. After detecting the lower phase error from the adder 930, the two phase errors are added to output the final phase error.

When the phase error detected by the phase error detector 806 passes through the frequency converter 807, the loop filter 808, and the NCO 809 sequentially, detailed operations may be omitted since the detailed descriptions may be referred to the above-described embodiments.

10 illustrates an embodiment of a digital broadcast receiver including detailed blocks of a carrier recovery unit and a phase error detector according to the present invention.

In FIG. 10, reference numeral 1130 denotes a modulator having the same configuration as the first embodiment of the present invention, and 1200 denotes a timing recovery unit. 1140 is an upper error detector, 1150 is a lower error detector, and 1160 is an adder, and has the same configuration as that of the phase error detector of FIG. 9.

The timing recovery unit 1200 includes a timing error detector 1201, a loop filter 1202, and an NCO 1203. The timing error detector 1201 obtains information on the timing error from the lower edge spectrum signal of FIG. 4B and outputs the information about the timing error to the loop filter 1202. The loop filter 1202 filters only the low-band signal components among the timing error information extracted by the timing error detector 1201 and outputs the low-band signal component to the NCO 1203. The NCO 1203 adjusts the sampling timing of the resampling unit 1120 by converting the output frequency according to the low band component of the timing error information.

10 illustrates a case in which an A / D converter (not shown) samples an analog passband signal at a fixed frequency, that is, 25 MHz. 10, if the resampling unit 1120 and the frequency converter 1170 are to be removed, the output frequency of the NCO 1203 of the timing recovery unit 1200 may be input to the A / D converter.

In FIG. 10, the center frequency of the NCO 1190 for carrier recovery is 3.309441 MHz, which is the same structure as the first embodiment of the present invention.

On the other hand, the terms used in the present invention (terminology) are terms defined in consideration of the functions in the present invention may vary according to the intention or practice of those skilled in the art, the definitions are the overall contents of the present invention It should be based on.

The present invention is not limited to the above-described embodiments, and can be modified by those skilled in the art as can be seen from the appended claims, and such modifications are within the scope of the present invention.

As described above, the effects of the carrier recovery apparatus and the digital broadcast receiver using the same according to the present invention will be described.

First, the present invention has the effect of maintaining the characteristics of the existing FPLL system by adding and using a phase error detector that does not use another pilot signal based on the existing FPLL system. It is also very easy to apply to existing systems.

Second, the present invention can improve the carrier recovery performance of the system by using a COSTAS loop that does not use a pilot signal as a phase error detector, since the carrier can be normally recovered even when the pilot signal is very weak.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (11)

A frequency shifting unit multiplying the digital passband signal by a complex carrier to convert the digital passband signal into a digital baseband signal; From the baseband signal output from the frequency shifter, an upper edge spectrum signal in which an opposite edge of an edge with a pilot signal is located near DC and a lower edge spectrum signal in which a pilot signal is located near DC. A modulator for generating a; A phase error detector for detecting and outputting an upper phase error and a lower phase error from an upper edge spectrum signal and a lower edge spectrum signal output from the modulator; A loop filter for filtering and integrating the phase error output from the phase error detection unit; And And a NCO (Numerically Controlled Oscillator) for generating a complex carrier in proportion to the integrated value based on a preset center frequency and outputting the complex carrier to the frequency shifting unit. The method of claim 1, wherein the modulator To the baseband signal output from the frequency shifter.

Multiply twice in succession to produce a higher edge spectral signal,

And multiplying to generate a lower edge spectrum signal. The method of claim 1, wherein the modulator To the baseband signal output from the frequency shifter.

Multiplying twice successively to output an upper edge spectrum signal, and outputting an output signal of the frequency shifting unit as a lower edge spectrum signal. The method of claim 1, wherein the modulator To the baseband signal output from the frequency shifter.

Multiply by to generate the upper edge spectral signal,

And multiplying to generate a lower edge spectrum signal. The method of claim 1, wherein the phase error detection unit An upper error detection unit of a COSTAS loop structure which detects an upper phase error by extracting a signal near a DC where a pilot signal does not exist among the upper edge spectrum signals; An upper error detection unit of a frequency phase locked loop (FPLL) structure that detects a lower phase error by extracting a signal near a DC where a pilot signal exists among the lower edge spectrum signals; And an adder for calculating and outputting a final phase error by adding the upper and lower phase errors. A first frequency shifter for multiplying the digital passband signal by a first complex carrier to output a digital baseband signal in the form of an upper edge spectrum in which an opposite edge of the edge with the pilot signal is located near direct current (DC); A second frequency shifter which multiplies the digital passband signal by a second complex carrier to output a digital baseband signal in the form of a lower edge spectrum in which the pilot signal is located near DC; A phase error detector for detecting and outputting an upper phase error and a lower phase error from the upper edge spectrum signal and the lower edge spectrum signal output from the first and second frequency shifting units, respectively; A loop filter for filtering and integrating the phase error output from the phase error detection unit; A first NCO (Numerically Controlled Oscillator) for generating a first complex carrier proportional to the value integrated in the loop filter based on a preset first center frequency and outputting the first complex carrier to the first frequency shifter; And a second NCO generating a second complex carrier proportional to a value integrated in the loop filter based on a second preset center frequency and outputting the second complex carrier to the second frequency shifter. An analog-to-digital (A / D) converter configured to sample the analog passband signal at a sampling frequency and convert the analog passband signal into a digital passband signal; A frequency shifter for converting the passband signal digitized by the A / D converter into a digital baseband signal by multiplying a complex carrier wave; From the baseband signal output from the frequency shifter, an upper edge spectrum signal in which an opposite edge of an edge with a pilot signal is located near DC and a lower edge spectrum signal in which a pilot signal is located near DC. A modulator for generating a; A phase error detector for detecting and outputting an upper phase error and a lower phase error from an upper edge spectrum signal and a lower edge spectrum signal output from the modulator; A loop filter for filtering and integrating the phase error output from the phase error detection unit; A NCO (Numerically Controlled Oscillator) for generating a complex carrier in proportion to the value integrated in the loop filter based on a preset center frequency and outputting the complex carrier to the frequency shifter; And And a timing recovery unit for detecting timing error information from the lower edge spectrum signal, generating a frequency of a newly corrected double symbol clock according to the information, and outputting the frequency as a sampling frequency to the A / D converter. Digital broadcast receiver characterized. The method of claim 7, wherein When the A / D converter converts an analog passband signal into a digital passband signal using a fixed frequency generated by the fixed oscillator as a sampling frequency, A resampling unit for resampling the digital baseband signal output from the frequency shifting unit at a frequency of twice the symbol clock output from the timing recovery unit, and interpolating between the frequency shifting unit and the modulation unit, And a frequency converter configured to output the phase error in synchronization with a fixed frequency, between the phase error detector and a loop filter. The method of claim 7, wherein the modulator To the baseband signal output from the frequency shifter.

Multiply twice in succession to produce a higher edge spectral signal,

And multiplying to generate a lower edge spectrum signal. The method of claim 7, wherein the modulator To the baseband signal output from the frequency shifter.

Multiply by to generate the upper edge spectral signal,

And multiplying to generate a lower edge spectrum signal. An analog-to-digital (A / D) converter configured to sample the analog passband signal at a sampling frequency and convert the analog passband signal into a digital passband signal; The A / D converter multiplies the digitized passband signal by a first complex carrier to output a digital baseband signal in the form of an upper edge spectrum in which the opposite edge of the edge with the pilot signal is located near the direct current. 1 frequency transition section; A second frequency shifter configured to multiply a passband signal digitized by the A / D converter by a second complex carrier to output a digital baseband signal having a lower edge spectrum in which a pilot signal is located near DC; A phase error detector for detecting and outputting an upper phase error and a lower phase error from the upper edge spectrum signal and the lower edge spectrum signal output from the first and second frequency shifting units, respectively; A loop filter for filtering and integrating the phase error output from the phase error detection unit; A first NCO (Numerically Controlled Oscillator) for generating a first complex carrier proportional to the value integrated in the loop filter based on a preset first center frequency and outputting the first complex carrier to the first frequency shifter; A second NCO which generates a second complex carrier proportional to a value integrated in the loop filter based on a second preset center frequency and outputs the second complex carrier to the second frequency shifter; And And a timing recovery unit for detecting timing error information from the lower edge spectrum signal, generating a frequency of a newly corrected double symbol clock according to the information, and outputting the frequency as a sampling frequency to the A / D converter. Digital broadcast receiver characterized.

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