JPS59198042A - 同期信号受信保護回路の試験方式 - Google Patents

同期信号受信保護回路の試験方式

Info

Publication number
JPS59198042A
JPS59198042A JP58072448A JP7244883A JPS59198042A JP S59198042 A JPS59198042 A JP S59198042A JP 58072448 A JP58072448 A JP 58072448A JP 7244883 A JP7244883 A JP 7244883A JP S59198042 A JPS59198042 A JP S59198042A
Authority
JP
Japan
Prior art keywords
synchronization signal
synchronizing signal
circuit
test
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58072448A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0218779B2 (cg-RX-API-DMAC10.html
Inventor
Yoshio Aoki
芳夫 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58072448A priority Critical patent/JPS59198042A/ja
Publication of JPS59198042A publication Critical patent/JPS59198042A/ja
Publication of JPH0218779B2 publication Critical patent/JPH0218779B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58072448A 1983-04-25 1983-04-25 同期信号受信保護回路の試験方式 Granted JPS59198042A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58072448A JPS59198042A (ja) 1983-04-25 1983-04-25 同期信号受信保護回路の試験方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58072448A JPS59198042A (ja) 1983-04-25 1983-04-25 同期信号受信保護回路の試験方式

Publications (2)

Publication Number Publication Date
JPS59198042A true JPS59198042A (ja) 1984-11-09
JPH0218779B2 JPH0218779B2 (cg-RX-API-DMAC10.html) 1990-04-26

Family

ID=13489579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58072448A Granted JPS59198042A (ja) 1983-04-25 1983-04-25 同期信号受信保護回路の試験方式

Country Status (1)

Country Link
JP (1) JPS59198042A (cg-RX-API-DMAC10.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04178037A (ja) * 1990-11-13 1992-06-25 Fujitsu Ltd ディジタル伝送システムのフレーム・フォーマットにおける機能試験方法及び試験回路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5718146A (en) * 1980-07-07 1982-01-29 Nippon Telegr & Teleph Corp <Ntt> Diagnostic system for synchronous operating circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5718146A (en) * 1980-07-07 1982-01-29 Nippon Telegr & Teleph Corp <Ntt> Diagnostic system for synchronous operating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04178037A (ja) * 1990-11-13 1992-06-25 Fujitsu Ltd ディジタル伝送システムのフレーム・フォーマットにおける機能試験方法及び試験回路

Also Published As

Publication number Publication date
JPH0218779B2 (cg-RX-API-DMAC10.html) 1990-04-26

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