JPS59198028A - Phase locked circuit - Google Patents

Abstract

PURPOSE:To prevent the variation of the operating point because of temperature change and vibration or the like by providing a dead band to a charge pump circuit. CONSTITUTION:An output signal frequency f0 of a voltage controlled oscillator 2 and a frequency fR from a reference signal generator 5 are mixed by a mixer 4, and a reference frequency fS is fed to a phase detector 1 and a frequency discriminating circuit 7. The phase detector 1 compares a frequency fi with the reference frequency fS and transmits a DC error voltage corresponding to the phase difference to an analog adder 8. The discriminating circuit 7 gives a signal to a charge pump circuit 6 when the absolute value ¦fi-fS¦ being a difference between the frequency fi and the reference frequency fS is larger than a predetermined value DELTAf, and the circuit 6 increases a control voltage transmitted to the adder 8 by one step's share. Then, even if the input signal frequency fi is parted largely from the reference frequency fS, the circuit 6 traces the frequency fi so as to drive the phase locked loop into the capture range. Moreover, since the dead band DELTAf exists, the operating point is not fluctuated even with temperature change and vibration or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked circuit, and particularly to a phase-locked circuit that expands the capture range and ensures reliable retraction operation, and provides a high-speed, low-noise phase-locked circuit. In order to achieve.

A phase detector using a diode mixer is used. However, when this type of phase detector is used, the capture range is narrow and there is instability in that the phase locked loop cannot be reliably locked due to the linearity of the voltage controlled oscillator. And since it does not have the ability to track frequencies on its own, it has the disadvantage that once it loses its lock, it becomes lost again. Therefore, if the phase-locked loop loses lock, a tracking circuit is installed to track the frequency and bring it within the capture range.
I'm trying to expand the capture range.

FIG. 1 shows a complete example of the configuration of a conventional phase-locked circuit. An input signal with a frequency fi is input to the phase detector 1. In the phase detector 1, the input signal of the frequency fi and the frequency converter 3
The phase is compared with the signal of frequency f8 input from
An error voltage corresponding to the phase difference is output as a control voltage to the voltage controlled oscillator 2. The voltage controlled oscillator 2 has a frequency f according to the error voltage input from the phase detector 1.

The output signal of (fo=fi+fR) is oscillated. The frequency f. is input to the mixer 4 in the frequency converter 3.

The mixer 4 has a frequency f oscillated from the reference signal generator 5.
A signal of R is added, and a reference signal of the frequency of f, H and the f. is mixed with the output signal of frequency f8, and a signal of frequency f8 is output. As shown above, this signal of frequency f8 is applied to the phase detector IK, and the phase detector 1, the voltage controlled oscillator 2, and the frequency converter 3 constitute a phase locked loop. In addition, a charge pump circuit 6 is added in parallel with the phase detector l as a circuit for tracking the frequency described above, and it detects the frequency fi of the input signal that is out of the locking range and the frequency output from the frequency converter 3. An error voltage proportional to the phase difference with the f8 signal is sent to the voltage controlled oscillator 2. Therefore, it will be locked in the phase locked loop. The charge pump circuit 6f: By providing the charge pump circuit 6f, frequencies that are largely outside the locking range are tracked and brought into the capture range, thereby apparently expanding the capture range.

By the way, with such a conventional circuit configuration, the capture range is greatly expanded, but the charge pump circuit 6
Since one unit controls the operation of phase detection, the configuration has two phase detectors, and when the operating point is reached, phase detector 1
There was a drawback that the operating point was not determined, such as when the charge pump circuit 51i111 was used. If the phase of the output signal output from the voltage controlled oscillators 2, 2 changes due to some reason, such as temperature change or shock, the charge pump circuit 6 operates each time, and the operating point shifts. In other words, it responds sensitively to noise.

7hi also has the disadvantage of being sensitive to noise.

The present invention aims to solve the above-mentioned drawbacks, and aims to expand the capture range by tracking and capturing signals at frequencies where the phase-locked loop is out of lock. The purpose of the present invention is to provide a phase synchronization circuit that suppresses the operation as a phase detector and can deal with noise. An embodiment of the present invention will be described below with reference to the drawings from FIG. 2 onwards.

Fig. 2 shows the configuration of an embodiment of the phase-locked circuit according to the present invention, Fig. 3 is a flowchart explaining the basic operation of the phase-locked circuit according to the invention, and Fig. 4 shows an embodiment of the frequency discrimination circuit. Circuit configuration, FIGS. 5 and 6 are time charts of the frequency discrimination circuit, FIG. 7 is an embodiment of the circuit configuration of the charge pump circuit, and FIG. 8.

FIG. 9 shows output waveform diagrams illustrating the output of the charge pump circuit.

In FIG. 2, the numbers 6 to 9 correspond to those in FIG. Reference numeral 7 denotes a frequency discrimination circuit, which is explained in detail in FIG. 8 is an analog adder which adds the error voltage output from the phase detector 1 and the step voltage output from the charge pump circuit 6. , which sends out a control voltage to the voltage controlled oscillator 2.

The operation shown in FIG. 2 will be explained using the flowchart shown in FIG. 3 which explains the basic operation of the phase-locked circuit according to the present invention.

The frequency to be synchronized, that is, the frequency of the output signal, is f
. When set to , the frequency fo of the output signal and the frequency fR from the reference signal generator 5 are mixed by the mixer 4, and the reference frequency f8 is sent to the phase detector 1 and the frequency discrimination circuit 7. On the other hand, an input signal of frequency fi is input to the phase detector 1 and the frequency discrimination circuit 7, and the frequency discrimination circuit 7 determines the absolute difference between the frequency fi of the input signal and the reference frequency fs from the frequency converter 3. value 1 ti-f
It is checked whether sl is larger or smaller than a predetermined frequency Δf.

When the absolute value 1f□-f, l of the difference between the frequency fi of the input signal and the reference frequency fs from the frequency converter 3 is smaller than the predetermined frequency Δf, the phase detection i! , v 1
+Analog adder8. The voltage controlled oscillator 2 and the frequency converter 3 can be locked in a phase-locked loop (hereinafter referred to as phase-locked loop) (with Δf selected as such), and the frequency f. The output signal is oscillated by two voltage controlled oscillators. At this time, the frequency discrimination circuit 7 is outputting logic "0" to the charge pump circuit 6, and the charge pump circuit 6 is not outputting to the analog adder 8.

When the absolute value 1 fi - fs l of the difference between the frequency fi of the input signal and the reference frequency fs from the frequency converter 3 is larger than the predetermined frequency Δf, the phase-locked loop cannot be locked. On the other hand, the frequency discrimination circuit 7 has logic “1”.
" is output to the charge pump circuit 6, which activates the charge pump circuit 6 and
A step voltage as shown in the figure is now applied to the analog adder 8. That is, the control voltage for the voltage controlled oscillator 2 increases or decreases stepwise. This abnormal state is caused by the absolute value If of the difference between the frequency fi of the input signal and the reference frequency fs of the frequency converter 37).
This is repeated until iis l becomes smaller than the frequency Δf.

When I fi −fs l <Δf, the output of the frequency discrimination circuit 7 is inverted to logic "0", and the step voltage output to the analog adder 8 of the charge pump circuit 6 stops increasing or decreasing the number of lamps. let At this time, from the charge pump circuit 6 to the analog adder 8.

The frequency discrimination circuit 7 inverts from logic "1" to logic r01 and continues to output the step voltage at the time when the operation of the charge pump circuit 6 was stopped. That is, voltage B is held in FIG. 8 or 9. Therefore, the phase-locked loop is again within the capture range, so that it can be locked using the error voltage of the phase detector 1 as described above. That is, the frequency f of the input signal
Even if i and the reference frequency fs from the frequency converter 3 deviate greatly, it is possible to track the frequency fit and bring the phase-locked loop within the capture range. As can be seen from the above description, the charge pump circuit 6 has a dead zone of ±Δf, so it will not operate due to shocks such as temperature changes or vibrations, and therefore the operating point will not fluctuate. do not have.

Specific example of the frequency discrimination circuit 7 that operates the charge pump circuit 6 when the absolute value I fi - fs I of the difference between the frequency fi of the input signal and the reference frequency f8 from the frequency converter 3 becomes larger than Δf will be explained next.

In FIG. 4, an input signal of frequency fi is input from terminal 9 to the D terminal of first D-type flimp float circuit 11, and a signal of reference frequency fs is input from terminal 10 to its OK (clock) terminal. The first D-type flip-flop circuit 11 serves as a digital mixer that takes out a frequency difference signal of the difference between the input frequency fi and the reference frequency f8. First D-type slip float circuit 1
The pulse signal corresponding to the difference frequency outputted from 1 is input to the AND circuit 13, and the width T is determined by taking into account the time constants of the resistor 15 and the capacitor 16.

The signal is input to a first monomultipipulator circuit 14 which generates a pulse. The noise ξ output from the first mono-multivibrator circuit 14 is sent to the D terminal of the second D-type flip-flop circuit 17. A second monomultivibrator circuit 1 that generates a noggle with a width T2 determined by the time constant of a resistor 19 and a capacitor 20
From the ζ terminal of 8, the norm of the width T is the second D
It is sent to the OK terminal of the type flip-flop circuit 17, and at the same time, it is also sent to the AND circuit 13, and its output is the second
This is the trigger signal for the mono-multi-twitch mibrator circuit 18.

Now, the time constant of the resistor 15 and capacitor 16 which determines the voltage pulse width T+k of the first mono-multivibrator circuit 14 is τ1. The time constant of the resistor 19 and capacitor 20 that determines the noggle width T of the second mono-multivibrator circuit 18 is τ2=τ, +Δτ (Δτ>0), IA.

Select the slope Δf. Note that here, τ, T, and τ,
and T are almost equal, so below τ, #T1 and τ@ slope T
I will proceed with the explanation as follows. Therefore, consider T, = T, 1 ΔT (ΔT>0) and 17(T, +T, ) #Δf.

First D-type lip flop circuit 11, terminals 9 and 10
The difference between the frequency fi input to the reference frequency f and the reference frequency f
When l-fs l is less than 1/4II+, the operation shown in FIG. 5 is performed. That is, the first D-type flip 7
WT1) of the nozzle signal output from the Nichitsubu circuit 11)
The trigger is applied to the first mono-multivibrator circuit 14. In response to this, the first monomultiplier circuit 14 generates all pulses having a width T+fr and sends them to the D terminal of the second D-type flip-flop circuit 17. On the other hand, the AND circuit 13 inverts the logic from the logic "1" to the logic rOJK in response to the output of the pulse signal output from the first D-type fritz bronze circuit ll, and triggers the second mono-multi pie break circuit 18. Multiply. As a result, the second monomulti-tube mibrator circuit 18 has a width T.

This ξ pulse is inverted with respect to the nogle output from the first mono-multi-tube mibrator circuit 14), and it is sent to the second D-type flip-flop circuit 17. Send 9 to the OK terminal and AND circuit 13. By the way, as explained above, the time constant τ, <τ, (that is, T, (T,) [the difference between the frequency fi of the selected input signal input to the terminal 9 and the reference frequency f8 is TI < 1 / (fi - fs), the operation timing is such that logic "1" is always input to the OK terminal after the D terminal of the second D-type flip-flop circuit 17 becomes logic "0". , the second D-type flip-flop circuit 17 never outputs a logic "1" determination signal.

The input signal of frequency fi input to terminal 9 is 1/T.
, when the error is large, the operation shown in FIG. 6 is performed. That is, within the pulse width T1 of the pulse output from the first mono multivibrator circuit 14, a trigger signal that completely fails to trigger the mono multivibrator circuit 14 of the ml is sent one after another from the 117) D-type slip 70 tube circuit 11. Therefore, the first monomalte pisolator circuit 11-j continues to output the logic rlJ as shown in FIG. Therefore, the logic "rl" is input to the D terminal of the second D-type flip-flop circuit 17. On the other hand, since a trigger is applied to the second mono multi-tub mibrator circuit 18 through the AND circuit 13t-, the node ξ having the width Tz'e is the OK terminal of the second D-type 7-ring 70-tub circuit 17. and the second D-type flip-flop circuit 17
The OK terminal of is inverted from logic "0" to logic "1". This causes the second D-type fritz-flop circuit 17 to have a logic r
A determination signal of lJ is output. The D terminal is still logic “
Since the month continues to be input, the logic "l" in this output is maintained over time.

When the difference 1 ft - fs l between the frequency fi inputted to the terminal 9Vc and the reference frequency f8 becomes smaller than 17T, the output of the second Dffl flip-pun Ronzo circuit 17 changes from logic "1" to logic "0". Perform the action of reversing.

Although the above explanation describes the case where the frequency fl input to the terminal 9 is changed, the same applies to the case where the reference frequency f input to the terminal lO is changed, and the first D The operation shown in FIG. 5 or 6 depends on the relationship between the period of the pulse signal output from the current flip-front circuit 11 and the pulse width T1 output from the first mono-multivibrator circuit 14. and the output signal will be obtained.

In this way, it is possible to determine whether the absolute value 1 fi -f81 of the difference between the two frequencies fi and f8 is greater or less than the preset frequency Δf, and the corresponding logic "l" or "0" is obtained.

Therefore, it can be applied to activate other equipment when the difference between two frequencies becomes larger than a predetermined value. Note that for the input signal to the D terminal of the first D-type fringe flop circuit 11, a duty of 50 channels is normally desirable for operation.
It is not limited to that. If the frequency is too high, connect the terminals 9 and 10 and the first D-type lip flop circuit 1.
A tree scaler may be connected between the D terminal and the CK terminal of the tube 1 to lower the frequency and then input to the D-type flip-flop circuit 11 of the tube 1 for use.

As explained in FIG. 4, when the absolute value 1 fi - fs I of the difference between the frequency fi of the input signal and the reference frequency fs from the frequency converter 3 increases by Δf in the frequency discrimination circuit 7, the logic becomes "1". is output, and the charge pump circuit 6 is activated. Next, the charge iginzo circuit 6 will be explained.

FIG. 7 shows the circuit configuration of an embodiment of the charge pump circuit, and when l fi −f, l becomes larger than Δf, a logic “1” is input to the clock generation circuit 21.

The clock generation circuit 21 is a circuit including, for example, a NAND circuit 22 having hysteresis, a resistor 23 that determines an oscillation frequency, and a capacitor 24. The clock oscillated from the clock generation circuit 21 is input to the slump counter 26 when the logic "1" input to the NAND circuit 22 is inverted to logic "0" and the clock is stopped.
Information provided to prevent the advancement of
The data is inputted via the counter 25 to a hexadecimal counter 26, for example. The counter 26 changes its output terminals A, B, O, and D one after another when the clock is input, and outputs the output to the adder 27. The adder 27 includes resistors 28 to 31 . which perform weighting. Operational amplification'i! 932° foot resistance 3
3 and an offset variable resistor 34. Each time a clock is input to the counter 26, a step voltage is sequentially outputted to the output terminal of the adder 27, as shown in FIG.

Now, the absolute value of the difference between the frequency fi of the input signal and the reference frequency f8 from the frequency converter 3 is 1 ft - f, and I is Δf
When the frequency becomes smaller, the output of the 1-frequency discrimination circuit 7 becomes logic “0”.
”, and the clock generation circuit 21 is stopped. Therefore, the output of the adder 27, which until now has increased the voltage by one step each time a clock is input, is now equal to the logic "0".
'', the step WE, for example, the voltage E in FIG. 8, is maintained as it is. And the above l fi
-fs l is Δf'f: When the output of the exceeding frequency discrimination circuit 7 comes to output logic "1", the output of the adder 27 increases the voltage stepwise from the voltage E again.

FIG. 9 shows an output voltage waveform when the counter 26 in FIG. 7 is replaced with an up-down counter, and the phase-locked loop shown in FIG. 2 fails to lock on the upper voltage side. In this case, locking can be achieved more quickly than in the case of the output voltage waveform shown in the 8th i+ diagram.

As explained above, according to the present invention, since the original phase detector has a capture range of Δf, it is possible to lock by the phase detection gain within this range, and the charge 2 insulator circuit does not operate. It has a dead zone,
The operating point becomes stable. MatashiΔf! If the voltage deviates significantly, the charge pump circuit tracks that frequency and drives it into the capture range, maintaining that voltage.The phase detector can then lock onto any subsequent frequency fluctuations, improving sensitivity. The upper capture range is apparently expanded. Furthermore, since the above-mentioned dead zone is provided, the operating point will not fluctuate due to shocks such as temperature changes or vibrations. Then, the pull-in of the phase locked circuit becomes reliable.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of a conventional phase-locked circuit. Figure 2 shows the configuration of an embodiment of the phase locked circuit according to the present invention.
Figure 3 is a flowchart that clearly explains the basic operation of the phase-locked circuit according to the present invention, Figure 4 is the circuit configuration of an embodiment of the frequency discrimination circuit, and Figures 5 and 6 are the times of the frequency discrimination circuit. The chart, FIG. 7, shows the circuit configuration of an embodiment of the charge pump circuit, and FIG. 8 shows it. FIG. 9 shows output waveform diagrams illustrating the output of the charge pump circuit. In the figure, 1 is a phase detector, 2 is a voltage controlled root generator, 3 is a frequency converter, 4 is a mixer 55 is a reference signal generator, 6 is a charge pump circuit, 7 is a frequency discrimination circuit, and 8 is an analog adder , 9.10 is a terminal, 11 is a first D-type flimp float circuit, 13 is an AND circuit, 14 is a first monomultivibrator circuit, 15 is a resistor, 16 is a capacitor, 1
7 is a second D-type lip frontozo circuit, 18 is a second mono multivibrator circuit, 19 is a resistor, 20 is a capacitor, 21 is a clock generation circuit, 22 is a NAND circuit, 2
3 is a resistor, 24 is a capacitor, 25 is an inverter, 26
is a counter, 27 is an adder, 28 is l/'IL31,3
3tj represents a resistor, 32 represents an operational amplifier, and 34 represents a variable resistor. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 The night of 17 Figure 9

Claims (2)

[Claims] (1) The frequency fi of the input signal is input to the two-phase detector by going to the phase locked circuit, which is completely composed of a closed loop consisting of a phase detector, a voltage controlled oscillator, and a frequency converter, and the frequency fi of the input signal is input from the frequency converter to the phase detector. Frequency f. a frequency discrimination circuit that outputs a discrimination signal when the difference 1 ft - f81 from 1 ft - f81 is equal to or higher than a predetermined frequency Δf; and a charge pump circuit that holds the voltage of four times the voltage at that step when the frequency discrimination circuit is not outputting the discrimination signal; A phase synchronized circuit comprising an analog adder that performs full addition with a phase difference voltage and voltage-controls the voltage-controlled oscillator. (2) The frequency discrimination circuit includes a first D-type flimp 70 amplifier circuit in which an input signal of 9 frequencies fi is input to a D terminal, and a signal of a frequency f is input to an OK terminal;
a first mono-multi-twist break circuit which uses the output of the D-type slip-flop circuit as a trigger signal to generate a pulse with a width T1 equal to the period of the predetermined frequency Δf; width Tt (T2>T, ); a second mono multi-twitch break circuit that generates a nozzle; the pulse outputted from the second mono multi-tsum break circuit and the output signal of the first D-type lip flop circuit are respectively inputted; , an AND circuit that sends a trigger signal to the second monomultivibrator circuit;
The zth mono multivibrator circuit is output to the terminal. and a second D-type flip 70 tube circuit in which the input signals of e signals are respectively input to the OK terminals, and the frequency difference Hi-fsl between the input signal of frequency fi and the signal of frequency f8 is determined by a predetermined frequency Δf (Δf 1. The phase synchronized circuit according to claim 1, wherein the logic level of the 7 lip-flop circuit @2 is completely inverted and outputted at the boundary of =1./i'1).