JPH04105729U - PLL circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To eliminate fluctuations in the steady phase error between the reference clock pulse and the feedback clock pulse created by the oscillator due to factors such as fluctuations in the oscillation frequency of the oscillator. [Structure] In addition to the proportional control type PLL, the phase difference between the input reference clock pulse and the feedback clock pulse created from the output of the voltage controlled oscillator 6 is monitored by the phase comparator 9, and the error voltage is determined according to this phase difference. Low pass filter 10, amplifier 1
1, and the error voltage changes the limiter waveform in the PLL, that is, the amplitude of the output of the analog switch 3, to an amplitude corresponding to the error voltage.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

TECHNICAL FIELD The present invention relates to a PLL circuit, and particularly to control of steady phase fluctuations.

0002

[Conventional technology]

FIG. 3 shows the configuration of a conventional PLL circuit. A conventional PLL circuit has a reference clock pulse input terminal 1 and a phase comparator (PC). 2, limiter amplifier 3', low-pass filter 4, amplifier 5, and voltage controlled oscillator. (VCO) 6, an output terminal 7, and an N frequency divider circuit 8.

The voltage controlled oscillator 6 oscillates with a center frequency N times the reference clock frequency f _s of the reference clock pulse supplied to the reference clock pulse input terminal 1 . The output of this voltage controlled oscillator 6 is fed back to the phase comparator 2 via an N frequency divider circuit 8 at a feedback frequency f _o that is approximately the same as the reference clock frequency f _s .

A reference clock pulse (reference clock frequency f _s ) input to a reference clock pulse input terminal 1 is supplied to a phase comparator 2 . The phase comparator 2 compares the phases of this input reference clock pulse with a feedback clock pulse having a feedback frequency _fo obtained by dividing the output of the voltage controlled oscillator 6 by N. The output of the phase comparator 2 passes through a limiter amplifier 3' and a low-pass filter 4 to generate an error voltage Ve corresponding to the difference between the two frequencies whose phases have been compared. The error voltage Ve passes through the amplifier 5 and controls the voltage controlled oscillator 6 in a DC manner. 1

The error voltage Ve controls the voltage controlled oscillator 6 so that the output frequency N×f _o of the voltage controlled oscillator 6 decreases the difference between the feedback frequency f _o and the reference clock frequency f _s . Therefore, if the feedback frequency f _o and the input reference clock frequency f _s are sufficiently close, the feedback frequency f _o will be locked to the input reference clock frequency f _s and the frequency and phase difference will disappear. That is, a signal having an output frequency N times the frequency f _s of the input reference clock pulse appears at the output terminal 7.

[0006]

[Problem that the idea aims to solve]

In the conventional PLL circuit described above, fluctuations in the steady phase error occur due to factors such as fluctuations in the oscillation frequency N×f _o of the voltage controlled oscillator 6. The only way to reduce this variation in steady phase error is to improve the oscillation frequency accuracy of the voltage controlled oscillator 6, or, if a voltage controlled oscillator 6 with good oscillation frequency accuracy cannot be obtained, increase the loop gain. do not have. Therefore, the worse the oscillation frequency accuracy of the voltage controlled oscillator 6, the larger the loop gain needs to be. When the loop gain is increased, the response speed of the system increases accordingly, and jitter transfer characteristics deteriorate, making it difficult to always obtain a stable clock.

[0007] The purpose of this invention is to provide a PLL circuit that can eliminate fluctuations in steady phase error. It's about doing.

[0008]

[Means to solve the problem]

The PLL circuit of the present invention operates using the output of the first phase comparator as a control signal, and Input the (+) reference voltage and (-) reference voltage to each of the two contacts, and from the output The limit with the (+) reference voltage at “H” level and the (-) reference voltage at “L” level. In addition to the analog switch that obtains the data waveform and the first phase comparator, there is one other base. Phase difference between the quasi-clock pulse and the clock pulse created from the output of the voltage-controlled oscillator A second phase comparator monitors the phase difference, and generates an error voltage according to the phase difference. A circuit that changes the (+) reference voltage to a voltage according to the error voltage using the error voltage. It has

[0009]

【Example】

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a PLL circuit according to an embodiment of the present invention. The PLL circuit of this embodiment has an analog switch 3 instead of a limiter amplifier 3'. It further includes a phase comparator 9, a low-pass filter 10, an amplifier 11, and a reference voltage generator. (+ side) 12, voltage follower 13, reference voltage generator (- side) 14, and adder 15 The configuration is similar to that shown in FIG. 3, except that it has a configuration similar to that shown in FIG. Therefore, Components having the same functions as the PLL circuit in FIG. 3 are given the same reference numerals, and The explanation of is omitted.

FIG. 2A shows that a steady phase error occurs in a PLL (configuration equivalent to a conventional PLL circuit) composed of phase comparator 2 → voltage controlled oscillator 6 → N frequency divider 8 → phase comparator 2. An example of the waveform when it is not visible is shown. At this time, if the phase comparator 2 is a set/reset type, the phase relationship between the input reference clock pulse C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 by N is shown in FIG. 2(A). It will be like that. The output of the phase comparator 2 (PC _o in FIG. 2(A)) is then supplied to the control input of the analog switch 3 . In order to operate the analog switch 3, a reference voltage V- generated from a reference voltage generator 14 inputted to two contacts of the switch in the analog switch 3 and a reference voltage generated from the reference voltage generator 12 via a voltage follower 13 are used. A repetitive waveform of the reference voltage V+ appears at the output of the analog switch 3 (LIMO in FIG. 2(A)). The average value V _o of the output of the analog switch 3 is detected by the low-pass filter 4 . This average value V _o is fed via an amplifier 5 to a control input of a voltage controlled oscillator 6 . This locks the PLL. At this time, no steady phase error occurs between the input reference clock pulse C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 by N. Therefore, no error voltage Ve is generated via the phase comparator 9, low-pass filter 10, and amplifier 11. Therefore, the reference voltage V+ generated from the reference voltage generator 12 is supplied to the input of the analog switch 3 as is. As a result, the phase becomes stable as shown in FIG. 2(A).

In FIG. 2(B), in a PLL composed of phase comparator 2→voltage controlled oscillator 6→N frequency divider 8→phase comparator 2, due to factors such as fluctuations in the center frequency of voltage controlled oscillator 6, In order to make the frequency of the reference clock pulse input C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 equal to N, and to lock the PLL, a voltage of V _o +ΔV is applied to the control input of the voltage controlled oscillator 6. An example waveform is shown when . At this time, the phase of the input reference clock pulse C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator ₆ by N is adjusted as shown in FIG. The phase relationship is as shown in (B), and a steady phase error occurs. The phase error between the input reference clock pulse C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 by N is detected by a phase comparator 9 and passed through a low-pass filter 10 and an amplifier 11 to the input reference clock pulse. An error voltage Ve is generated according to the phase difference between C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 by N. This error voltage Ve is added by an adder 15 to the reference voltage V + generated from the reference voltage generator 12 . A voltage obtained by adding the error voltage Ve and the reference voltage V+ generated from the reference voltage generator 12 by the adder 15 is supplied directly to one side of the switch contact of the analog switch 3 via the voltage follower 13. Therefore, the amplitude of the output LIMO of the analog switch 3 changes as shown in FIG. 2(C).

While the PLL is locked, the output of the voltage controlled oscillator 6 is divided into N parts so that the average value V _o +ΔV of the waveform of the output LIMO of the analog switch 3 in FIG. 2(C) is always constant. The phase of the cycled feedback clock pulse C _o is controlled. As a result, as shown in FIG. 2C, the phase difference between the input reference clock pulse C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 by N is reduced. In the end, the error voltage V e corresponding to the phase difference between the input reference clock pulse C _s detected by the phase comparator 9 and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 by N is the input reference clock pulse It acts in the direction of reducing the phase difference between C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 by N. As a result, the input reference clock pulse C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 by N have the same phase relationship as shown in FIG. 2(A). This makes it possible to eliminate a steady phase error between the input reference clock pulse C _s and the feedback clock pulse C _o obtained by dividing the output of the voltage controlled oscillator 6 by N.

[0013] However, the phase comparator 2→voltage controlled oscillator 6→N frequency divider 8→phase comparator 2 phase comparator 9 → voltage follower 13 → voltage controlled oscillator 6 → N frequency divider circuit 8 → phase It is necessary to avoid contention with the comparator 9 loop. Therefore, these two loops The response of A constant is set.

[0014]

[Effect of the idea]

As explained above, the present invention combines the input reference clock pulse and the output of the voltage controlled oscillator. The phase difference of the feedback clock pulse created from the input signal is monitored, and the error is calculated according to this phase difference. A voltage is generated, and this error voltage is used to set the limit before detecting the average value in the PLL. It controls the amplitude of the data waveform and cancels out the steady phase error caused by the PLL. Therefore, the loop gain is increased more than necessary to reduce the steady-state phase error. It is possible to eliminate steady-state phase errors and always obtain stable clock pulses. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of waveforms of the PLL circuit of FIG. 1;

FIG. 3 is a block diagram of a conventional PLL circuit.

[Explanation of symbols]

1 Reference clock pulse input terminal 2 Phase comparator (PC) 3 Analog switch 4 Low pass filter 5 Amplifier 6 Voltage controlled oscillator (VCO) 7 Output terminal 8 N frequency divider circuit 9 Phase comparator (PC) 10 Low pass filter 11 Amplifier 12 Reference voltage generator (V+) 13 Voltage follower 14 Reference voltage generator (V-) 15 Adder

Claims (3)

[Scope of utility model registration request] 1. Means (9) for monitoring a phase difference between an input reference clock pulse (C _s ) and a feedback clock pulse (C _o ) produced from a voltage controlled oscillator (6); Means (10, 1) for generating an error voltage (Ve)
1), and means (13, 15) for changing the amplitude of the limiter waveform at the stage before average value detection in the PLL by the error voltage (Ve) to an amplitude corresponding to the error voltage (Ve).
A PLL circuit comprising: Claim 2: Operates using the output of the first phase comparator (2) as a control signal, and inputs a (+) reference voltage (V+) and a (-) reference voltage (V-) to the two contacts, respectively. and an analog switch (3) that obtains a limiter waveform with the (+) reference voltage at "H" level and the (-) reference voltage at "L" level from the output, and an input reference clock pulse (C _s ).
and a second phase comparator (9) that monitors the phase difference between the feedback clock pulse (C _o ) created from the output of the voltage controlled oscillator (6) and the output of the voltage controlled oscillator (6), and generates an error voltage (Ve) according to the phase difference. and means (10, 11, 13, 15) for changing the (+) reference voltage (V+) to a voltage according to the error voltage (Ve) using the error voltage (Ve). PLL circuit. 3. A first phase comparator (2) that compares the phases of an input reference clock pulse (C _s ) and a feedback clock pulse (C _o ) and outputs a phase comparison result signal, and the phase comparison result signal an analog switch (3) for obtaining a limiter waveform with the (+) reference voltage at "H" level and the (-) reference voltage at "L"level; and detecting the average value of the limiter waveform. average value detection means (4, 5) for outputting a control voltage; a voltage controlled oscillator (6) for outputting an output clock pulse in response to the control voltage; a second phase comparator (9) for detecting a phase error between said input reference clock pulse (C _s ) and said feedback clock pulse ( _{C o )} ; Means (10, 11) for generating an error voltage (Ve) according to
and means (13, 15) for changing the (+) reference voltage (V+) to a voltage according to the error voltage (Ve) using the error voltage (Ve).
LL circuit.